2026-03-02 01:31:26.099 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.40.20:5700'
2026-03-02 01:31:26.100 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.40.20:5802)
2026-03-02 01:31:26.100 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.40.20:5801)
2026-03-02 01:31:26.100 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.40.22:6700'
2026-03-02 01:31:26.100 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.40.22:6802)
2026-03-02 01:31:26.100 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.40.22:6801)
2026-03-02 01:31:26.100 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.40.20:5700/1'
2026-03-02 01:31:26.100 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.40.20:5804)
2026-03-02 01:31:26.100 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.40.20:5803)
2026-03-02 01:31:26.100 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.40.20:5700/2'
2026-03-02 01:31:26.100 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.40.20:5806)
2026-03-02 01:31:26.100 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.40.20:5805)
2026-03-02 01:31:26.100 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.40.20:5700/3'
2026-03-02 01:31:26.100 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.40.20:5808)
2026-03-02 01:31:26.100 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.40.20:5807)
2026-03-02 01:31:26.100 [INFO] fake_trx.py:429 Init complete
2026-03-02 01:31:26.100 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-02 01:31:27.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:31:27.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:31:27.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:27.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:27.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:27.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:30.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:30.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:31:30.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:30.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:31:30.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 0 -> 1
2026-03-02 01:31:30.757 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:31:30.758 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:31:30.758 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:31:30.758 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:30.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:30.759 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:31:30.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:31:30.760 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 0 -> 1
2026-03-02 01:31:30.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:30.762 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:31:30.762 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:31:30.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:31:30.762 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:30.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:30.763 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:31:30.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:31:30.763 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 0 -> 1
2026-03-02 01:31:30.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:30.765 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:31:30.765 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:31:30.766 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:31:30.766 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:30.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:30.766 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:31:30.766 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:31:30.766 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 0 -> 1
2026-03-02 01:31:30.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:30.768 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:31:30.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:31:30.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:31:30.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:31:30.768 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:31:30.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:31:30.769 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:31:30.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:31:30.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:30.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.769 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:31:30.769 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:31:30.769 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:31:30.770 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:30.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:30.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:30.774 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:31:31.257 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:31:31.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:31.341 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:31:31.344 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:31:31.344 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:31:31.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:31.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:31.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:31.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:31.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:31.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:31.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:31.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:31.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:31.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:31.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:31.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:31.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:31.735 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:31:31.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:31.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:31.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:31.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:31.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:31.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:31.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:31.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:31.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:31.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:31.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:31.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:31.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:31.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:31.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:31.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:31.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:32.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:32.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:32.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:32.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:32.212 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:31:32.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:32.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:32.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:32.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:32.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:32.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:32.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:32.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:32.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:32.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:32.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:32.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:32.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:32.690 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:31:32.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:32.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:32.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:32.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:32.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:32.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:32.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:32.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:33.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:33.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:33.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:33.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:33.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:33.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:33.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:33.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:33.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:33.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:33.167 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:31:33.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:33.231 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:33.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:33.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:33.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:33.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:33.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:33.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:33.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:33.645 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:31:33.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:33.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:33.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:33.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:33.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:33.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:33.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:33.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:33.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:33.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:33.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:33.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:33.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:34.123 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:31:34.601 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:31:34.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:34.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:34.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:34.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:34.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:34.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:34.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:34.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:34.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:34.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:34.687 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:34.687 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:34.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:34.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:34.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:34.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:34.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:34.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:34.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:34.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:34.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:35.078 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:31:35.556 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:31:35.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:35.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:35.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:35.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:35.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:35.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:35.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:35.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:35.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:35.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:35.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:35.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:35.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:35.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:35.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:35.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:35.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:36.034 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:31:36.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:36.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:36.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:36.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:36.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:36.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:36.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:36.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:36.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:36.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:36.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:36.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:36.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:36.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:36.511 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:31:36.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:36.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:36.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:36.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:36.989 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:31:37.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:37.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:37.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:37.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:37.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:37.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:37.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:37.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:37.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:37.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:37.304 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:37.304 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:37.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:37.467 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:31:37.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:37.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:37.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:37.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:37.946 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:31:38.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:38.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:38.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:38.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:38.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:38.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:38.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:38.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:38.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:38.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:38.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:38.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:38.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:38.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:38.422 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:31:38.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:38.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:38.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:38.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:38.900 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:31:39.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:39.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:39.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:39.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:39.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:39.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:39.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:39.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:39.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:39.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:39.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:39.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:39.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:39.377 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:31:39.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:39.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:39.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:39.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:39.855 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:31:40.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:40.202 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:40.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:40.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:40.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:40.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:40.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:40.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:40.225 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:40.225 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:40.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:40.332 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:31:40.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:40.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:40.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:40.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:40.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:40.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:40.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:40.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:40.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:40.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:40.770 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:40.770 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:40.810 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:31:40.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:40.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:40.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:40.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:40.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:40.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:40.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:40.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:40.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:40.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:40.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:40.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:40.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:40.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:41.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:41.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:41.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:41.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.287 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:31:41.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:41.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:41.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:41.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:41.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:41.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:41.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:41.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:41.486 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:41.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:41.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:41.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:41.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:41.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.764 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:31:41.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:41.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:41.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:41.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:41.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:41.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:41.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:41.970 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:41.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:41.970 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:41.970 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:42.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:42.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:42.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:42.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.241 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:31:42.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:42.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:42.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:42.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:42.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:42.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:42.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:42.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:42.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:42.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:42.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:42.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:42.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:42.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:42.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:42.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:42.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:42.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:42.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:42.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:42.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:42.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:42.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:42.718 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:31:42.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:42.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:42.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:42.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:42.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:43.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:43.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:43.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:43.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:43.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:43.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:43.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:43.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:43.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:43.195 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:31:43.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:43.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:43.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:43.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:43.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:43.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:43.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:43.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:43.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:43.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:43.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:43.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:31:43.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:31:43.673 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:31:43.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:43.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:31:43.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:31:43.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:43.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:44.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:31:44.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:44.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:44.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:44.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:44.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:44.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:44.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:44.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:44.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:44.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:44.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:44.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:31:44.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:31:44.141 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:44.141 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:49.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:31:49.147 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:31:49.147 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:49.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:49.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:49.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:49.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:49.157 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:31:49.158 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:49.159 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:31:49.159 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:31:49.163 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:31:49.163 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:31:49.163 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:31:49.163 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:49.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:49.164 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:31:49.164 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:31:49.164 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:31:49.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:49.166 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:31:49.167 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:31:49.167 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:31:49.167 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:49.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:49.168 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:31:49.168 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:31:49.168 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:31:49.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:49.169 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:31:49.169 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:31:49.169 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:31:49.169 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:49.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:49.170 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:31:49.170 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:31:49.170 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:31:49.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.173 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:31:49.173 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:31:49.173 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:31:49.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:49.179 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:31:49.662 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:31:49.699 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:31:49.700 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:31:49.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.701 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:31:49.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:49.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:49.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:49.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:49.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
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2026-03-02 01:31:50.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.132 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:31:50.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:50.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:50.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:50.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:50.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
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2026-03-02 01:31:50.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:50.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:50.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:50.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:50.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:50.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:50.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:50.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:50.385 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:31:50.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:31:50.386 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:31:50.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:50.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:55.391 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:31:55.391 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:31:55.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:55.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:55.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:55.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:55.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:55.399 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:31:55.399 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:55.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:31:55.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:31:55.404 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:31:55.404 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:31:55.404 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:31:55.404 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:55.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:55.405 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:31:55.405 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:31:55.405 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:31:55.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:55.407 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:31:55.407 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:31:55.407 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:31:55.408 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:55.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:55.408 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:31:55.408 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:31:55.408 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:31:55.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:55.410 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:31:55.410 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:31:55.411 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:31:55.411 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:31:55.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:55.411 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:31:55.411 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:31:55.411 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:31:55.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:31:55.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:31:55.415 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:31:55.415 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:31:55.415 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:31:55.420 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:31:55.903 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:31:55.944 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:31:55.945 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:31:55.947 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:31:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:55.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:31:55.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:31:55.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:31:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:55.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:31:55.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:31:55.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:31:55.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:31:55.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:31:55.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:31:55.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:31:55.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:31:55.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:31:55.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:31:55.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:31:55.993 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:31:55.993 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:55.993 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:55.993 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:55.993 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:55.993 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:31:55.994 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:00.990 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:32:00.990 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:32:00.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:00.993 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:00.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:00.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:01.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:01.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:32:01.006 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:01.006 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:32:01.006 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:32:01.009 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:32:01.010 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:32:01.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:32:01.010 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:01.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:01.011 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:32:01.011 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:32:01.011 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:32:01.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:01.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:32:01.012 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:32:01.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:32:01.012 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:01.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:01.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:32:01.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:32:01.013 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:32:01.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:32:01.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:32:01.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:32:01.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:01.017 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:32:01.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:32:01.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:32:01.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:32:01.017 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:32:01.018 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:32:01.018 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:32:01.018 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:01.023 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:32:01.506 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:32:01.543 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:32:01.544 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:32:01.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:01.545 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:32:01.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:01.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:01.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:01.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:01.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:01.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:01.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:01.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:01.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:01.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:01.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:32:01.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:32:01.566 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:32:01.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:01.566 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:01.566 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:01.566 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:01.567 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:01.567 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:01.567 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:01.567 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:06.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:32:06.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:32:06.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:06.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:06.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:06.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:06.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:06.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:32:06.578 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:06.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:32:06.578 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:32:06.580 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:32:06.580 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:32:06.580 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:32:06.580 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:06.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:06.581 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:32:06.581 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:32:06.581 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:32:06.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:06.582 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:32:06.582 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:32:06.582 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:32:06.582 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:06.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:06.582 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:32:06.583 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:32:06.583 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:32:06.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:06.584 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:32:06.584 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:32:06.584 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:32:06.584 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:06.584 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:32:06.584 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:32:06.584 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:32:06.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:06.586 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:32:06.587 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:32:06.587 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:32:06.587 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:06.592 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:32:07.076 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:32:07.115 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:32:07.117 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:32:07.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:07.118 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:32:07.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.202 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.202 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:07.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:07.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:07.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:07.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:07.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:07.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:07.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:07.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:07.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:07.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:32:07.238 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:32:07.238 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:32:07.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:07.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=139 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:32:12.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:32:12.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:32:12.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:12.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:12.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:12.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:12.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:32:12.252 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:32:12.252 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:12.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:32:12.253 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:32:12.255 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:32:12.255 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:32:12.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:32:12.256 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:12.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:32:12.256 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:32:12.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:32:12.256 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:32:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:12.258 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:32:12.258 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:32:12.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:32:12.259 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:12.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:32:12.259 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:32:12.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:32:12.259 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:32:12.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:32:12.261 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:32:12.261 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:32:12.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:32:12.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:32:12.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:32:12.265 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:32:12.265 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:12.270 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:32:12.754 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:32:12.792 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:32:12.793 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:32:12.793 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:32:12.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:12.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:12.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:12.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:12.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:12.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:12.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:12.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:12.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:12.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:12.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:12.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:12.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:12.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:12.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:13.229 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:32:13.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:13.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:13.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:13.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:13.706 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:32:14.184 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:32:14.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:14.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:14.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:14.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:14.662 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:32:15.140 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:32:15.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:15.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:15.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:15.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:15.618 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:32:16.096 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:32:16.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:16.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:16.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:16.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:16.574 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:32:16.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:16.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:16.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:16.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:16.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:16.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:16.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:16.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:16.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:16.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:16.982 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:16.982 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:16.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:16.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:16.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:16.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:16.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:17.052 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:32:17.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:32:17.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:32:17.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:17.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:32:17.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:32:17.530 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:32:18.008 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:32:18.486 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:32:18.964 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:32:19.442 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:32:19.919 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:32:20.397 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:32:20.874 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:32:21.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:21.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:21.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:21.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:21.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:21.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:21.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:21.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:21.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:21.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:21.299 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:21.299 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:21.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:21.351 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:21.351 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:21.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:21.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:21.352 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:32:21.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:21.830 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:32:22.307 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:32:22.785 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:32:23.262 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:32:23.740 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:32:24.217 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:32:24.695 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:32:25.173 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:32:25.650 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:32:25.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:25.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:25.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:25.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:25.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:25.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:25.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:25.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:25.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:25.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:25.808 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:25.808 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:25.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:25.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:25.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:25.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:25.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:26.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:26.128 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:32:26.605 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:32:27.082 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:32:27.560 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:32:28.037 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:32:28.515 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:32:28.993 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:32:29.471 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:32:29.949 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:32:30.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:30.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:30.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:30.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:30.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:30.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:30.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:30.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:30.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:30.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:30.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:30.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:30.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:30.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:30.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:30.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:30.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:30.426 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:32:30.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:30.903 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:32:31.382 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:32:31.860 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:32:32.337 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:32:32.815 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:32:33.293 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:32:33.770 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:32:34.248 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:32:34.726 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:32:34.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:34.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:34.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:34.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:34.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:34.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:34.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:34.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:34.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:34.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:34.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:34.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:34.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:34.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:34.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:34.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:34.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:35.203 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:32:35.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:35.680 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:32:36.158 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:32:36.636 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:32:37.114 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:32:37.593 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:32:38.070 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:32:38.548 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:32:39.025 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:32:39.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:39.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:39.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:39.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:39.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:39.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:39.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:39.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:39.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:39.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:39.244 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:39.244 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:39.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:39.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:39.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:39.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:39.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:39.503 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:32:39.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:39.980 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:32:40.458 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:32:40.936 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:32:41.414 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:32:41.892 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:32:42.370 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:32:42.847 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:32:43.325 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:32:43.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:43.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:43.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:43.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:43.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:43.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:43.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:43.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:43.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:43.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:43.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:43.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:43.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:43.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:43.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:43.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:43.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:43.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:43.801 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:32:44.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:44.280 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:32:44.757 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:32:45.236 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:32:45.713 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:32:46.191 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:32:46.669 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 01:32:47.147 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 01:32:47.625 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 01:32:48.103 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 01:32:48.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:48.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:48.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:48.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:48.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:48.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:48.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:48.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:48.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:48.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:48.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:48.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:48.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:48.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:48.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:48.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:48.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:48.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:48.581 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 01:32:49.060 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 01:32:49.538 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 01:32:50.016 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 01:32:50.494 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 01:32:50.972 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 01:32:51.451 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 01:32:51.929 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 01:32:52.407 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 01:32:52.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:52.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:52.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:52.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:52.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:52.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:52.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:52.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:52.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:52.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:52.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:52.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:52.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:32:52.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:52.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:52.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:52.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:52.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:52.884 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 01:32:53.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:53.362 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 01:32:53.839 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 01:32:54.317 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 01:32:54.795 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 01:32:55.273 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 01:32:55.751 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 01:32:56.228 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 01:32:56.706 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 01:32:57.184 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 01:32:57.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:57.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:57.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:57.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:57.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:32:57.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:32:57.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:32:57.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:57.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:57.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:57.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:32:57.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:32:57.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:57.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:32:57.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:32:57.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:57.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:32:57.661 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 01:32:58.139 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 01:32:58.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:32:58.618 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 01:32:59.096 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 01:32:59.574 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 01:33:00.052 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 01:33:00.530 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 01:33:01.009 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 01:33:01.487 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 01:33:01.965 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 01:33:02.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:02.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:02.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:02.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:02.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:02.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:02.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:02.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:02.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:02.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:02.263 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:02.263 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:02.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:02.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:02.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:02.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:02.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:02.443 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 01:33:02.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:02.921 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 01:33:03.399 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 01:33:03.877 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 01:33:04.355 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 01:33:04.833 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 01:33:05.311 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 01:33:05.790 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 01:33:06.268 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 01:33:06.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:06.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:06.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:06.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:06.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:06.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:06.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:06.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:06.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:06.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:06.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:06.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:06.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:06.745 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 01:33:06.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:06.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:06.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:06.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:06.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:07.222 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 01:33:07.700 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 01:33:08.178 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 01:33:08.655 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 01:33:09.134 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 01:33:09.611 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 01:33:10.089 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 01:33:10.568 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 01:33:10.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:10.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:10.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:10.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:10.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:10.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:10.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:10.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:10.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:10.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:10.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:10.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:10.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:10.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:10.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:10.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:11.045 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 01:33:11.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:11.523 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 01:33:12.001 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 01:33:12.479 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 01:33:12.957 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 01:33:13.435 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 01:33:13.912 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 01:33:14.391 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 01:33:14.869 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 01:33:15.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:15.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:15.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:15.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:15.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:15.243 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:15.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:15.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:15.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:15.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:15.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:15.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:15.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:15.299 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:15.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:15.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:15.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:15.346 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 01:33:15.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:15.824 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 01:33:16.301 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 01:33:16.779 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 01:33:17.257 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 01:33:17.734 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 01:33:18.212 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 01:33:18.690 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 01:33:19.167 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 01:33:19.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:19.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:19.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:19.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:19.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:19.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:19.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:19.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:19.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:19.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:19.566 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:19.566 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:19.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:19.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:19.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:19.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:19.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:19.645 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 01:33:19.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:20.122 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 01:33:20.600 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 01:33:21.077 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 01:33:21.555 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 01:33:22.032 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 01:33:22.510 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 01:33:22.988 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 01:33:23.465 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 01:33:23.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:23.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:23.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:23.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:23.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:23.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:23.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:23.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:23.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:23.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:23.883 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:23.883 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:23.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:23.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:23.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:23.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:23.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:23.942 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 01:33:24.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:24.420 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 01:33:24.897 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 01:33:25.375 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 01:33:25.852 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 01:33:26.330 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 01:33:26.808 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 01:33:27.285 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 01:33:27.763 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 01:33:28.241 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 01:33:28.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:28.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:28.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:28.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:28.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:28.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:28.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:28.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:28.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:28.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:28.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:28.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:28.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:28.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:28.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:28.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:28.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:28.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:28.717 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 01:33:29.195 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 01:33:29.673 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 01:33:30.151 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 01:33:30.629 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 01:33:31.107 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 01:33:31.585 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 01:33:32.064 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 01:33:32.542 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 01:33:32.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:32.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:32.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:32.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:32.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:32.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:32.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:32.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:32.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:32.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:32.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:32.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:32.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:32.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:32.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:32.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:32.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:32.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:33.020 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 01:33:33.498 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 01:33:33.975 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 01:33:34.453 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 01:33:34.931 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 01:33:35.409 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 01:33:35.887 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 01:33:36.365 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 01:33:36.843 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 01:33:36.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:36.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:36.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:36.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:36.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:36.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:36.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:36.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:36.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:36.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:36.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:36.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:37.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:37.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:37.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:37.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:37.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:37.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:37.320 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 01:33:37.798 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 01:33:38.276 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 01:33:38.753 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 01:33:39.231 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-02 01:33:39.709 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-02 01:33:40.186 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-02 01:33:40.664 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-02 01:33:41.141 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-02 01:33:41.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:41.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:41.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:41.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:41.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:41.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:41.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:41.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:41.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:33:41.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:33:41.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:33:41.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:33:41.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:33:41.298 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:33:41.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:33:46.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:33:46.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:33:46.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:33:46.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:33:46.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:33:46.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:33:46.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:33:46.311 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:33:46.311 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:46.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:33:46.312 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:33:46.313 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:33:46.314 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:33:46.314 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:33:46.314 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:46.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:33:46.315 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:33:46.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:33:46.315 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:33:46.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:46.316 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:33:46.316 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:33:46.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:33:46.316 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:46.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:33:46.317 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:33:46.317 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:33:46.317 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:33:46.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:33:46.319 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:33:46.319 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:33:46.319 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:46.322 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:33:46.322 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:33:46.322 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:33:46.323 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:33:46.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:46.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:46.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:33:46.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:33:46.324 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:46.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:33:51.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:33:51.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:33:51.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:33:51.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:33:51.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:33:51.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:33:51.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:33:51.340 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:51.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:33:51.341 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:33:51.343 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:33:51.343 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:33:51.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:33:51.344 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:51.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:33:51.345 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:33:51.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:33:51.345 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:33:51.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:51.346 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:33:51.346 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:33:51.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:33:51.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:51.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:33:51.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:33:51.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:33:51.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:33:51.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:51.348 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:33:51.348 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:33:51.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:33:51.348 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:33:51.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:33:51.349 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:33:51.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:33:51.349 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:33:51.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:33:51.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:33:51.352 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:33:51.352 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:33:51.352 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:51.357 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:33:51.841 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:33:51.874 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:33:51.875 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:33:51.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:51.876 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:33:51.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:51.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:51.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:51.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:51.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:51.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:51.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:51.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:51.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:51.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:51.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:51.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:51.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:52.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:52.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:52.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:52.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:52.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:52.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:52.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:52.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:52.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:52.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:52.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:52.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:52.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.316 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:33:52.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:52.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:52.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:52.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:52.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:52.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:52.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:52.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:52.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:52.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:52.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:52.557 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:52.557 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:52.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:52.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:52.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:52.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:52.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:52.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:52.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:52.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:52.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:52.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:52.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:52.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:52.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:52.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:33:52.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:52.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:52.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:52.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:52.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:53.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:53.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:53.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:53.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:53.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:53.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:53.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:53.263 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:53.263 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:53.271 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:33:53.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:53.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:53.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:53.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:53.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:53.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:53.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:53.748 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:33:53.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:53.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:53.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:53.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:53.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:53.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:53.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:53.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:53.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:53.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:53.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:53.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:53.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:53.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:53.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.225 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:33:54.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:54.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:54.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:54.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:54.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:54.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:54.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:54.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:54.354 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:54.354 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:54.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:54.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:54.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:54.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:54.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:54.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:54.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:54.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.701 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:33:54.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:54.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:54.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:54.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:54.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:54.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:54.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:54.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:54.901 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:54.901 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:54.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:54.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:54.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:54.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:54.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:54.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.179 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:33:55.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:55.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:55.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:55.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:55.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:55.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:55.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:55.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:55.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:55.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:55.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:55.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:55.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:55.443 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:55.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:55.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:55.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.657 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:33:55.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:55.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:55.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:55.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:55.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:55.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:55.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:55.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:55.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:55.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:55.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:56.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:33:56.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:56.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:56.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:56.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:56.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:56.135 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:33:56.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:33:56.359 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:33:56.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:33:56.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:33:56.613 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:33:56.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:56.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:56.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:56.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:56.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:56.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:56.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:56.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:56.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:56.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:56.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:56.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:56.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:56.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:56.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:56.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:56.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.091 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:33:57.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:57.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:57.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:57.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:57.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:57.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:57.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:57.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:57.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:57.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:57.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:57.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:57.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:57.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.569 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:33:57.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:57.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:57.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:57.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:57.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:57.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:57.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:57.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:57.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:57.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:57.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:57.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:57.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:57.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:57.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.046 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:33:58.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:58.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:58.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:58.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:58.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:58.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:58.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:58.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:58.226 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:58.226 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:58.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:58.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:58.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:58.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.523 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:33:58.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:58.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:58.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:58.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:58.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:58.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:58.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:58.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:58.713 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:58.713 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:58.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:58.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:58.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:58.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:58.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.001 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:33:59.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:59.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:59.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:59.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:59.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:59.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:59.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:59.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:59.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:59.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:59.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:59.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:59.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:59.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.477 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:33:59.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:59.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:59.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:59.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:59.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:59.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:59.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:59.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:59.713 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:59.713 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:59.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:59.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:59.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:59.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:59.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:59.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:59.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:33:59.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:33:59.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:33:59.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:59.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:59.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:33:59.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:33:59.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:33:59.953 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:33:59.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:33:59.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:33:59.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:33:59.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:00.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:00.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:00.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:00.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:00.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:00.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:00.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:00.387 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:00.387 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:00.431 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:34:00.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:00.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:00.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:00.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:00.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:00.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:00.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:00.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:00.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:00.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:00.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:00.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:00.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:00.909 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:34:00.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:00.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:00.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:00.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:00.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:01.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:01.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:01.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:01.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:34:01.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:34:01.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:34:01.365 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:01.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:06.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:34:06.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:34:06.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:34:06.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:34:06.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:34:06.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:34:06.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:34:06.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:34:06.381 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:06.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:34:06.381 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:34:06.384 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:34:06.384 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:34:06.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:34:06.385 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:06.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:34:06.386 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:34:06.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:34:06.386 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:34:06.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:06.387 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:34:06.387 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:34:06.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:34:06.387 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:06.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:34:06.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:34:06.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:34:06.388 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:34:06.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:06.390 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:34:06.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:34:06.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:34:06.390 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:06.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:34:06.390 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:34:06.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:34:06.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:34:06.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:06.393 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:34:06.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:34:06.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:34:06.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:34:06.393 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:34:06.394 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:34:06.394 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:34:06.394 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:06.399 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:34:06.882 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:34:06.924 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:34:06.927 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:34:06.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:06.929 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:34:06.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:06.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:06.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:06.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:06.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:06.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:06.957 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:06.957 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:06.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:06.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:06.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:06.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:06.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:07.360 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:34:07.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:07.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:07.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:07.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:07.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:07.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:07.838 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:34:08.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:08.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:08.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:08.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:08.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:08.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:08.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:08.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:08.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:08.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:08.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:08.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:08.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:08.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:08.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:08.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:08.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:08.315 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:34:08.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:08.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:08.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:08.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:08.793 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:34:09.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:09.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:09.271 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:34:09.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:09.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:09.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:09.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:09.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:09.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:09.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:09.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:09.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:09.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:09.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:09.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:09.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:09.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:09.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:09.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:09.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:09.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:09.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:09.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:09.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:09.748 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:34:10.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:10.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:10.226 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:34:10.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:10.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:10.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:10.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:10.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:10.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:10.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:10.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:10.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:10.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:10.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:10.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:10.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:10.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:10.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:10.704 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:34:10.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:10.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:10.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:10.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:10.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:11.181 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:34:11.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:11.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:11.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:11.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:11.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:11.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:11.659 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:34:12.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:12.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:12.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:12.137 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:34:12.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:12.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:12.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:12.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:12.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:12.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:12.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:12.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:12.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:12.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:12.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:12.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:12.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:12.614 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:34:13.092 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:34:13.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:13.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:13.570 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:34:13.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:13.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:13.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:13.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:13.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:13.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:13.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:13.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:13.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:13.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:13.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:13.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:13.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:13.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:13.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:13.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:14.048 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:34:14.525 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:34:14.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:14.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:15.003 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:34:15.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:15.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:15.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:15.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:15.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:15.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:15.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:15.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:15.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:15.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:15.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:15.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:15.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:15.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:15.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:15.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:15.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:15.481 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:34:15.959 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:34:16.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:16.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:16.437 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:34:16.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:16.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:16.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:16.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:16.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:16.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:16.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:16.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:16.756 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:16.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:16.756 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:16.756 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:16.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:16.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:16.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:16.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:16.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:16.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:16.913 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:34:17.391 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:34:17.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:17.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:17.869 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:34:18.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:18.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:18.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:18.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:18.263 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=2535 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:18.263 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=2535 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:18.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:18.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:18.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:18.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:18.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:18.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:18.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:18.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:18.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:18.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:18.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:18.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:18.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:18.346 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:34:18.824 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:34:19.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:19.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:19.302 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:34:19.781 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:34:19.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:19.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:19.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:19.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:19.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:19.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:19.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:19.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:19.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:19.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:19.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:19.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:19.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:19.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:19.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:19.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:19.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:20.258 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:34:20.736 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:34:21.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:21.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:21.214 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:34:21.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:21.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:21.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:21.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:21.691 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:34:21.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:21.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:21.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:21.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:21.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:21.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:21.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:21.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:21.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:21.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:21.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:21.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:21.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:22.169 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:34:22.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:22.647 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:34:22.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:23.125 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:34:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:23.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:23.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:23.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:23.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:23.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:23.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:23.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:23.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:23.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:23.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:23.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:23.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:23.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:23.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:23.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:23.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:23.602 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:34:24.080 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:34:24.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:24.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:24.559 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:34:24.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:24.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:24.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:24.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:24.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:24.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:24.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:24.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:24.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:24.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:24.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:24.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:24.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:24.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:24.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:24.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:24.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:25.036 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:34:25.513 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:34:25.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:25.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:25.991 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:34:26.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:26.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:26.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:26.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:26.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:26.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:26.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:26.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:26.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:26.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:26.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:26.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:26.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:26.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:26.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:26.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:26.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:26.469 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:34:26.948 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:34:27.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:27.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:27.426 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:34:27.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:27.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:27.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:27.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:27.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:27.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:27.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:27.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:27.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:27.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:27.615 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:27.615 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:27.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:27.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:27.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:27.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:27.903 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:34:28.381 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:34:28.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:28.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:28.859 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:34:29.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:29.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:29.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:29.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:29.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:29.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:29.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:29.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:29.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:29.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:29.076 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:29.076 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:29.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:29.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:29.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:29.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:29.336 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:34:29.814 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:34:30.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:30.291 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:34:30.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:30.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:30.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:30.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:30.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:30.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:30.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:30.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:30.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:30.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:30.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:30.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:30.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:30.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:30.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:30.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:30.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:30.768 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:34:31.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:31.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:31.246 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:34:31.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:31.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:31.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:31.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:31.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:31.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:31.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:31.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:31.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:31.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:31.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:31.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:31.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:31.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:31.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:31.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:31.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:31.723 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:34:32.201 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:34:32.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:32.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:32.679 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:34:33.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:33.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:33.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:33.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:33.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:33.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:33.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:33.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:33.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:33.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:33.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:33.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:33.157 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:34:33.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:33.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:33.166 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:33.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:33.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:33.635 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:34:34.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:34.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:34.112 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:34:34.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:34.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:34.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:34.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:34.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:34.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:34.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:34.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:34.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:34.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:34.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:34.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:34.590 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:34:34.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:34.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:34.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:34.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:34.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:35.068 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:34:35.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:35.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:35.545 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:34:35.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:35.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:35.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:35.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:36.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:36.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:36.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:36.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:36.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:34:36.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:34:36.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:34:36.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:34:36.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:34:36.011 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:34:36.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.012 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.013 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.013 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.013 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.013 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.013 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:36.013 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6325 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:34:41.010 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:34:41.010 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:34:41.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:34:41.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:34:41.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:34:41.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:34:41.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:34:41.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:34:41.021 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:41.022 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:34:41.022 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:34:41.026 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:34:41.026 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:34:41.026 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:34:41.026 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:41.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:34:41.026 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:34:41.027 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:34:41.027 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:34:41.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:41.029 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:34:41.029 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:34:41.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:34:41.029 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:41.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:34:41.030 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:34:41.030 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:34:41.030 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:34:41.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:41.033 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:34:41.033 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:34:41.033 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:34:41.033 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:34:41.033 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:34:41.033 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:34:41.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:34:41.034 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:34:41.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:34:41.038 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:34:41.038 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:34:41.038 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:34:41.043 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:34:41.525 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:34:41.573 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:34:41.575 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:34:41.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:41.577 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:34:41.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:41.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:41.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:41.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:41.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:41.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:41.604 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:41.604 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:41.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:41.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:41.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:41.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:41.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:42.002 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:34:42.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:42.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:42.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:42.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:42.480 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:34:42.958 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:34:43.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:43.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:43.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:43.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:43.436 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:34:43.914 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:34:44.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:44.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:44.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:44.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:44.392 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:34:44.870 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:34:45.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:45.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:45.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:45.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:45.348 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:34:45.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:45.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:45.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:45.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:45.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:45.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:45.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:45.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:45.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:45.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:45.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:45.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:45.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:45.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:45.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:45.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:45.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:45.825 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:34:46.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:34:46.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:34:46.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:34:46.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:34:46.303 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:34:46.781 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:34:47.259 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:34:47.737 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:34:48.214 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:34:48.692 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:34:49.169 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:34:49.647 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:34:49.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:49.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:49.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:49.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:49.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:49.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:49.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:49.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:49.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:49.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:49.891 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:49.891 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:49.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:49.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:49.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:49.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:49.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:50.124 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:34:50.602 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:34:51.080 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:34:51.558 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:34:52.036 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:34:52.514 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:34:52.992 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:34:53.469 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:34:53.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:53.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:53.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:53.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:53.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:53.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:53.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:53.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:53.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:53.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:53.930 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:53.930 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:53.947 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:34:53.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:53.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:53.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:53.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:53.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:54.425 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:34:54.903 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:34:55.380 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:34:55.858 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:34:56.336 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:34:56.814 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:34:57.291 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:34:57.768 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:34:58.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:58.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:58.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:58.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:58.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:34:58.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:34:58.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:34:58.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:58.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:58.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:58.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:34:58.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:34:58.245 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:34:58.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:34:58.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:34:58.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:34:58.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:58.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:34:58.722 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:34:59.199 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:34:59.677 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:35:00.154 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:35:00.632 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:35:01.110 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:35:01.588 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:35:02.066 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:35:02.544 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:35:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:02.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:02.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:02.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:02.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:02.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:02.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:02.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:02.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:02.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:02.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:02.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:03.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:03.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:03.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:03.022 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:35:03.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:03.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:03.499 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:35:03.977 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:35:04.455 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:35:04.931 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:35:05.404 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:35:05.880 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:35:06.359 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:35:06.836 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:35:07.314 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:35:07.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:07.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:07.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:07.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:07.395 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=5629 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:35:07.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:07.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:07.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:07.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:07.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:07.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:07.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:07.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:07.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:07.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:07.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:07.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:07.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:07.792 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:35:08.270 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:35:08.747 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:35:09.225 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:35:09.703 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:35:10.180 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:35:10.659 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:35:11.136 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:35:11.614 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:35:11.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:11.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:11.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:11.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:11.837 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=6578 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:35:11.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:11.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:11.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:11.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:11.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:11.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:11.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:11.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:11.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:35:11.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:11.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:11.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:11.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:11.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:12.091 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:35:12.575 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:35:13.053 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:35:13.531 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:35:14.009 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:35:14.487 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:35:14.966 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:35:15.444 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 01:35:15.922 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 01:35:16.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:16.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:16.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:16.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:16.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:16.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:16.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:16.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:16.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:16.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:16.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:16.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:16.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:16.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:16.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:16.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:16.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:16.399 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 01:35:16.877 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 01:35:17.355 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 01:35:17.834 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 01:35:18.312 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 01:35:18.790 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 01:35:19.268 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 01:35:19.746 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 01:35:20.224 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 01:35:20.701 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 01:35:20.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:20.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:20.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:20.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:20.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:20.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:20.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:20.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:20.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:20.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:20.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:20.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:20.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:35:20.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:20.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:20.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:20.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:20.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:21.179 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 01:35:21.657 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 01:35:22.134 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 01:35:22.612 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 01:35:23.090 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 01:35:23.567 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 01:35:24.045 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 01:35:24.523 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 01:35:25.001 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 01:35:25.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:25.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:25.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:25.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:25.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:25.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:25.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:25.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:25.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:25.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:25.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:25.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:25.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:25.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:25.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:25.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:25.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:25.477 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 01:35:25.954 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 01:35:26.431 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 01:35:26.909 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 01:35:27.387 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 01:35:27.865 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 01:35:28.343 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 01:35:28.821 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 01:35:29.300 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 01:35:29.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:29.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:29.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:29.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:29.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:29.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:29.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:29.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:29.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:29.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:29.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:29.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:29.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:29.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:29.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:29.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:29.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:29.776 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 01:35:30.254 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 01:35:30.732 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 01:35:31.209 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 01:35:31.687 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 01:35:32.165 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 01:35:32.643 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 01:35:33.121 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 01:35:33.599 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 01:35:33.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:33.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:33.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:33.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:33.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:33.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:33.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:33.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:33.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:33.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:33.907 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:33.907 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:33.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:33.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:33.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:33.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:33.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:34.073 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 01:35:34.551 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 01:35:35.029 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 01:35:35.507 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 01:35:35.985 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 01:35:36.462 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 01:35:36.940 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 01:35:37.419 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 01:35:37.897 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 01:35:38.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:38.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:38.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:38.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:38.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:38.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:38.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:38.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:38.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:38.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:38.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:38.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:38.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:38.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:38.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:38.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:38.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:38.374 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 01:35:38.852 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 01:35:39.330 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 01:35:39.808 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 01:35:40.285 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 01:35:40.763 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 01:35:41.241 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 01:35:41.719 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 01:35:42.197 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 01:35:42.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:42.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:42.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:42.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:42.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:42.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:42.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:42.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:42.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:42.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:42.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:42.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:42.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:42.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:42.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:42.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:42.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:42.671 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 01:35:43.149 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 01:35:43.626 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 01:35:44.104 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 01:35:44.582 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 01:35:45.060 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 01:35:45.538 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 01:35:46.016 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 01:35:46.493 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 01:35:46.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:46.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:46.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:46.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:46.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:46.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:46.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:46.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:46.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:46.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:46.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:46.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:46.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:46.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:46.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:46.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:46.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:46.970 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 01:35:47.448 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 01:35:47.925 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 01:35:48.402 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 01:35:48.880 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 01:35:49.358 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 01:35:49.836 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 01:35:50.313 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 01:35:50.791 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 01:35:51.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:51.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:51.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:51.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:51.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:51.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:51.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:51.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:51.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:51.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:51.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:51.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:51.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:51.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:51.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:51.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:51.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:51.268 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 01:35:51.746 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 01:35:52.224 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 01:35:52.702 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 01:35:53.180 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 01:35:53.658 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 01:35:54.136 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 01:35:54.613 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 01:35:55.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:55.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:55.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:55.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:55.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:55.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:55.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:55.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:55.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:55.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:55.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:55.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:55.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:55.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:55.092 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 01:35:55.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:55.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:55.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:55.569 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 01:35:56.047 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 01:35:56.526 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 01:35:57.003 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 01:35:57.481 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 01:35:57.960 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 01:35:58.438 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 01:35:58.916 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 01:35:59.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:59.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:59.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:59.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:59.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:35:59.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:35:59.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:35:59.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:59.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:59.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:59.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:35:59.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:35:59.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:35:59.393 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 01:35:59.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:35:59.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:35:59.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:59.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:35:59.871 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 01:36:00.349 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 01:36:00.827 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 01:36:01.304 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 01:36:01.776 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 01:36:02.254 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 01:36:02.732 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 01:36:03.210 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 01:36:03.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:03.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:03.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:03.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:03.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:03.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:03.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:03.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:03.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:03.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:03.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:03.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:03.687 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 01:36:03.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:03.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:03.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:03.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:03.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:04.165 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 01:36:04.643 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 01:36:05.121 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 01:36:05.599 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 01:36:06.077 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 01:36:06.554 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 01:36:07.032 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 01:36:07.510 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 01:36:07.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:07.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:07.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:07.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:07.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:07.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:07.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:07.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:07.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:36:07.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:36:07.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:36:07.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:36:07.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:36:07.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:36:07.971 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:36:12.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:36:12.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:36:12.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:36:12.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:36:12.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:36:12.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:36:12.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:36:12.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:36:12.979 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:12.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:36:12.979 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:36:12.980 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:36:12.980 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:36:12.980 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:36:12.980 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:12.980 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:36:12.980 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:36:12.980 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:36:12.980 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:36:12.981 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:36:12.981 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:36:12.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:36:12.982 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:36:12.982 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:36:12.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:36:12.984 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:36:12.984 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:36:12.984 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:36:12.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:36:12.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:36:12.985 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:36:17.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:36:17.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:36:17.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:36:17.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:36:17.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:36:17.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:36:18.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:36:18.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:36:18.021 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:18.022 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:36:18.022 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:36:18.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:36:18.029 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:36:18.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:36:18.030 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:18.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:36:18.031 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:36:18.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:36:18.032 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:36:18.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:18.034 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:36:18.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:36:18.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:36:18.035 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:18.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:36:18.036 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:36:18.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:36:18.036 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:36:18.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:36:18.038 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:36:18.038 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:36:18.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:36:18.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:36:18.041 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:36:18.041 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:36:18.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:36:18.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:18.046 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:36:18.531 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:36:18.565 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:36:18.566 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:36:18.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:18.568 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:36:18.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:18.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:18.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:18.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:18.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:18.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:18.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:18.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:18.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:18.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:18.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:18.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:18.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:19.007 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:36:19.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:19.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:19.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:19.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:19.485 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:36:19.963 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:36:20.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:20.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:20.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:20.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:20.441 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:36:20.919 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:36:21.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:21.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:21.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:21.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:21.397 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:36:21.874 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:36:22.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:22.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:22.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:22.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:22.352 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:36:22.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:22.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:22.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:22.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:22.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:22.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:22.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:22.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:22.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:22.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:22.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:22.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:22.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:22.757 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:22.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:22.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:22.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:22.829 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:36:23.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:36:23.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:36:23.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:36:23.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:36:23.307 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:36:23.784 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:36:24.262 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:36:24.740 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:36:25.217 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:36:25.695 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:36:26.173 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:36:26.651 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:36:27.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:27.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:27.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:27.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:27.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:27.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:27.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:27.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:27.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:27.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:27.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:27.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:27.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:27.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:27.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:27.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:27.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:27.128 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:36:27.605 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:36:28.083 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:36:28.561 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:36:29.038 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:36:29.516 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:36:29.994 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:36:30.472 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:36:30.950 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:36:31.428 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:36:31.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:31.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:31.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:31.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:31.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:31.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:31.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:31.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:31.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:31.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:31.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:31.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:31.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:31.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:31.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:31.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:31.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:31.905 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:36:32.382 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:36:32.860 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:36:33.337 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:36:33.815 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:36:34.293 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:36:34.771 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:36:35.249 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:36:35.727 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:36:35.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:35.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:35.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:35.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:35.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:35.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:35.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:35.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:35.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:35.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:35.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:35.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:35.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:35.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:35.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:35.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:35.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:36.205 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:36:36.682 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:36:37.160 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:36:37.638 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:36:38.116 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:36:38.593 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:36:39.071 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:36:39.549 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:36:40.027 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:36:40.504 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:36:40.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:40.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:40.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:40.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:40.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:40.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:40.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:40.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:40.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:40.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:40.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:40.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:40.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:40.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:40.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:40.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:40.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:40.982 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:36:41.460 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:36:41.938 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:36:42.416 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:36:42.895 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:36:43.372 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:36:43.850 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:36:44.328 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:36:44.806 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:36:44.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:44.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:44.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:44.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:44.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:44.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:44.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:44.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:44.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:44.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:44.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:44.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:45.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:45.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:45.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:45.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:45.284 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:36:45.762 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:36:46.240 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:36:46.718 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:36:47.196 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:36:47.674 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:36:48.151 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:36:48.629 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:36:49.106 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:36:49.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:49.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:49.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:49.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:49.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:49.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:49.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:49.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:49.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:49.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:49.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:49.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:49.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:49.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:49.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:49.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:49.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:49.584 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:36:50.062 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:36:50.540 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:36:51.018 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:36:51.497 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:36:51.975 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:36:52.453 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 01:36:52.931 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 01:36:53.409 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 01:36:53.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:53.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:53.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:53.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:53.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:53.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:53.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:53.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:53.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:53.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:53.878 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:53.878 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:53.886 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 01:36:53.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:53.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:53.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:53.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:53.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:54.364 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 01:36:54.842 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 01:36:55.320 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 01:36:55.799 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 01:36:56.277 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 01:36:56.755 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 01:36:57.233 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 01:36:57.711 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 01:36:58.189 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 01:36:58.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:58.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:58.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:58.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:58.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:36:58.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:36:58.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:36:58.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:58.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:58.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:58.331 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:36:58.331 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:36:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:36:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:36:58.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:36:58.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:36:58.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:58.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:36:58.667 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 01:36:59.145 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 01:36:59.623 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 01:37:00.101 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 01:37:00.579 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 01:37:01.057 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 01:37:01.535 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 01:37:02.013 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 01:37:02.487 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 01:37:02.966 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 01:37:03.443 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 01:37:03.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:03.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:03.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:03.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:03.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:03.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:03.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:03.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:03.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:03.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:03.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:03.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:03.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:03.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:03.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:03.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:03.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:03.921 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 01:37:04.399 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 01:37:04.878 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 01:37:05.356 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 01:37:05.834 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 01:37:06.312 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 01:37:06.790 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 01:37:07.268 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 01:37:07.746 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 01:37:08.224 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 01:37:08.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:08.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:08.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:08.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:08.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:08.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:08.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:08.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:08.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:08.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:08.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:08.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:08.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:08.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:08.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:08.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:08.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:08.702 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 01:37:09.179 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 01:37:09.657 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 01:37:10.135 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 01:37:10.613 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 01:37:11.092 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 01:37:11.570 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 01:37:12.048 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 01:37:12.526 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 01:37:12.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:12.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:12.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:12.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:12.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:12.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:12.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:12.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:12.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:12.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:12.948 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:12.948 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:12.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:13.004 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 01:37:13.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:13.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:13.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:13.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:13.482 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 01:37:13.960 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 01:37:14.437 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 01:37:14.915 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 01:37:15.392 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 01:37:15.870 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 01:37:16.348 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 01:37:16.826 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 01:37:17.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:17.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:17.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:17.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:17.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:17.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:17.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:17.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:17.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:17.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:17.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:17.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:17.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:17.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:17.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:17.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:17.304 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 01:37:17.782 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 01:37:18.261 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 01:37:18.739 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 01:37:19.217 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 01:37:19.694 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 01:37:20.172 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 01:37:20.650 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 01:37:21.128 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 01:37:21.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:21.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:21.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:21.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:21.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:21.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:21.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:21.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:21.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:21.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:21.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:21.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:21.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:21.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:21.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:21.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:21.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:21.606 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 01:37:22.083 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 01:37:22.561 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 01:37:23.039 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 01:37:23.516 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 01:37:23.994 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 01:37:24.472 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 01:37:24.949 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 01:37:25.427 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 01:37:25.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:25.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:25.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:25.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:25.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:25.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:25.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:25.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:25.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:25.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:25.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:25.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:25.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:25.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:25.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:25.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:25.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:25.904 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 01:37:26.382 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 01:37:26.859 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 01:37:27.336 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 01:37:27.813 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 01:37:28.290 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 01:37:28.768 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 01:37:29.246 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 01:37:29.723 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 01:37:30.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:30.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:30.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:30.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:30.075 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=15378 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:30.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:30.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:30.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:30.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:30.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:30.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:30.097 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:30.097 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:30.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:30.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:30.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:30.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:30.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:30.200 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 01:37:30.678 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 01:37:31.156 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 01:37:31.634 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 01:37:32.113 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 01:37:32.590 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 01:37:33.069 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 01:37:33.547 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 01:37:34.024 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 01:37:34.502 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 01:37:34.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:34.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:34.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:34.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:34.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:34.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:34.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:34.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:34.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:34.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:34.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:34.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:34.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:34.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:34.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:34.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:34.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:34.979 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 01:37:35.457 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 01:37:35.934 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 01:37:36.412 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 01:37:36.890 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 01:37:37.369 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 01:37:37.847 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 01:37:38.325 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 01:37:38.802 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 01:37:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:38.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:38.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:38.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:38.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:38.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:38.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:38.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:38.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:38.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:38.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:38.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:38.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:38.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:38.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:38.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:38.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:39.280 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 01:37:39.758 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 01:37:40.236 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 01:37:40.714 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 01:37:41.192 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 01:37:41.670 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 01:37:42.148 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 01:37:42.626 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 01:37:43.104 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 01:37:43.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:43.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:43.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:43.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:43.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:43.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:43.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:43.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:43.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:43.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:43.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:43.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:43.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:43.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:43.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:43.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:43.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:43.581 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 01:37:44.059 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 01:37:44.537 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 01:37:45.015 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-02 01:37:45.493 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-02 01:37:45.970 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-02 01:37:46.448 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-02 01:37:46.926 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-02 01:37:47.403 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-02 01:37:47.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:47.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:47.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:47.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:47.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:37:47.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:37:47.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:37:47.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:37:47.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:37:47.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:37:47.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:37:47.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:37:47.526 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:37:47.526 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:37:47.526 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:37:47.526 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19101 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.526 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19101 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19101 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19101 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19101 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19101 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.527 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:47.528 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19102 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:37:52.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:37:52.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:37:52.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:37:52.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:37:52.529 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:37:52.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:37:52.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:37:52.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:37:52.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:52.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:37:52.542 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:37:52.545 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:37:52.546 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:37:52.546 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:37:52.547 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:52.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:37:52.547 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:37:52.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:37:52.548 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:37:52.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:37:52.549 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:37:52.549 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:37:52.550 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:37:52.550 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:52.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:37:52.550 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:37:52.550 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:37:52.550 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:37:52.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:37:52.552 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:37:52.552 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:37:52.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:37:52.553 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:52.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:37:52.553 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:37:52.553 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:37:52.553 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:37:52.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:52.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:52.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:52.557 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:37:52.557 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:37:52.557 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:37:52.557 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:37:52.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:52.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:52.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:37:52.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:37:52.558 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:52.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.561 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:37:57.561 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:37:57.563 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:37:57.564 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:37:57.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:37:57.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:37:57.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:37:57.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:37:57.573 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:57.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:37:57.573 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:37:57.576 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:37:57.576 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:37:57.576 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:37:57.577 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:57.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:37:57.577 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:37:57.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:37:57.578 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:37:57.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:37:57.578 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:37:57.578 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:37:57.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:37:57.578 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:57.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:37:57.579 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:37:57.579 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:37:57.579 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:37:57.579 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:37:57.580 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:37:57.580 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:37:57.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:37:57.581 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:37:57.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:37:57.581 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:37:57.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:37:57.581 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:37:57.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:37:57.584 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:37:57.584 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:37:57.584 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:37:57.589 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:37:58.073 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:37:58.109 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:37:58.110 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:37:58.111 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:37:58.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:58.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:58.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:58.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:58.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:58.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:58.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:58.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:58.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:58.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:58.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:58.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:58.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:58.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:58.550 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:37:58.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:37:58.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:37:58.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:37:58.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:37:59.028 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:37:59.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:59.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:59.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:59.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:59.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:37:59.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:37:59.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:37:59.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:59.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:59.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:59.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:37:59.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:37:59.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:37:59.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:37:59.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:37:59.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:59.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:37:59.505 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:37:59.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:37:59.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:37:59.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:37:59.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:37:59.982 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:38:00.460 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:38:00.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:00.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:00.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:00.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:00.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:00.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:00.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:00.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:00.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:00.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:00.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:00.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:00.704 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:00.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:00.704 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:00.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:00.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:00.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:00.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:00.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:00.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:00.938 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:38:01.415 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:38:01.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:01.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:01.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:01.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:01.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:01.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:01.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:01.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:01.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:01.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:01.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:01.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:01.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:01.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:01.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:01.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:01.892 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:38:01.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:01.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:01.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:01.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:01.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:02.370 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:38:02.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:02.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:02.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:02.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:02.848 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:38:03.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:03.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:03.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:03.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:03.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:03.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:03.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:03.325 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:38:03.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:03.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:03.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:03.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:03.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:03.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:03.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:03.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:03.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:03.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:03.803 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:38:04.281 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:38:04.759 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:38:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:04.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:04.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:04.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:04.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:04.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:04.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:04.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:04.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:04.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:04.909 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:04.909 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:04.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:04.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:04.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:04.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:04.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:05.236 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:38:05.714 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:38:06.192 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:38:06.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:06.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:06.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:06.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:06.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:06.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:06.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:06.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:06.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:06.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:06.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:06.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:06.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:06.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:06.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:06.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:06.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:06.669 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:38:07.148 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:38:07.626 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:38:07.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:07.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:07.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:07.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:07.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:07.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:07.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:07.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:07.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:07.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:07.951 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:07.951 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:08.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:08.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:08.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:08.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:08.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:08.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:08.103 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:38:08.581 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:38:09.059 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:38:09.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:09.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:09.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:09.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:09.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:09.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:09.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:09.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:09.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:09.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:09.473 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:09.473 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:09.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:09.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:09.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:09.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:09.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:09.537 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:38:10.015 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:38:10.493 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:38:10.971 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:38:10.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:10.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:10.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:10.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:10.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:10.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:10.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:10.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:10.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:10.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:10.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:10.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:11.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:11.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:11.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:11.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:11.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:11.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:11.449 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:38:11.926 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:38:12.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:12.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:12.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:12.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:12.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:12.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:12.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:12.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:12.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:12.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:12.392 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:12.392 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:12.404 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:38:12.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:12.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:12.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:12.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:12.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:12.882 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:38:13.360 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:38:13.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:13.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:13.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:13.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:13.838 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:38:13.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:13.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:13.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:13.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:13.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:13.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:13.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:13.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:13.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:13.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:13.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:13.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:13.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:14.315 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:38:14.793 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:38:15.272 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:38:15.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:15.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:15.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:15.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:15.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:15.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:15.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:15.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:15.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:15.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:15.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:15.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:15.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:15.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:15.439 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:15.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:15.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:15.749 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:38:16.227 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:38:16.705 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:38:16.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:16.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:16.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:16.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:16.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:16.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:16.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:16.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:16.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:16.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:16.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:16.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:16.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:16.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:16.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:16.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:16.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:17.182 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:38:17.660 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:38:18.138 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:38:18.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:18.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:18.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:18.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:18.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:18.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:18.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:18.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:18.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:18.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:18.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:18.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:18.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:18.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:18.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:18.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:18.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:18.616 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:38:19.094 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:38:19.571 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:38:19.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:19.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:19.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:19.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:19.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:19.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:19.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:19.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:19.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:19.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:19.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:19.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:19.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:19.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:19.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:19.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:19.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:20.048 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:38:20.526 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:38:21.004 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:38:21.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:21.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:21.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:21.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:21.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:21.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:21.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:21.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:21.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:21.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:21.236 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:21.236 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:21.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:21.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:21.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:21.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:21.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:21.482 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:38:21.960 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:38:22.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:22.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:22.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:22.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:22.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:22.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:22.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:22.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:22.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:22.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:22.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:22.377 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:22.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:22.436 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:38:22.439 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:22.439 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:22.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:22.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:22.914 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:38:23.392 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:38:23.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:23.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:23.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:23.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:23.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:23.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:23.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:23.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:23.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:23.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:23.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:23.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:23.870 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:38:23.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:23.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:23.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:23.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:23.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:24.347 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:38:24.825 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:38:25.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:25.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:25.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:25.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:25.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:25.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:25.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:25.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:25.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:25.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:25.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:25.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:25.303 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:38:25.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:25.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:25.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:25.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:25.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:25.781 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:38:26.259 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:38:26.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:26.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:26.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:26.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:26.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:26.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:26.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:26.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:26.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:38:26.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:38:26.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:38:26.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:38:26.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:38:26.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:38:26.723 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6221 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6221 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6221 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6221 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6221 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6221 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:26.723 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6222 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:31.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:38:31.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:38:31.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:38:31.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:38:31.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:38:31.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:38:31.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:38:31.741 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:38:31.741 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:38:31.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:38:31.742 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:38:31.744 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:38:31.744 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:38:31.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:38:31.745 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:38:31.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:38:31.745 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:38:31.746 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:38:31.746 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:38:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:31.747 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:38:31.747 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:38:31.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:38:31.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:38:31.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:38:31.747 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:38:31.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:38:31.747 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:38:31.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:31.749 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:38:31.749 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:38:31.749 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:38:31.749 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:38:31.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:38:31.749 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:38:31.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:38:31.750 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:38:31.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:38:31.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:38:31.753 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:38:31.753 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:38:31.753 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:38:31.758 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:38:32.240 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:38:32.277 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:38:32.278 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:38:32.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:32.279 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:38:32.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:32.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:32.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:32.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:32.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:32.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:32.307 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:32.307 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:32.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:32.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:32.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:32.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:32.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:32.718 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:38:32.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:32.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:32.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:32.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:33.196 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:38:33.673 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:38:33.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:33.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:33.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:33.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:34.152 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:38:34.629 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:38:34.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:34.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:34.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:34.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:35.107 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:38:35.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:35.585 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:38:35.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:35.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:35.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:35.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:36.062 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:38:36.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:36.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:36.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:36.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:36.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:36.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:36.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:36.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:36.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:36.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:36.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:36.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:36.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:36.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:36.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:36.540 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:38:36.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:38:36.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:38:36.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:38:36.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:38:37.018 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:38:37.495 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:38:37.974 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:38:38.451 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:38:38.929 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:38:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:39.407 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:38:39.885 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:38:40.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:40.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:40.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:40.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:40.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:40.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:40.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:40.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:40.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:40.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:40.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:40.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:40.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:40.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:40.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:40.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:40.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:40.362 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:38:40.841 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:38:41.319 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:38:41.797 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:38:42.275 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:38:42.753 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:38:43.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:43.231 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:38:43.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:43.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:43.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:43.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:43.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:43.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:43.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:43.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:43.687 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:43.687 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:43.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:43.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:43.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:43.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:43.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:43.709 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:38:44.187 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:38:44.665 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:38:45.143 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:38:45.622 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:38:46.100 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:38:46.579 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:38:46.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:47.057 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:38:47.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:47.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:47.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:47.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:47.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:47.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:47.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:47.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:47.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:47.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:47.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:47.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:47.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:47.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:47.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:47.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:47.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:47.534 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:38:48.011 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:38:48.489 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:38:48.966 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:38:49.444 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:38:49.922 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:38:50.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:50.400 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:38:50.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:50.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:50.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:50.840 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=4075 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:50.840 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=4075 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:38:50.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:50.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:50.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:50.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:50.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:50.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:50.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:50.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:50.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:50.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:50.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:50.877 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:38:51.355 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:38:51.832 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:38:52.310 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:38:52.788 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:38:53.266 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:38:53.744 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:38:53.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:54.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:54.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:54.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:54.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:54.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:54.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:54.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:54.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:54.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:54.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:54.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:54.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:54.221 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:38:54.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:54.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:54.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:54.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:54.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:54.699 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:38:55.177 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:38:55.654 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:38:56.132 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:38:56.611 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:38:57.088 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:38:57.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:57.566 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:38:57.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:38:57.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:57.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:38:57.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:38:57.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:38:57.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:57.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:57.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:57.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:38:57.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:38:57.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:38:57.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:38:57.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:38:57.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:57.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:38:58.043 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:38:58.521 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:38:58.999 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:38:59.477 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:38:59.954 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:39:00.432 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:39:00.910 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:39:01.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:01.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:01.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:01.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:01.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:01.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:01.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:01.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:01.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:01.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:39:01.321 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:39:01.321 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:39:01.321 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:39:01.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:39:01.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:39:01.321 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:39:01.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:01.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:01.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:01.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:01.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:01.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:01.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:06.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:39:06.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:39:06.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:39:06.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:39:06.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:39:06.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:39:06.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:39:06.333 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:39:06.333 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:06.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:39:06.334 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:39:06.339 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:39:06.339 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:39:06.339 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:39:06.339 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:06.339 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:39:06.339 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:39:06.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:39:06.340 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:39:06.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:06.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:39:06.342 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:39:06.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:39:06.343 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:06.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:39:06.343 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:39:06.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:39:06.343 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:39:06.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:06.345 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:39:06.345 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:39:06.346 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:39:06.346 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:06.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:39:06.346 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:39:06.346 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:39:06.346 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:39:06.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:39:06.350 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:39:06.350 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:39:06.350 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:06.355 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:39:06.838 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:39:06.878 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:39:06.881 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:39:06.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:06.883 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:39:06.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:06.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:06.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:06.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:06.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:06.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:06.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:06.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:06.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:06.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:06.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:06.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:06.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:07.315 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:39:07.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:07.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:07.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:07.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:07.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:39:08.271 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:39:08.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:08.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:08.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:08.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:08.749 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:39:09.226 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:39:09.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:09.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:09.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:09.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:09.704 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:39:09.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:10.182 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:39:10.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:10.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:10.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:10.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:10.660 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:39:10.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:10.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:10.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:10.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:10.736 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=936 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:10.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:10.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:10.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:10.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:10.738 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:10.738 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:10.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:10.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:10.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:10.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:10.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:11.138 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:39:11.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:11.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:11.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:11.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:11.616 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:39:12.094 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:39:12.572 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:39:13.050 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:39:13.528 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:39:13.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:14.006 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:39:14.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:14.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:14.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:14.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:14.147 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=1664 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:14.147 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=1664 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:14.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:14.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:14.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:14.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:14.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:14.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:14.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:14.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:14.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:14.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:14.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:14.484 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:39:14.962 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:39:15.440 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:39:15.918 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:39:16.396 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:39:16.873 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:39:17.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:17.350 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:39:17.828 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:39:18.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:18.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:18.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:18.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:18.042 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=2496 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:18.042 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=2496 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:18.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:18.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:18.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:18.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:18.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:18.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:18.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:18.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:18.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:18.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:18.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:18.305 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:39:18.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:18.783 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:39:19.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:19.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:19.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:19.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:19.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:19.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:19.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:19.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:19.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:19.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:19.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:19.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:19.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:19.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:19.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:19.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:19.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:19.260 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:39:19.738 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:39:20.217 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:39:20.695 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:39:21.172 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:39:21.650 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:39:22.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:22.129 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:39:22.606 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:39:22.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:22.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:22.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:22.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:22.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:22.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:22.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:22.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:22.675 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:22.675 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:22.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:22.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:22.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:22.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:22.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:23.084 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:39:23.562 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:39:24.040 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:39:24.518 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:39:24.997 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:39:25.475 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:39:25.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:25.952 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:39:26.430 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:39:26.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:26.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:26.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:26.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:26.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:26.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:26.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:26.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:26.574 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:26.574 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:26.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:26.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:26.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:26.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:26.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:26.908 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:39:27.386 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:39:27.865 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:39:28.343 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:39:28.821 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:39:29.299 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:39:29.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:29.778 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:39:30.256 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:39:30.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:30.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:30.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:30.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:30.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:30.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:30.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:30.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:30.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:30.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:30.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:30.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:30.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:30.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:30.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:30.734 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:39:30.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:31.211 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:39:31.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:31.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:31.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:31.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:31.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:31.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:31.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:31.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:31.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:31.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:31.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:31.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:31.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:31.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:31.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:31.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:31.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:31.688 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:39:32.166 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:39:32.643 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:39:33.121 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:39:33.599 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:39:34.077 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:39:34.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:34.554 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:39:34.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:34.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:34.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:34.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:34.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:34.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:34.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:34.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:34.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:34.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:35.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:35.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:35.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:35.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:35.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:35.032 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:39:35.509 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:39:35.987 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:39:36.465 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:39:36.942 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:39:37.420 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:39:37.898 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:39:38.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:38.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:38.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:38.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:38.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:38.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:38.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:38.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:38.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:38.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:38.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:38.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:38.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:38.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:38.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:38.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:38.376 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:39:38.853 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:39:39.331 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:39:39.809 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:39:40.286 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:39:40.763 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 01:39:41.242 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 01:39:41.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:41.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:41.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:41.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:41.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:41.682 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=7543 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:41.682 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=7543 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:41.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:41.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:41.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:41.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:41.683 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:41.683 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:41.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:41.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:41.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:41.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:41.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:41.720 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 01:39:42.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:42.197 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 01:39:42.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:42.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:42.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:42.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:42.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:42.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:42.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:42.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:42.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:42.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:42.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:42.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:42.675 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 01:39:42.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:42.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:42.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:42.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:42.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:43.152 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 01:39:43.630 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 01:39:44.108 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 01:39:44.585 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 01:39:45.063 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 01:39:45.542 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 01:39:45.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:46.019 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 01:39:46.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:46.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:46.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:46.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:46.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:46.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:46.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:46.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:46.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:46.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:46.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:46.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:46.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:46.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:46.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:46.496 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 01:39:46.974 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 01:39:47.452 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 01:39:47.929 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 01:39:48.408 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 01:39:48.886 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 01:39:49.364 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 01:39:49.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:49.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:49.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:49.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:49.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:49.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:49.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:49.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:49.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:49.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:49.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:49.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:49.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:49.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:49.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:49.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:49.841 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 01:39:50.319 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 01:39:50.797 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 01:39:51.274 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 01:39:51.752 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 01:39:52.230 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 01:39:52.708 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 01:39:52.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:53.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:53.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:53.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:53.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:53.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:53.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:53.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:53.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:53.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:53.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:39:53.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:39:53.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:53.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:53.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:53.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:53.186 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 01:39:53.663 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 01:39:53.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:54.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:54.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:54.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:54.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:54.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:54.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:54.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:54.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:54.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:39:54.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:39:54.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:39:54.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:39:54.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:39:54.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:39:54.073 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:54.074 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10188 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:39:59.072 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:39:59.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:39:59.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:39:59.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:39:59.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:39:59.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:39:59.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:39:59.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:39:59.087 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:59.088 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:39:59.088 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:39:59.092 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:39:59.092 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:39:59.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:39:59.093 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:59.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:39:59.094 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:39:59.094 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:39:59.094 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:39:59.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:39:59.096 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:39:59.096 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:39:59.096 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:39:59.096 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:59.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:39:59.096 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:39:59.096 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:39:59.096 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:39:59.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:39:59.099 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:39:59.099 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:39:59.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:39:59.099 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:39:59.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:39:59.099 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:39:59.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:39:59.099 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:39:59.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.103 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:39:59.104 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:39:59.104 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:39:59.104 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:39:59.109 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:39:59.593 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:39:59.631 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:39:59.633 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:39:59.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:39:59.635 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:39:59.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:39:59.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:39:59.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:39:59.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:39:59.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:39:59.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:39:59.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:39:59.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:40:00.068 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:40:00.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:00.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:00.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:00.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:00.540 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:40:01.013 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:40:01.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:01.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:01.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:01.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:01.485 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:40:01.959 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:40:02.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:02.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:02.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:02.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:02.432 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:40:02.904 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:40:03.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:03.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:03.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:03.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:03.374 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:40:03.845 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:40:04.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:04.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:04.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:04.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:04.319 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:40:04.791 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:40:05.263 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:40:05.733 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:40:06.204 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:40:06.675 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:40:07.149 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:40:07.627 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:40:08.105 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:40:08.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:08.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:08.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:08.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:08.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:08.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:08.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:08.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:08.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:08.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:08.474 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:08.474 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:08.474 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2019 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2019 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2019 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2019 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2019 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2019 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2020 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2020 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:08.475 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2020 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:13.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:13.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:13.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:13.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:13.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:13.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:13.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:13.488 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:40:13.488 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:13.489 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:40:13.489 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:40:13.493 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:40:13.493 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:40:13.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:40:13.494 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:13.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:13.495 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:40:13.495 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:40:13.495 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:40:13.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:13.496 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:40:13.497 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:40:13.497 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:40:13.497 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:13.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:13.498 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:40:13.498 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:40:13.498 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:40:13.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:40:13.499 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:40:13.499 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:40:13.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.502 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:40:13.502 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:40:13.502 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:40:13.502 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:13.507 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:40:13.990 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:40:14.030 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:14.032 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:40:14.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:40:14.034 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:40:14.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:14.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:14.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:40:14.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:40:14.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:40:14.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:40:14.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:40:14.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:40:14.465 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:40:14.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:14.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:14.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:14.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:14.935 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:40:15.404 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:40:15.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:15.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:15.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:15.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:15.876 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:40:16.348 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:40:16.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:16.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:16.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:16.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:16.823 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:40:17.297 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:40:17.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:17.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:17.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:17.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:17.771 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:40:18.248 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:40:18.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:18.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:18.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:18.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:18.726 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:40:19.204 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:40:19.679 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:40:20.152 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:40:20.624 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:40:21.096 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:40:21.567 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:40:22.038 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:40:22.509 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:40:22.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:22.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:22.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:22.853 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:22.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:22.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:22.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:22.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:22.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:22.857 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:22.857 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:22.857 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:40:22.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:22.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:22.859 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2016 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:27.857 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:27.857 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:27.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:27.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:27.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:27.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:27.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:27.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:40:27.869 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:27.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:40:27.870 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:40:27.872 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:40:27.872 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:40:27.873 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:40:27.873 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:27.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:27.873 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:40:27.874 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:40:27.874 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:40:27.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:27.874 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:40:27.874 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:40:27.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:40:27.875 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:27.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:27.875 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:40:27.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:40:27.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:40:27.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:40:27.877 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:40:27.877 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:40:27.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:27.879 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:40:27.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:40:27.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:40:27.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:40:27.879 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:40:27.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:40:27.880 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:40:27.880 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:40:27.880 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:40:27.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:27.885 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:40:28.368 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:40:28.414 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:28.416 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:40:28.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:40:28.418 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:40:28.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:28.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:28.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:40:28.847 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:40:28.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:28.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:28.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:28.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:29.325 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:40:29.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:40:29.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:40:29.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:40:29.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:40:29.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:40:29.803 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:40:29.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:29.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:29.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:29.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:30.281 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:40:30.754 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:40:30.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:30.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:30.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:30.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:40:31.701 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:40:31.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:31.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:31.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:31.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:32.174 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:40:32.652 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:40:32.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:32.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:32.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:32.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:33.130 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:40:33.602 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:40:34.073 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:40:34.543 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:40:35.015 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:40:35.487 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:40:35.962 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:40:36.435 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:40:36.913 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:40:37.385 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:40:37.856 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:40:38.326 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:40:38.804 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:40:39.281 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:40:39.759 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:40:40.237 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:40:40.714 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:40:41.192 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:40:41.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:41.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:41.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:41.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:41.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:41.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:41.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:41.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:41.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:41.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:41.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:41.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:41.300 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:40:41.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2881 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:41.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2881 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:41.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2881 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:41.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2881 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:41.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2881 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:41.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2881 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:46.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:46.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:46.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:46.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:46.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:46.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:46.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:46.315 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:40:46.315 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:46.315 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:40:46.316 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:40:46.319 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:40:46.320 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:40:46.320 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:40:46.320 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:46.321 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:46.321 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:40:46.321 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:40:46.322 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:40:46.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:46.322 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:40:46.322 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:40:46.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:40:46.323 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:46.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:46.323 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:40:46.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:40:46.323 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:40:46.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:40:46.325 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:40:46.325 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:40:46.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:40:46.329 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:40:46.329 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:40:46.329 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:40:46.334 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:40:46.817 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:40:46.858 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:46.860 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:40:46.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:40:46.862 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:40:46.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:46.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:46.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:40:46.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:40:46.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:40:46.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:40:46.865 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:40:46.865 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:40:47.295 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:40:47.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:47.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:47.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:47.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:47.772 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:40:47.907 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:48.250 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:40:48.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:48.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:48.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:48.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:48.453 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:48.727 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:40:48.975 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:49.205 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:40:49.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:49.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:49.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:49.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:49.683 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:40:50.161 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:40:50.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:50.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:50.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:50.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:50.639 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:40:50.998 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:51.117 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:40:51.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:51.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:51.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:51.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:51.508 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:51.594 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:40:52.032 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:52.072 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:40:52.550 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:40:52.563 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:53.027 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:40:53.504 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:40:53.982 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:40:54.459 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:40:54.585 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:40:54.937 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:40:55.415 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:40:55.893 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:40:56.371 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:40:56.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:40:56.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:40:56.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:40:56.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:40:56.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:40:56.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:40:56.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:40:56.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:40:56.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:40:56.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:40:56.600 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:40:56.600 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:40:56.600 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:40:56.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2193 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:56.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2193 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:56.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2193 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:40:56.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2193 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:01.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:01.603 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:01.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:01.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:01.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:01.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:01.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:01.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:01.616 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:01.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:01.617 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:01.619 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:01.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:01.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:01.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:01.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:01.621 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:01.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:01.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:01.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:01.623 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:01.623 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:01.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:01.623 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:01.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:01.624 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:01.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:01.624 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:01.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:01.626 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:01.626 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:01.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:01.626 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:01.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:01.626 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:01.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:01.626 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:01.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:01.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:01.631 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:01.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:01.636 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:41:02.120 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:41:02.155 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:41:02.157 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:41:02.158 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:41:02.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:02.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:02.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:02.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:02.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:02.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.309 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.309 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.309 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:02.309 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:02.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:02.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:02.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:02.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:02.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:02.597 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:41:02.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:02.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:02.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:02.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:02.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:02.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:02.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:02.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:02.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:02.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:02.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:02.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:02.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:02.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:02.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.074 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:41:03.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.089 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.089 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.154 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.154 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.180 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.180 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.236 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.236 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:03.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.299 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.299 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.299 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:03.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.482 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.482 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.548 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:41:03.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.629 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.629 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:03.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:03.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:03.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:03.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:03.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:03.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:03.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:03.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:03.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:03.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:03.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:03.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:03.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:03.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.022 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:41:04.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:04.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:04.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:04.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:04.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:04.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.420 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:04.420 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:04.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:04.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.499 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:41:04.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:04.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:04.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:04.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:04.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:04.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.681 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:04.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:04.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:04.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:04.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:04.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:04.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:04.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:04.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:04.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:04.976 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:41:04.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:04.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:04.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:04.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:05.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:05.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:05.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:05.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:05.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:05.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:05.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:05.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:05.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:05.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:05.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:05.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:05.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:05.188 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:41:05.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:05.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:10.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:10.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:10.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:10.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:10.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:10.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:10.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:10.195 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:10.195 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:10.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:10.196 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:10.200 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:10.200 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:10.200 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:10.200 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:10.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:10.200 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:10.200 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:10.201 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:10.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:10.203 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:10.203 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:10.203 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:10.203 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:10.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:10.204 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:10.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:10.204 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:10.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:10.206 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:10.206 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:10.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:10.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:10.210 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:10.210 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:10.210 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:10.215 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:41:10.699 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:41:10.745 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:41:10.747 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:41:10.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:10.748 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:41:10.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:10.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:10.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:10.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:10.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:10.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:10.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:10.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:10.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 01:41:10.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:10.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:10.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:10.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:10.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:11.176 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:41:11.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:11.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:11.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:11.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:11.654 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:41:12.132 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:41:12.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:12.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:12.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:12.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:12.610 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:41:12.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:12.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:12.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:12.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:12.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:12.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:12.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:12.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:12.866 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:12.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:12.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:12.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:12.866 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:12.866 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:17.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:17.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:17.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:17.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:17.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:17.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:17.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:17.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:17.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:17.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:17.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:17.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:17.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:17.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:17.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:17.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:17.881 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:17.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:17.882 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:17.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:17.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:17.883 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:17.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:17.883 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:17.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:17.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:17.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:17.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:17.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:17.885 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:17.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:17.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:17.886 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:17.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:17.886 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:17.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:17.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:17.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:17.890 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:17.890 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:17.890 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:17.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:17.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:17.893 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:41:22.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:22.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:22.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:22.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:22.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:22.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:22.903 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:22.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:22.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:22.905 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:22.905 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:22.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:22.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:22.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:22.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:22.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:22.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:22.907 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:22.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:22.907 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:22.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:22.909 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:22.909 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:22.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:22.909 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:22.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:22.909 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:22.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:22.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:22.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:22.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:22.913 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:22.913 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:22.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:41:23.400 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:41:23.440 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:41:23.443 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:41:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:23.445 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:41:23.878 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:41:23.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:23.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:23.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:23.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:24.358 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:41:24.840 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:41:24.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:24.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:25.320 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:41:25.799 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:41:25.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:25.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:25.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:25.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:26.277 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:41:26.758 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:41:26.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:26.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:26.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:27.239 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:41:27.721 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:41:27.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:27.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:27.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:27.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:28.202 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:41:28.683 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:41:28.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:28.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:28.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:28.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:28.937 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:28.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:28.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:28.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:28.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:28.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:28.937 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:41:33.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:33.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:33.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:33.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:33.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:33.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:33.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:33.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:33.949 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:33.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:33.950 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:33.956 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:33.956 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:33.956 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:33.956 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:33.957 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:33.957 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:33.957 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:33.957 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:33.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:33.961 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:33.961 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:33.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:33.962 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:33.962 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:33.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:33.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:33.962 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:33.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:33.965 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:33.965 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:33.965 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:33.965 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:33.965 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:33.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:33.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:33.966 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:33.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:33.968 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:33.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:33.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:33.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:33.968 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:33.969 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:33.969 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:33.969 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:33.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:33.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:33.974 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:41:34.458 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:41:34.497 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:41:34.499 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:41:34.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:34.501 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:41:34.939 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:41:34.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:34.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:34.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:34.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:35.418 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:41:35.898 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:41:35.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:35.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:35.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:35.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:36.379 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:41:36.860 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:41:36.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:36.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:36.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:36.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:37.338 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:41:37.817 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:41:37.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:37.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:37.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:37.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:38.297 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:41:38.767 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:41:38.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:38.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:38.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:38.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:39.235 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:39.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:39.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:39.511 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:41:39.511 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:39.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:39.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:39.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:39.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:39.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:39.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1184 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:41:44.514 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:44.514 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:44.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:44.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:44.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:44.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:44.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:44.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:44.529 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:44.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:44.530 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:44.532 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:44.533 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:44.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:44.533 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:44.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:44.534 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:44.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:44.535 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:44.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:44.536 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:44.536 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:44.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:44.536 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:44.537 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:44.537 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:44.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:44.537 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:44.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:44.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:44.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:44.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:44.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:44.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:44.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:44.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:44.538 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:44.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.541 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:44.542 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:44.542 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:44.542 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:44.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:44.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:44.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:44.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:44.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:44.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:44.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:44.544 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:41:49.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:41:49.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:41:49.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:49.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:49.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:49.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:49.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:41:49.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:49.561 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:49.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:41:49.562 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:41:49.567 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:41:49.567 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:41:49.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:49.568 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:49.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:41:49.569 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:41:49.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:41:49.570 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:41:49.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:49.571 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:41:49.571 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:41:49.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:49.571 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:49.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:41:49.571 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:41:49.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:41:49.571 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:41:49.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:49.573 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:41:49.574 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:41:49.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:49.574 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:41:49.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:41:49.574 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:41:49.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:41:49.574 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:41:49.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:41:49.578 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:41:49.578 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:41:49.578 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:41:49.583 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:41:50.065 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:41:50.112 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:41:50.114 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:41:50.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:41:50.116 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:41:50.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:41:50.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:41:50.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:41:50.541 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:41:50.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:50.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:50.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:50.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:51.014 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:41:51.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:41:51.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:41:51.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:41:51.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:41:51.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:41:51.489 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:41:51.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:51.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:51.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:51.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:51.961 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:41:52.433 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:41:52.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:52.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:52.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:52.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:52.903 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:41:53.380 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:41:53.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:53.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:53.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:53.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:53.858 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:41:54.330 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:41:54.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:41:54.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:41:54.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:41:54.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:41:54.803 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:41:55.279 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:41:55.756 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:41:56.228 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:41:56.699 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:41:57.170 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:41:57.640 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:41:58.111 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:41:58.583 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:41:59.053 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:41:59.528 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:42:00.000 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:42:00.477 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:42:00.955 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:42:01.433 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:42:01.911 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:42:02.382 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:42:02.860 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:42:03.338 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:42:03.815 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:42:04.292 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:42:04.770 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:42:04.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:04.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:04.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:04.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:04.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:04.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:04.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:04.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:04.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:04.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:04.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:04.925 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:04.925 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:42:04.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3299 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:04.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3299 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:04.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3299 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:04.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3299 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:04.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3299 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:04.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3299 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:09.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:09.925 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:09.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:09.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:09.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:09.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:09.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:09.939 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:09.939 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:09.940 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:09.940 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:42:09.943 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:42:09.943 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:42:09.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:09.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:09.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:09.944 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:42:09.945 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:09.945 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:42:09.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:09.946 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:42:09.946 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:42:09.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:09.946 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:09.946 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:09.946 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:42:09.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:09.946 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:42:09.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:09.948 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:42:09.948 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:42:09.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:09.948 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:09.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:09.948 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:42:09.949 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:09.949 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:42:09.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:09.951 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:42:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:42:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:42:09.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:42:09.951 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:42:09.952 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:42:09.952 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:42:09.952 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:42:09.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:09.957 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:42:10.441 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:42:10.484 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:10.487 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:10.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:10.490 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:42:10.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:10.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:10.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:42:10.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:10.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:10.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:10.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:42:10.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:42:10.532 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:10.536 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:10.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:10.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:10.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:10.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:10.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:10.918 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:42:10.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:10.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:10.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:10.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:11.396 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:42:11.874 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:42:11.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:11.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:11.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:11.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:12.352 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:42:12.829 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:42:12.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:12.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:12.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:12.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:13.306 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:42:13.784 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:42:13.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:13.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:13.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:13.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:14.262 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:42:14.740 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:42:14.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:14.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:14.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:14.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:15.218 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:42:15.696 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:42:16.174 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:42:16.652 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:42:17.130 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:42:17.608 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:42:18.086 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:42:18.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:18.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:18.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:18.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:18.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:18.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:18.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:18.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:18.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:18.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:18.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:18.562 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:42:18.562 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:23.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:23.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:23.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:23.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:23.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:23.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:23.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:23.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:23.578 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:23.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:23.578 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:42:23.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:42:23.582 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:42:23.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:23.583 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:23.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:23.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:42:23.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:23.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:42:23.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:23.585 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:23.585 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:42:23.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:23.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:42:23.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:42:23.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:23.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:23.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:23.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:42:23.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:23.588 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:42:23.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:42:23.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:42:23.591 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:42:23.591 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:42:23.591 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:23.596 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:42:24.079 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:42:24.117 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:24.119 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:24.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:24.121 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:42:24.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:24.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:24.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:42:24.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:24.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:24.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:24.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:42:24.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:42:24.172 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:24.175 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:24.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:24.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:24.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:24.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:24.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:24.557 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:42:24.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:24.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:24.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:24.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:25.035 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:42:25.512 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:42:25.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:25.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:25.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:25.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:25.990 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:42:26.468 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:42:26.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:26.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:26.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:26.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:26.947 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:42:27.425 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:42:27.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:27.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:27.902 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:42:28.381 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:42:28.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:28.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:28.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:28.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:28.858 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:42:29.337 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:42:29.814 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:42:30.292 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:42:30.770 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:42:31.248 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:42:31.726 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:42:32.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:32.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:32.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:32.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:32.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:32.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:32.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:32.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:32.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:32.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:32.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:32.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:32.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:32.202 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:32.202 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.203 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:32.204 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:37.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:37.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:37.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:37.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:37.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:37.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:37.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:37.217 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:37.217 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:37.218 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:37.218 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:42:37.222 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:42:37.222 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:42:37.223 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:37.223 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:37.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:37.223 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:42:37.223 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:37.223 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:42:37.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:37.226 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:42:37.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:42:37.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:37.227 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:37.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:37.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:42:37.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:37.228 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:42:37.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:37.230 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:42:37.230 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:42:37.230 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:37.230 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:37.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:37.230 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:42:37.230 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:37.231 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:42:37.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:42:37.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:42:37.235 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:42:37.235 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:42:37.235 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:37.240 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:42:37.724 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:42:37.769 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:37.771 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:37.772 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:42:37.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:37.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:37.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:37.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:42:37.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:37.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:37.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:37.801 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:42:37.801 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:42:37.816 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:37.819 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:37.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:37.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:37.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:37.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:37.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:38.200 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:42:38.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:38.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:38.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:38.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:38.678 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:42:39.156 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:42:39.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:39.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:39.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:39.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:39.634 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:42:40.112 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:42:40.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:40.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:40.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:40.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:40.590 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:42:41.069 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:42:41.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:41.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:41.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:41.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:41.547 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:42:42.025 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:42:42.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:42.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:42.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:42.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:42.503 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:42:42.982 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:42:43.460 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:42:43.938 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:42:44.416 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:42:44.894 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:42:45.372 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:42:45.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:45.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:45.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:45.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:45.849 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:42:45.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:45.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:45.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:42:45.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:45.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:45.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:45.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:42:45.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:42:45.916 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:45.921 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:45.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:45.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:45.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:45.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:45.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:46.327 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:42:46.805 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:42:47.283 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:42:47.762 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:42:48.240 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:42:48.718 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:42:49.196 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:42:49.674 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:42:50.152 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:42:50.630 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:42:51.107 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:42:51.585 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:42:52.064 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:42:52.542 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:42:53.020 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:42:53.497 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:42:53.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:53.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:53.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:53.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:53.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:53.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:53.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:53.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:53.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:53.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:53.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:53.954 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:53.954 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:53.954 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:42:53.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3569 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:53.954 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3569 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:42:58.953 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:42:58.953 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:42:58.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:58.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:58.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:58.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:58.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:42:58.967 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:58.967 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:58.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:42:58.968 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:42:58.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:42:58.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:42:58.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:58.972 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:58.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:42:58.973 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:42:58.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:42:58.973 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:42:58.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:58.974 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:42:58.974 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:42:58.975 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:58.975 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:58.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:42:58.975 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:42:58.975 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:42:58.975 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:42:58.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:58.976 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:42:58.977 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:42:58.977 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:58.977 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:42:58.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:42:58.977 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:42:58.977 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:42:58.977 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:42:58.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.980 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:42:58.980 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:42:58.980 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:42:58.980 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:42:58.985 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:42:59.469 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:42:59.507 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:59.509 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:59.510 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:42:59.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:59.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:42:59.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:42:59.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:42:59.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:59.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:59.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:59.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:42:59.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:42:59.562 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:42:59.565 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:42:59.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:42:59.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:42:59.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:42:59.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:59.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:42:59.947 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:42:59.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:42:59.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:42:59.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:42:59.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:00.425 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:43:00.903 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:43:00.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:00.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:00.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:00.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:01.381 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:43:01.859 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:43:01.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:01.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:01.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:01.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:02.337 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:43:02.816 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:43:02.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:02.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:02.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:02.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:03.294 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:43:03.772 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:43:03.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:03.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:03.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:03.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:04.250 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:43:04.728 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:43:05.204 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:43:05.681 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:43:06.159 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:43:06.638 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:43:07.116 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:43:07.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:07.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:07.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:07.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:07.594 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:43:07.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:07.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:07.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:43:07.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:07.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:07.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:07.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:43:07.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:43:07.640 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:07.646 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:07.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:07.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:07.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:07.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:07.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:08.072 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:43:08.550 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:43:09.027 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:43:09.506 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:43:09.984 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:43:10.461 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:43:10.939 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:43:11.417 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:43:11.895 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:43:12.373 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:43:12.851 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:43:13.329 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:43:13.807 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:43:14.285 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:43:14.764 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:43:15.242 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:43:15.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:15.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:15.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:15.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:15.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:15.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:15.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:15.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:15.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:43:15.673 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:43:15.673 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:43:15.673 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:43:15.673 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:43:15.673 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:43:15.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:15.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:20.678 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:43:20.678 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:43:20.678 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:43:20.678 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:43:20.678 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:43:20.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:43:20.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:43:20.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:43:20.681 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:20.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:43:20.681 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:43:20.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:43:20.682 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:43:20.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:43:20.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:20.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:43:20.682 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:43:20.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:43:20.682 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:43:20.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:43:20.683 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:43:20.683 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:43:20.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:43:20.684 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:43:20.684 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:43:20.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:20.685 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:43:20.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:43:20.686 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:43:20.686 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:43:20.686 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:20.691 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:43:21.175 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:43:21.216 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:21.218 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:21.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:21.220 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:43:21.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:21.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:21.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:43:21.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:21.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:21.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:21.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:43:21.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:43:21.267 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:21.271 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:21.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:21.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:21.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:21.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:21.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:21.652 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:43:21.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:21.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:21.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:21.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:22.131 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:43:22.609 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:43:22.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:22.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:22.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:22.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:23.087 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:43:23.564 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:43:23.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:23.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:23.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:23.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:24.043 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:43:24.521 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:43:24.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:24.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:24.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:24.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:24.999 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:43:25.478 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:43:25.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:25.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:25.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:25.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:25.956 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:43:26.434 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:43:26.912 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:43:27.390 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:43:27.868 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:43:28.346 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:43:28.824 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:43:29.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:29.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:29.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:29.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:29.302 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:43:29.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:29.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:29.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:43:29.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:29.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:29.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:29.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:43:29.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:43:29.348 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:29.353 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:29.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:29.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:29.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:29.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:29.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:29.779 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:43:30.258 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:43:30.736 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:43:31.214 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:43:31.692 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:43:32.170 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:43:32.648 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:43:33.127 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:43:33.605 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:43:34.083 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:43:34.561 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:43:35.039 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:43:35.517 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:43:35.995 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:43:36.474 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:43:36.952 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:43:37.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:37.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:37.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:37.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:37.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:37.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:37.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:37.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:37.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:43:37.382 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:43:37.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:43:37.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:43:37.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:43:37.383 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:43:37.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:43:37.383 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.383 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.383 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.383 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:37.384 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:43:42.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:43:42.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:43:42.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:43:42.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:43:42.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:43:42.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:43:42.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:43:42.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:43:42.400 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:42.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:43:42.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:43:42.402 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:43:42.403 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:43:42.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:43:42.403 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:42.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:43:42.403 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:43:42.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:43:42.403 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:43:42.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:43:42.405 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:43:42.405 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:43:42.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:43:42.407 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:43:42.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:43:42.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:43:42.409 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:43:42.409 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:43:42.409 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:43:42.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:43:42.414 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:43:42.898 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:43:42.933 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:42.935 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:42.937 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:43:42.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:42.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:42.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:42.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:43:42.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:42.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:42.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:42.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:43:42.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:43:42.990 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:42.994 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:42.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:43.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:43.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:43.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:43.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:43.375 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:43:43.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:43.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:43.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:43.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:43.848 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:43:44.324 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:43:44.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:44.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:44.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:44.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:44.802 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:43:45.280 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:43:45.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:45.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:45.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:45.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:45.758 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:43:46.236 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:43:46.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:46.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:46.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:46.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:46.713 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:43:47.191 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:43:47.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:43:47.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:43:47.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:43:47.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:43:47.669 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:43:48.147 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:43:48.625 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:43:49.104 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:43:49.581 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:43:50.059 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:43:50.538 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:43:51.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:51.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:51.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:51.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:51.015 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:43:51.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:51.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:51.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:43:51.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:51.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:51.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:51.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:43:51.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:43:51.062 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:51.067 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:51.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:51.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:51.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:51.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:51.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:51.493 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:43:51.970 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:43:52.448 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:43:52.926 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:43:53.403 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:43:53.881 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:43:54.359 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:43:54.837 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:43:55.315 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:43:55.793 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:43:56.271 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:43:56.749 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:43:57.227 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:43:57.705 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:43:58.183 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:43:58.661 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:43:59.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:59.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:59.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:59.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:59.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:43:59.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:43:59.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:43:59.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:59.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:59.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:59.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:43:59.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:43:59.132 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:43:59.135 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:43:59.139 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:43:59.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:43:59.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:43:59.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:43:59.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:59.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:43:59.617 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:44:00.095 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:44:00.573 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:44:01.051 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:44:01.529 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:44:02.007 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:44:02.485 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:44:02.963 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:44:03.441 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:44:03.919 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:44:04.397 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:44:04.874 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:44:05.352 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:44:05.830 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:44:06.308 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:44:06.786 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:44:07.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:07.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:07.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:07.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:07.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:07.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:07.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:44:07.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:07.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:07.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:07.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:44:07.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:44:07.206 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:07.211 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:07.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:07.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:07.220 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:07.220 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:07.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:07.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:07.263 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:44:07.741 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:44:08.219 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:44:08.696 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:44:09.174 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:44:09.652 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:44:10.129 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:44:10.608 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:44:11.085 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:44:11.564 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:44:12.042 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:44:12.519 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:44:12.996 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:44:13.474 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:44:13.952 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:44:14.430 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:44:14.908 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:44:15.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:15.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:15.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:15.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:15.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:15.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:15.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:15.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:15.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:44:15.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:44:15.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:44:15.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:44:15.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:44:15.232 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:44:15.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:15.232 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:20.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:44:20.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:44:20.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:44:20.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:44:20.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:44:20.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:44:20.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:44:20.246 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:44:20.246 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:20.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:44:20.247 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:44:20.248 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:44:20.249 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:44:20.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:44:20.249 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:20.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:44:20.250 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:44:20.250 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:44:20.250 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:44:20.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:44:20.251 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:44:20.251 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:44:20.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:44:20.253 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:44:20.253 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:44:20.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:44:20.256 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:44:20.256 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:44:20.256 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:20.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:20.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:20.261 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:44:20.744 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:44:20.785 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:20.787 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:20.789 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:44:20.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:20.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:20.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:20.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:44:20.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:20.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:20.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:20.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:44:20.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:44:20.836 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:20.840 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:20.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:20.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:20.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:20.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:21.222 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:44:21.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:21.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:21.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:21.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:21.700 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:44:22.178 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:44:22.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:22.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:22.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:22.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:22.656 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:44:23.134 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:44:23.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:23.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:23.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:23.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:23.612 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:44:24.090 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:44:24.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:24.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:24.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:24.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:24.568 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:44:25.046 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:44:25.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:25.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:25.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:25.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:25.524 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:44:26.002 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:44:26.480 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:44:26.958 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:44:27.436 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:44:27.914 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:44:28.393 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:44:28.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:28.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:28.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:28.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:28.871 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:44:28.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:28.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:28.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:44:28.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:28.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:28.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:28.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:44:28.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:44:28.917 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:28.922 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:28.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:28.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:28.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:28.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:28.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:29.349 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:44:29.827 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:44:30.305 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:44:30.783 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:44:31.262 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:44:31.740 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:44:32.218 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:44:32.696 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:44:33.175 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:44:33.653 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:44:34.131 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:44:34.610 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:44:35.088 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:44:35.566 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:44:36.044 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:44:36.522 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:44:36.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:36.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:36.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:36.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:36.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:36.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:36.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:36.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:36.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:44:36.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:44:36.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:44:36.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:44:36.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:44:36.949 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:44:36.949 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3561 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3561 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3561 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3561 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3561 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3561 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:36.949 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:44:41.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:44:41.950 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:44:41.951 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:44:41.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:44:41.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:44:41.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:44:41.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:44:41.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:44:41.965 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:41.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:44:41.965 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:44:41.972 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:44:41.972 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:44:41.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:44:41.972 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:41.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:44:41.973 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:44:41.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:44:41.973 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:44:41.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:41.976 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:44:41.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:44:41.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:44:41.976 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:41.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:44:41.976 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:44:41.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:44:41.977 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:44:41.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:41.979 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:44:41.979 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:44:41.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:44:41.979 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:44:41.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:44:41.980 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:44:41.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:44:41.980 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:44:41.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:41.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:44:41.984 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:44:41.984 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:44:41.984 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:44:41.989 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:44:42.473 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:44:42.509 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:42.511 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:42.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:42.513 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:44:42.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:42.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:42.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:44:42.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:42.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:42.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:42.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:44:42.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:44:42.566 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:42.570 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:42.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:42.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:42.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:42.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:42.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:42.949 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:44:42.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:42.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:42.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:42.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:43.427 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:44:43.905 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:44:43.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:43.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:43.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:43.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:44.383 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:44:44.862 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:44:44.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:44.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:44.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:44.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:45.340 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:44:45.818 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:44:45.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:45.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:45.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:45.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:46.296 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:44:46.773 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:44:46.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:44:46.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:44:46.991 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:44:46.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:44:47.251 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:44:47.729 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:44:48.207 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:44:48.685 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:44:49.163 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:44:49.641 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:44:50.119 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:44:50.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:50.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:50.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:50.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:50.597 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:44:50.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:50.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:50.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:44:50.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:50.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:50.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:50.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:44:50.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:44:50.643 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:50.647 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:50.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:50.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:50.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:50.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:50.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:51.074 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:44:51.552 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:44:52.030 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:44:52.508 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:44:52.986 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:44:53.463 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:44:53.941 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:44:54.419 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:44:54.896 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:44:55.374 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:44:55.852 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:44:56.330 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:44:56.808 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:44:57.285 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:44:57.763 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:44:58.241 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:44:58.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:58.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:58.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:58.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:58.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:44:58.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:44:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:44:58.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:58.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:58.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:58.685 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:44:58.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:44:58.710 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:44:58.713 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:44:58.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:44:58.718 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:44:58.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:44:58.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:44:58.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:58.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:44:59.196 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:44:59.674 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:45:00.151 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:45:00.629 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:45:01.107 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:45:01.586 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:45:02.064 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:45:02.541 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:45:03.018 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:45:03.496 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:45:03.974 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:45:04.451 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:45:04.929 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:45:05.407 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:45:05.885 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:45:06.363 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:45:06.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:06.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:06.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:06.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:06.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:06.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:06.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:45:06.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:06.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:06.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:06.746 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:45:06.746 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:45:06.783 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:06.787 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:06.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:06.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:06.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:06.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:06.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:06.840 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:45:07.318 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:45:07.796 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:45:08.274 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:45:08.751 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:45:09.229 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:45:09.706 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:45:10.184 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:45:10.661 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:45:11.139 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:45:11.617 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:45:12.095 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:45:12.573 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:45:13.051 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:45:13.528 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:45:14.006 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:45:14.484 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:45:14.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:14.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:14.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:14.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:14.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:14.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:14.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:14.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:14.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:45:14.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:45:14.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:45:14.812 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:45:14.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:45:14.812 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:45:14.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:45:19.818 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:45:19.818 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:45:19.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:45:19.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:45:19.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:45:19.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:45:19.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:45:19.829 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:45:19.829 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:45:19.830 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:45:19.830 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:45:19.834 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:45:19.834 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:45:19.835 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:45:19.835 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:45:19.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:45:19.836 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:45:19.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:45:19.836 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:45:19.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:19.837 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:45:19.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:45:19.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:45:19.838 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:45:19.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:45:19.838 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:45:19.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:45:19.838 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:45:19.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:19.840 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:45:19.840 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:45:19.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:45:19.841 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:45:19.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:45:19.841 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:45:19.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:45:19.841 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:45:19.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:45:19.845 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:45:19.845 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:45:19.845 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:45:19.850 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:45:20.333 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:45:20.372 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:20.374 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:20.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:20.376 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:45:20.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:20.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:20.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:45:20.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:20.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:20.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:20.405 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:45:20.405 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:45:20.426 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:20.429 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:20.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:20.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:20.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:20.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:20.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:20.810 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:45:20.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:20.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:20.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:20.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:21.288 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:45:21.766 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:45:21.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:21.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:21.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:21.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:22.244 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:45:22.722 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:45:22.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:22.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:22.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:22.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:23.200 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:45:23.677 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:45:23.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:23.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:23.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:23.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:24.155 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:45:24.633 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:45:24.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:45:24.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:45:24.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:45:24.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:45:25.110 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:45:25.588 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:45:26.067 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:45:26.545 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:45:27.022 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:45:27.500 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:45:27.978 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:45:28.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:28.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:28.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:28.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:28.455 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:45:28.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:28.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:28.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:45:28.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:28.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:28.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:28.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:45:28.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:45:28.501 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:28.506 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:28.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:28.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:28.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:28.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:28.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:28.932 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:45:29.410 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:45:29.888 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:45:30.366 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:45:30.844 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:45:31.322 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:45:31.800 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:45:32.278 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:45:32.755 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:45:33.233 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:45:33.711 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:45:34.189 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:45:34.667 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:45:35.145 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:45:35.623 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:45:36.101 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:45:36.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:36.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:36.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:36.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:36.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:36.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:36.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:45:36.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:36.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:36.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:36.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:45:36.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:45:36.571 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:36.574 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:36.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:36.578 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:45:36.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:36.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:36.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:36.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:37.055 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:45:37.533 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:45:38.010 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:45:38.488 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:45:38.966 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:45:39.443 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:45:39.921 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:45:40.398 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:45:40.876 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:45:41.353 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:45:41.832 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:45:42.309 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:45:42.787 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:45:43.266 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:45:43.744 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:45:44.221 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:45:44.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:44.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:44.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:44.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:44.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:44.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:44.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:45:44.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:44.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:44.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:44.608 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:45:44.608 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:45:44.641 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:44.644 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:44.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:44.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:44.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:44.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:44.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:44.698 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:45:45.176 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:45:45.654 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:45:46.133 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:45:46.611 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:45:47.089 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:45:47.567 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:45:48.044 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:45:48.522 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:45:49.000 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:45:49.478 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:45:49.956 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:45:50.433 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:45:50.911 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:45:51.389 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:45:51.866 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:45:52.344 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:45:52.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:52.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:52.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:52.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:52.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:45:52.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:45:52.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:45:52.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:52.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:52.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:52.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:45:52.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:45:52.718 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:45:52.722 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:45:52.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:45:52.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:45:52.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:45:52.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:52.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:45:52.822 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:45:53.299 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:45:53.776 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:45:54.254 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 01:45:54.732 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 01:45:55.210 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 01:45:55.688 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 01:45:56.166 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 01:45:56.644 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 01:45:57.121 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 01:45:57.599 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 01:45:58.077 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 01:45:58.555 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 01:45:59.033 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 01:45:59.511 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 01:45:59.988 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 01:46:00.466 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 01:46:00.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:00.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:00.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:00.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:00.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:00.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:00.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:46:00.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:00.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:00.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:00.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:46:00.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:46:00.794 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:00.796 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:00.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:00.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:00.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:00.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:00.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:00.944 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 01:46:01.421 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 01:46:01.898 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 01:46:02.377 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 01:46:02.855 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 01:46:03.333 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 01:46:03.810 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 01:46:04.287 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 01:46:04.765 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 01:46:05.243 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 01:46:05.721 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 01:46:06.199 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 01:46:06.687 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 01:46:07.165 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 01:46:07.642 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 01:46:08.120 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 01:46:08.597 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 01:46:08.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:08.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:08.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:08.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:08.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:08.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:08.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:46:08.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:08.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:08.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:08.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:46:08.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:46:08.878 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:08.882 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:08.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:08.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:08.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:08.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:08.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:09.074 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 01:46:09.552 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 01:46:10.030 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 01:46:10.508 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 01:46:10.986 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 01:46:11.464 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 01:46:11.940 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 01:46:12.418 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 01:46:12.896 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 01:46:13.374 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 01:46:13.852 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 01:46:14.330 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 01:46:14.808 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 01:46:15.286 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 01:46:15.764 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 01:46:16.242 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 01:46:16.742 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 01:46:16.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:16.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:16.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:16.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:16.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:16.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:16.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:46:16.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:16.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:16.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:16.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:46:16.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:46:16.923 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:16.924 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:16.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:16.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:16.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:16.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:16.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:17.218 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 01:46:17.696 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 01:46:18.173 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 01:46:18.651 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 01:46:19.129 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 01:46:19.606 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 01:46:20.084 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 01:46:20.562 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 01:46:21.040 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 01:46:21.517 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 01:46:21.995 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 01:46:22.473 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 01:46:22.950 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 01:46:23.427 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 01:46:23.905 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 01:46:24.382 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 01:46:24.860 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 01:46:24.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:24.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:24.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:24.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:24.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:24.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:24.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:24.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:24.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:46:24.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:46:24.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:46:24.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:46:24.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:46:24.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:46:24.942 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:46:29.945 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:46:29.945 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:46:29.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:46:29.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:46:29.950 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:46:29.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:46:29.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:46:29.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:46:29.966 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:29.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:46:29.967 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:46:29.968 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:46:29.968 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:46:29.969 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:46:29.969 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:29.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:46:29.969 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:46:29.970 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:46:29.970 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:46:29.970 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:46:29.971 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:46:29.971 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:46:29.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:46:29.972 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:46:29.972 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:46:29.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:46:29.975 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:46:29.975 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:46:29.975 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:29.979 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:46:30.462 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:46:30.504 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:30.506 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:30.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:30.508 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:46:30.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:30.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:30.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:46:30.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:30.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:30.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:30.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:46:30.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:46:30.554 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:30.556 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:30.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:30.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:30.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:30.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:30.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:30.939 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:46:30.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:30.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:30.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:30.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:31.417 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:46:31.896 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:46:31.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:31.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:31.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:31.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:32.374 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:46:32.852 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:46:32.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:32.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:32.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:32.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:33.330 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:46:33.808 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:46:33.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:33.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:33.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:33.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:34.286 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:46:34.764 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:46:34.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:34.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:34.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:34.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:35.242 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:46:35.720 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:46:36.199 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:46:36.677 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:46:37.155 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:46:37.633 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:46:38.111 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:46:38.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:38.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:38.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:38.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:38.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:38.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:38.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:46:38.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:38.588 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:46:38.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:38.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:38.589 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:46:38.589 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:46:38.635 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:38.640 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:38.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:38.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:38.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:38.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:38.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:39.066 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:46:39.544 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:46:40.023 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:46:40.502 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:46:40.980 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:46:41.458 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:46:41.936 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:46:42.415 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:46:42.893 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:46:43.372 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:46:43.850 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:46:44.328 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:46:44.807 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:46:45.286 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:46:45.764 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:46:46.242 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:46:46.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:46.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:46.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:46.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:46.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:46.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:46.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:46.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:46.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:46:46.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:46:46.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:46:46.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:46:46.672 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:46:46.672 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:46:46.672 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:46:46.672 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:46:46.672 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:46:46.672 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:46:46.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:46:46.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:46:46.673 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:46:51.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:46:51.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:46:51.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:46:51.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:46:51.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:46:51.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:46:51.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:46:51.685 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:46:51.686 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:51.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:46:51.686 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:46:51.690 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:46:51.691 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:46:51.691 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:46:51.691 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:51.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:46:51.692 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:46:51.693 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:46:51.693 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:46:51.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:51.694 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:46:51.694 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:46:51.695 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:46:51.695 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:51.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:46:51.696 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:46:51.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:46:51.696 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:46:51.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:51.697 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:46:51.697 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:46:51.697 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:46:51.697 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:46:51.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:46:51.698 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:46:51.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:46:51.698 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:46:51.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:51.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:46:51.702 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:46:51.702 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:46:51.702 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:46:51.707 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:46:52.191 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:46:52.230 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:46:52.232 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:46:52.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:52.235 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:46:52.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:46:52.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:46:52.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:46:52.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:52.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:52.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:52.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:46:52.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:46:52.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:46:52.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:46:52.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:46:52.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:52.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:46:52.668 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:46:52.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:52.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:52.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:52.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:53.146 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:46:53.623 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:46:53.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:53.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:53.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:53.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:54.101 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:46:54.579 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:46:54.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:54.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:54.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:54.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:55.057 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:46:55.535 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:46:55.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:55.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:55.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:55.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:56.013 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:46:56.491 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:46:56.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:46:56.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:46:56.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:46:56.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:46:56.969 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:46:57.447 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:46:57.922 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:46:58.400 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:46:58.877 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:46:59.355 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:46:59.833 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:47:00.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:00.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:00.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:00.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:00.311 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:47:00.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:00.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:00.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:00.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:00.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:00.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:00.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:00.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:00.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:00.319 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:00.319 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:47:05.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:05.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:05.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:05.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:05.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:05.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:05.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:05.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:05.335 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:05.336 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:05.336 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:47:05.339 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:47:05.339 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:47:05.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:05.340 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:05.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:05.341 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:47:05.341 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:05.341 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:47:05.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:05.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:47:05.342 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:47:05.342 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:05.342 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:05.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:05.343 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:47:05.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:05.343 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:47:05.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:05.345 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:05.345 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:47:05.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:05.347 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.348 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:47:05.348 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:47:05.348 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:47:05.348 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:05.353 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:47:05.837 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:47:05.882 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:47:05.884 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:47:05.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:05.886 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:47:05.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:05.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:05.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:47:05.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:05.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:47:05.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:47:05.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:47:05.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:47:05.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:05.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:47:05.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:47:05.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:05.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:06.315 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:47:06.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:06.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:06.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:06.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:06.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:47:07.272 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:47:07.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:07.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:07.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:07.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:07.750 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:47:08.228 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:47:08.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:08.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:08.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:08.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:08.705 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:47:09.183 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:47:09.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:09.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:09.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:09.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:09.662 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:47:10.140 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:47:10.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:10.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:10.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:10.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:10.619 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:47:11.097 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:47:11.575 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:47:12.054 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:47:12.532 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:47:13.010 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:47:13.489 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:47:13.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:13.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:13.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:13.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:13.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:13.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:13.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:13.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:13.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:13.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:13.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:13.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:13.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:13.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:13.963 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:47:18.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:18.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:18.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:18.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:18.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:18.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:18.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:18.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:18.974 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:18.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:18.974 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:47:18.976 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:47:18.976 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:47:18.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:18.976 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:18.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:18.977 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:47:18.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:18.977 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:47:18.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:18.978 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:18.978 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:47:18.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:18.980 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:18.980 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:47:18.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:47:18.982 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:47:18.982 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:47:18.982 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:18.987 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:47:19.471 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:47:19.503 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:47:19.505 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:47:19.507 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:47:19.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:19.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:19.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:19.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:47:19.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:19.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:47:19.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:47:19.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:47:19.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:47:19.948 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:47:19.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:19.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:19.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:19.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:20.426 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:47:20.904 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:47:20.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:20.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:20.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:20.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:21.381 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:47:21.859 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:47:21.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:21.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:21.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:21.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:22.337 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:47:22.815 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:47:22.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:22.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:22.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:22.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:23.293 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:47:23.770 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:47:23.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:23.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:23.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:23.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:24.248 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:47:24.726 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:47:25.204 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:47:25.681 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:47:26.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:26.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:26.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:26.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:26.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:26.031 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:47:31.034 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:31.034 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:31.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:31.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:31.038 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:31.038 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:31.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:31.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:31.049 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:31.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:31.049 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:47:31.054 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:47:31.054 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:47:31.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:31.055 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:31.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:31.055 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:47:31.055 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:31.055 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:47:31.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:31.058 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:47:31.058 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:47:31.058 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:31.058 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:31.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:31.058 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:47:31.059 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:31.059 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:47:31.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:31.061 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:47:31.061 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:47:31.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:31.061 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:31.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:31.061 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:47:31.062 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:31.062 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:47:31.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:31.065 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:47:31.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:47:31.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:47:31.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:47:31.065 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:47:31.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.066 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:47:31.066 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:47:31.066 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:47:31.066 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:31.071 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:47:31.556 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:47:31.590 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:47:31.591 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:47:31.592 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:47:31.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:31.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:31.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:31.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:47:31.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:31.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:47:31.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:47:31.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:47:31.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:47:32.032 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:47:32.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:32.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:32.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:32.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:32.510 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:47:32.988 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:47:33.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:33.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:33.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:33.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:33.465 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:47:33.942 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:47:34.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:34.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:34.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:34.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:34.420 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:47:34.898 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:47:35.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:35.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:35.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:35.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:35.375 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:47:35.853 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:47:36.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:36.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:36.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:36.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:36.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:36.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:36.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:36.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:36.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:36.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:36.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:36.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:36.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:36.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1078 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:47:36.333 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:47:36.818 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:47:37.305 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:47:37.789 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:47:38.273 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:47:38.761 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:47:39.246 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:47:39.731 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:47:40.215 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:47:40.701 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:47:41.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:41.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:41.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:41.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:41.116 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:47:41.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:41.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:41.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:41.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:41.124 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:41.124 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:41.124 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:41.124 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:41.124 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:41.125 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:41.125 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:47:41.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:41.127 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:41.127 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:47:41.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:41.128 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:41.128 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:47:41.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:47:41.131 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:47:41.131 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:47:41.131 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:41.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:41.132 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:41.132 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:41.132 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:47:46.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:47:46.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:47:46.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:46.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:46.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:46.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:46.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:46.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:46.147 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:46.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:47:46.147 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:47:46.149 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:47:46.149 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:47:46.150 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:46.150 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:46.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:47:46.151 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:47:46.152 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:47:46.152 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:47:46.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:46.152 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:47:46.153 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:47:46.153 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:46.153 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:46.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:47:46.153 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:47:46.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:47:46.154 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:47:46.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:46.155 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:47:46.156 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:47:46.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:46.156 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:47:46.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:47:46.156 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:47:46.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:47:46.156 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:47:46.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:47:46.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:47:46.160 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:47:46.160 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:47:46.160 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:47:46.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:47:46.165 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:47:46.649 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:47:46.694 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:47:46.696 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:47:46.698 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:47:46.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:47:46.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:47:46.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:47:46.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:47:46.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:47:46.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:47:46.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:47:46.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:47:46.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:47:47.127 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:47:47.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:47.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:47.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:47.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:47.605 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:47:48.082 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:47:48.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:48.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:48.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:48.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:48.560 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:47:49.038 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:47:49.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:49.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:49.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:49.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:49.515 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:47:49.993 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:47:50.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:50.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:50.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:50.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:50.471 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:47:50.949 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:47:51.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:51.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:47:51.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:47:51.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:47:51.426 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:47:51.904 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:47:52.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:52.382 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:47:52.859 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:47:53.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:53.337 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:47:53.814 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:47:54.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:54.292 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:47:54.770 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:47:55.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:55.248 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:47:55.725 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:47:56.203 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:47:56.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:47:56.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:47:56.682 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:47:57.162 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:47:57.643 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:47:58.121 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:47:58.599 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:47:59.077 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:47:59.555 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:48:00.033 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:48:00.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:00.511 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:48:00.989 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:48:01.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:01.466 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:48:01.944 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:48:02.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:02.422 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:48:02.899 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:48:03.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:03.377 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:48:03.855 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:48:04.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:04.333 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:48:04.810 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:48:05.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:05.288 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:48:05.765 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:48:06.243 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:48:06.721 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:48:07.199 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:48:07.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:07.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:07.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:07.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:07.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:07.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:07.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:07.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:07.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:07.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:48:07.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:48:07.318 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:48:07.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:07.319 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4515 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:12.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:48:12.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:48:12.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:12.321 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:12.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:12.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:12.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:12.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:48:12.330 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:12.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:48:12.331 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:48:12.335 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:48:12.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:48:12.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:48:12.336 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:12.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:12.336 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:48:12.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:48:12.337 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:48:12.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:12.341 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:48:12.341 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:48:12.341 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:48:12.341 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:12.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:12.342 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:48:12.342 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:48:12.342 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:48:12.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:12.345 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:48:12.345 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:48:12.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:48:12.345 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:12.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:12.346 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:48:12.346 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:48:12.346 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:48:12.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:48:12.351 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:48:12.351 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:48:12.351 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:12.356 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:48:12.839 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:48:12.887 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:48:12.889 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:48:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:12.891 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:48:12.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:12.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:12.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:48:12.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:12.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:12.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:12.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:48:12.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:48:12.931 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:48:12.934 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:48:12.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 01:48:12.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:12.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:12.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:12.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:13.315 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:48:13.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:13.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:13.359 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:13.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:13.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 01:48:13.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:13.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:13.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:13.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:13.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:13.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:13.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:13.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:13.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:13.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:13.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:48:13.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:48:13.765 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:48:13.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:13.766 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:18.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:48:18.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:48:18.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:18.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:18.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:18.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:18.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:18.779 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:48:18.779 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:18.779 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:48:18.779 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:48:18.783 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:48:18.784 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:48:18.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:48:18.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:18.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:18.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:48:18.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:48:18.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:48:18.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:18.788 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:48:18.788 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:48:18.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:48:18.788 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:18.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:18.789 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:48:18.789 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:48:18.789 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:48:18.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:18.791 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:48:18.791 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:48:18.792 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:48:18.792 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:18.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:18.792 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:48:18.792 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:48:18.792 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:48:18.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:48:18.797 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:48:18.797 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:48:18.797 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:18.802 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:48:19.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:48:19.329 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:48:19.331 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:48:19.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:19.334 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:48:19.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:19.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:19.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:48:19.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:19.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:19.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:19.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:48:19.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:48:19.377 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:48:19.381 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:48:19.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 01:48:19.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:19.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:19.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:19.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:19.761 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:48:19.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:19.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:19.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:19.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:20.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 01:48:20.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:20.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:20.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:20.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:20.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:20.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:20.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:20.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:20.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:20.212 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:20.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:20.212 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:48:20.212 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:48:20.212 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:48:20.213 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:20.213 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:20.213 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:20.213 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:20.213 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:20.213 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:48:25.210 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:48:25.210 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:48:25.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:25.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:25.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:25.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:25.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:48:25.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:48:25.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:25.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:48:25.225 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:48:25.230 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:48:25.230 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:48:25.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:48:25.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:25.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:48:25.232 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:48:25.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:48:25.232 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:48:25.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:25.235 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:48:25.235 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:48:25.235 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:48:25.235 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:25.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:48:25.235 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:48:25.236 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:48:25.236 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:48:25.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:25.238 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:48:25.239 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:48:25.239 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:48:25.239 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:48:25.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:48:25.239 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:48:25.239 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:48:25.239 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:48:25.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:25.242 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:48:25.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:48:25.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:48:25.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:48:25.242 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.243 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:48:25.243 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:48:25.243 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:48:25.243 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:48:25.248 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:48:25.731 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:48:25.777 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:48:25.779 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:48:25.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:25.781 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:48:25.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:25.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:25.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:48:25.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:25.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:25.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:25.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:48:25.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:48:25.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:25.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:25.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:25.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:25.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:26.208 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:48:26.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:26.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:26.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:26.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:26.686 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:48:27.164 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:48:27.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:27.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:27.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:27.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:27.642 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:48:28.120 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:48:28.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:28.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:28.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:28.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:28.599 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:48:29.077 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:48:29.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:29.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:29.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:29.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:29.555 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:48:30.032 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:48:30.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:48:30.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:48:30.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:48:30.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:48:30.510 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:48:30.988 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:48:31.467 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:48:31.944 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:48:32.422 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:48:32.900 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:48:33.378 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:48:33.856 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:48:34.334 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:48:34.812 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:48:35.290 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:48:35.768 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:48:36.246 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:48:36.724 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:48:37.201 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:48:37.680 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:48:38.158 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:48:38.635 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:48:39.114 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:48:39.591 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:48:40.070 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:48:40.547 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:48:41.025 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:48:41.503 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:48:41.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:41.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:41.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:41.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:41.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:41.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:41.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:48:41.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:41.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:41.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:41.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:48:41.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:48:41.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:41.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:41.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:41.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:41.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:41.980 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:48:42.458 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:48:42.937 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:48:43.414 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:48:43.892 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:48:44.370 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:48:44.848 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:48:45.326 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:48:45.804 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:48:46.282 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:48:46.759 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:48:47.237 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:48:47.716 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:48:48.193 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:48:48.671 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:48:49.149 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:48:49.628 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:48:50.106 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:48:50.584 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:48:51.062 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:48:51.540 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:48:52.018 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:48:52.495 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:48:52.973 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:48:53.450 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:48:53.927 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:48:54.405 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:48:54.883 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:48:55.361 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:48:55.838 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:48:56.316 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:48:56.794 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:48:57.273 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:48:57.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:57.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:57.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:57.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:57.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:48:57.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:48:57.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:48:57.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:57.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:57.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:57.483 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:48:57.483 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:48:57.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:48:57.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:48:57.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:48:57.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:57.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:48:57.750 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:48:58.228 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:48:58.706 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:48:59.183 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:48:59.661 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 01:49:00.139 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 01:49:00.617 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 01:49:01.095 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 01:49:01.573 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 01:49:02.051 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 01:49:02.529 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 01:49:03.007 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 01:49:03.485 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 01:49:03.963 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 01:49:04.441 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 01:49:04.919 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 01:49:05.397 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 01:49:05.876 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 01:49:06.353 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 01:49:06.831 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 01:49:07.309 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 01:49:07.787 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 01:49:08.266 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 01:49:08.742 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 01:49:09.220 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 01:49:09.698 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 01:49:10.176 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 01:49:10.654 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 01:49:11.132 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 01:49:11.610 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 01:49:12.087 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 01:49:12.564 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 01:49:13.042 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 01:49:13.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:13.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:13.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:49:13.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:49:13.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:49:13.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:49:13.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:49:13.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:13.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:49:13.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:49:13.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:49:13.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:49:13.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:13.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:13.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:49:13.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:49:13.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:13.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:13.520 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 01:49:13.999 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 01:49:14.477 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 01:49:14.955 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 01:49:15.433 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 01:49:15.910 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 01:49:16.388 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 01:49:16.866 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 01:49:17.344 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 01:49:17.822 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 01:49:18.300 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 01:49:18.778 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 01:49:19.256 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 01:49:19.734 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 01:49:20.212 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 01:49:20.690 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 01:49:21.168 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 01:49:21.647 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 01:49:22.125 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 01:49:22.603 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 01:49:23.080 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 01:49:23.558 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 01:49:24.036 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 01:49:24.515 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 01:49:24.992 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 01:49:25.470 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 01:49:25.948 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 01:49:26.426 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 01:49:26.903 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 01:49:27.380 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 01:49:27.858 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 01:49:28.335 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 01:49:28.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:28.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:28.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:49:28.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:49:28.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:28.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:28.784 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:49:28.784 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:49:28.784 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:28.784 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=13563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:33.784 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:49:33.784 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:49:33.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:33.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:33.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:33.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:33.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:33.796 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:49:33.796 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:33.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:49:33.797 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:49:33.803 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:49:33.803 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:49:33.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:49:33.804 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:33.804 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:33.804 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:49:33.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:49:33.804 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:49:33.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:33.808 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:49:33.808 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:49:33.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:49:33.808 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:33.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:33.809 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:49:33.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:49:33.809 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:49:33.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:33.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:49:33.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:49:33.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:49:33.812 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:33.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:33.812 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:49:33.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:49:33.813 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:49:33.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:33.816 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:49:33.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:49:33.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:49:33.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.817 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:49:33.817 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:49:33.817 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:49:33.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:49:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:49:33.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:49:33.820 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:49:33.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:38.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:49:38.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:49:38.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:38.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:38.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:38.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:38.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:38.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:49:38.836 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:38.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:49:38.836 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:49:38.839 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:49:38.839 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:49:38.840 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:49:38.840 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:38.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:38.841 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:49:38.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:49:38.841 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:49:38.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:38.843 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:49:38.843 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:49:38.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:49:38.843 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:38.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:38.844 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:49:38.844 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:49:38.844 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:49:38.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:49:38.846 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:49:38.846 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:49:38.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:38.849 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.850 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:49:38.850 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:49:38.851 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:49:38.851 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:38.855 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:49:39.340 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:49:39.382 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:49:39.382 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:49:39.383 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:49:39.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:39.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:49:39.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:49:39.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:49:39.420 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:49:39.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:39.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:49:39.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:49:39.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:49:39.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:49:39.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:39.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:49:39.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:49:39.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:39.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:39.817 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:49:39.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:39.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:39.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:39.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:40.295 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:49:40.773 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:49:40.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:40.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:40.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:40.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:41.251 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:49:41.729 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:49:41.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:41.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:41.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:41.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:42.207 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:49:42.685 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:49:42.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:42.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:42.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:42.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:43.163 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:49:43.641 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:49:43.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:43.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:43.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:43.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:44.118 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:49:44.596 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:49:45.075 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:49:45.553 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:49:46.031 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:49:46.509 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:49:46.987 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:49:47.465 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:49:47.943 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:49:48.421 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:49:48.899 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:49:49.377 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:49:49.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:49.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:49.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:49:49.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:49:49.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:49.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:49.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:49.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:49.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:49.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:49.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:49.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:49.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:49:49.838 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:49:49.838 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:49:49.838 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.838 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.838 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.838 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:49.839 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:49:54.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:49:54.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:49:54.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:54.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:54.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:54.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:54.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:49:54.854 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:49:54.854 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:54.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:49:54.855 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:49:54.858 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:49:54.858 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:49:54.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:49:54.859 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:54.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:49:54.860 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:49:54.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:49:54.860 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:49:54.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:54.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:49:54.861 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:49:54.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:49:54.861 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:54.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:49:54.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:49:54.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:49:54.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:49:54.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:54.863 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:49:54.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:49:54.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:49:54.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:49:54.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:49:54.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:49:54.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:49:54.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:49:54.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:54.866 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:49:54.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:49:54.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:49:54.867 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:49:54.867 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:49:54.867 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:49:54.872 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:49:55.355 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:49:55.396 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:49:55.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:55.399 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:49:55.401 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:49:55.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:49:55.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:49:55.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:49:55.442 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:49:55.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:55.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:49:55.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:49:55.445 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:49:55.445 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:49:55.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:49:55.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:49:55.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:49:55.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:55.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:49:55.831 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:49:55.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:55.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:55.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:55.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:56.309 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:49:56.787 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:49:56.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:56.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:56.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:56.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:57.265 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:49:57.743 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:49:57.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:57.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:57.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:57.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:58.221 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:49:58.699 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:49:58.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:58.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:58.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:58.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:49:59.177 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:49:59.654 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:49:59.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:49:59.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:49:59.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:49:59.879 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:00.132 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:50:00.610 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:50:01.089 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:50:01.566 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:50:02.045 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:50:02.523 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:50:03.000 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:50:03.478 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:50:03.957 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:50:04.434 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:50:04.912 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:50:05.390 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:50:05.867 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:50:06.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:06.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:06.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:50:06.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:50:06.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:06.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:06.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:06.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:06.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:06.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:06.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:06.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:06.334 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:50:06.334 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:50:06.334 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:50:06.334 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2449 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:06.334 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2449 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:06.334 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2449 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:06.334 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2449 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:06.334 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2449 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:06.335 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2449 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:11.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:50:11.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:50:11.339 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:11.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:11.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:11.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:11.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:11.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:50:11.352 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:11.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:50:11.352 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:50:11.356 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:50:11.356 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:50:11.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:50:11.357 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:11.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:11.357 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:50:11.358 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:50:11.358 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:50:11.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:11.360 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:50:11.360 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:50:11.360 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:50:11.360 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:11.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:11.360 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:50:11.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:50:11.361 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:50:11.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:11.364 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:50:11.364 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:50:11.364 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:50:11.364 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:11.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:11.365 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:50:11.365 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:50:11.365 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:50:11.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:50:11.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.370 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:50:11.370 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:50:11.370 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:50:11.370 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:11.375 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:50:11.859 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:50:11.902 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:50:11.904 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:11.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:11.907 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:50:11.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:50:11.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:50:11.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:50:11.946 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:11.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:11.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:50:11.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:50:11.948 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:50:11.948 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:50:12.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:12.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:50:12.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:50:12.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:12.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:12.335 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:50:12.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:12.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:12.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:12.813 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:50:13.291 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:50:13.316 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:13.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:13.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:13.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:13.769 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:50:14.246 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:50:14.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:14.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:14.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:14.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:14.724 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:50:15.203 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:50:15.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:15.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:15.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:15.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:15.680 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:50:16.159 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:50:16.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:16.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:16.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:16.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:16.637 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:50:17.115 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:50:17.593 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:50:18.068 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:50:18.546 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:50:19.023 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:50:19.501 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:50:19.979 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:50:20.457 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:50:20.935 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:50:21.413 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:50:21.891 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:50:22.369 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:50:22.847 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:50:23.326 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:50:23.803 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:50:24.281 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:50:24.759 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:50:25.236 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:50:25.715 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:50:26.193 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:50:26.670 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:50:27.148 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:50:27.627 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:50:28.105 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:50:28.583 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:50:29.062 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:50:29.540 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:50:30.018 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:50:30.496 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:50:30.974 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:50:31.452 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:50:31.930 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:50:32.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:32.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:32.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:50:32.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:50:32.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:32.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:32.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:32.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:32.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:32.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:32.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:32.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:32.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:50:32.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:50:32.052 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:50:37.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:50:37.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:50:37.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:37.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:37.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:37.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:37.067 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:37.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:50:37.069 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:37.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:50:37.070 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:50:37.073 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:50:37.073 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:50:37.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:50:37.074 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:37.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:37.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:50:37.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:50:37.074 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:50:37.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:37.077 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:50:37.077 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:50:37.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:50:37.078 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:37.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:37.079 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:50:37.079 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:50:37.079 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:50:37.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:37.080 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:50:37.080 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:50:37.080 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:50:37.080 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:37.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:37.081 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:50:37.081 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:50:37.081 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:50:37.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:37.083 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:50:37.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:50:37.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.084 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:50:37.084 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:50:37.084 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:50:37.084 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:37.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:37.089 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:50:37.573 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:50:37.613 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:50:37.615 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:37.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:37.617 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:50:37.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:50:37.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:50:37.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:50:37.656 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:37.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:37.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:50:37.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:50:37.659 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:50:37.659 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:50:37.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:37.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:50:37.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:50:37.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:37.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:38.050 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:50:38.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:38.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:38.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:38.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:38.527 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:50:38.543 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:39.005 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:50:39.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:39.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:39.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:39.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:39.483 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:50:39.517 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:39.961 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:50:40.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:40.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:40.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:40.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:40.440 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:50:40.492 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:40.917 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:50:41.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:41.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:41.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:41.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:41.395 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:50:41.466 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:41.873 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:50:42.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:42.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:42.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:42.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:42.351 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:50:42.441 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:42.829 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:50:43.306 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:50:43.414 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:43.782 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:50:44.260 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:50:44.387 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:44.738 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:50:45.216 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:50:45.361 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:45.694 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:50:46.171 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:50:46.335 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:46.650 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:50:47.127 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:50:47.310 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:47.605 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:50:48.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:48.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:48.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:50:48.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:50:48.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:48.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:48.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:48.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:48.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:48.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:48.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:48.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:48.074 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:50:48.074 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:50:48.074 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.075 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.076 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.076 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.076 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.076 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.076 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:48.076 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:50:53.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:50:53.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:50:53.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:53.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:53.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:53.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:53.089 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:50:53.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:50:53.090 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:53.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:50:53.090 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:50:53.094 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:50:53.094 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:50:53.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:50:53.095 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:53.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:50:53.096 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:50:53.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:50:53.096 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:50:53.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:53.097 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:50:53.098 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:50:53.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:50:53.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:53.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:50:53.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:50:53.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:50:53.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:50:53.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:50:53.101 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:50:53.101 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:50:53.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:50:53.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:50:53.106 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:50:53.106 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:50:53.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:50:53.591 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:50:53.632 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:50:53.633 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:53.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:53.634 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:50:53.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:50:53.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:50:53.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:50:53.665 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:50:53.668 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:53.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:53.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:50:53.669 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:50:53.669 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:50:53.669 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:50:53.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:50:53.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:50:53.697 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:50:53.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:50:53.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:53.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:50:54.067 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:50:54.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:54.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:54.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:54.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:54.545 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:50:54.561 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:50:55.023 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:50:55.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:55.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:55.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:55.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:55.501 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:50:55.978 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:50:56.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:56.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:56.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:56.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:56.456 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:50:56.934 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:50:57.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:57.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:57.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:57.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:57.412 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:50:57.889 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:50:58.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:50:58.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:50:58.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:50:58.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:50:58.367 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:50:58.845 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:50:59.322 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:50:59.800 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:51:00.278 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:51:00.756 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:51:01.234 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:51:01.712 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:51:02.183 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:51:02.660 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:51:03.138 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:51:03.616 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:51:04.093 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:51:04.295 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:51:04.572 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:51:05.049 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:51:05.527 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:51:06.005 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:51:06.482 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:51:06.960 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:51:07.437 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:51:07.915 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:51:08.393 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:51:08.870 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:51:09.348 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:51:09.826 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:51:10.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:10.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:10.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:10.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:10.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:10.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:10.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:10.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:10.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:10.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:10.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:10.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:10.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:10.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:10.164 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:51:10.164 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3645 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:10.164 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3645 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:10.164 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3645 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:10.164 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3645 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:10.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3645 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:10.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3645 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:15.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:15.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:15.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:15.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:15.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:15.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:15.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:15.168 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:15.169 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:15.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:15.169 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:51:15.172 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:51:15.172 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:51:15.173 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:15.173 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:15.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:15.174 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:51:15.174 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:15.174 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:51:15.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:15.175 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:15.175 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:51:15.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:15.177 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:51:15.177 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:51:15.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:15.177 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:15.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:15.177 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:51:15.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:15.178 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:51:15.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:51:15.181 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:51:15.181 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:51:15.181 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:15.186 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:51:15.670 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:51:15.700 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:51:15.701 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:51:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:15.702 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:51:15.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:15.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:15.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:15.727 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:51:15.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:15.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:15.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:15.731 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:15.731 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:15.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:15.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:15.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:15.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:15.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:16.147 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:51:16.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:16.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:16.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:16.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:16.625 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:51:16.641 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:51:17.103 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:51:17.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:17.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:17.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:17.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:17.581 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:51:18.058 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:51:18.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:18.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:18.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:18.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:18.536 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:51:19.014 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:51:19.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:19.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:19.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:19.491 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:51:19.969 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:51:20.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:20.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:20.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:20.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:20.447 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:51:20.925 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:51:21.404 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:51:21.882 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:51:22.358 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:51:22.836 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:51:23.314 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:51:23.792 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:51:24.269 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:51:24.747 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:51:25.225 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:51:25.703 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:51:25.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:25.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:25.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:25.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:25.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:25.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:25.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:25.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:25.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:25.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:25.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:25.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:25.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:25.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:25.793 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:25.793 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2265 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:30.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:30.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:30.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:30.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:30.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:30.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:30.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:30.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:30.819 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:30.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:30.819 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:51:30.822 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:51:30.822 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:51:30.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:30.823 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:30.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:30.824 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:51:30.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:30.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:51:30.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:30.825 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:30.825 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:51:30.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:30.827 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:30.827 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:51:30.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:30.829 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:51:30.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:51:30.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:51:30.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:51:30.830 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:51:30.830 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:51:30.830 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:30.835 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:51:31.317 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:51:31.352 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:51:31.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:31.355 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:51:31.357 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:51:31.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:31.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:31.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:31.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:31.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:31.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:31.380 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:31.380 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:31.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:31.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:31.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:31.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:31.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:31.794 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:51:31.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:31.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:31.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:31.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:31.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:31.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:31.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:31.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:31.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:31.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:31.820 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:31.820 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:31.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:31.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:31.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:31.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:31.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:31.846 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:31.846 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:31.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:31.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.271 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:51:32.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:32.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:32.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:32.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:32.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:32.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:32.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:32.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:32.548 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:32.548 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:32.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:32.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:32.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:32.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:32.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:32.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:32.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:32.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:32.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:32.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:32.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:32.732 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:32.732 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:32.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:32.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:32.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:32.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:32.745 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:51:32.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:32.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:32.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:32.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:33.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:33.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:33.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:33.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:33.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:33.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:33.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:33.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:33.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:33.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:33.151 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:33.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:33.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:33.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:33.151 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:33.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:38.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:38.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:38.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:38.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:38.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:38.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:38.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:38.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:38.164 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:38.165 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:38.165 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:51:38.170 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:51:38.170 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:51:38.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:38.171 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:38.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:38.172 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:51:38.173 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:38.173 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:51:38.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:38.174 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:51:38.175 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:51:38.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:38.175 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:38.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:38.175 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:51:38.176 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:38.176 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:51:38.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:38.178 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:51:38.178 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:51:38.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:38.179 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:38.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:38.179 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:51:38.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:38.179 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:51:38.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:38.183 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:51:38.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:51:38.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:51:38.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:51:38.183 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:51:38.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.184 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:51:38.184 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:51:38.184 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:51:38.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:38.189 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:51:38.669 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:51:38.715 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:51:38.717 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:51:38.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:38.719 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:51:38.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:38.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:38.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:38.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:38.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:38.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:38.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:38.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:38.760 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:51:38.764 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 01:51:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:38.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:38.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:38.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:38.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:39.142 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:51:39.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:39.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:39.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:39.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:39.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:39.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:39.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:39.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:39.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:39.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:39.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:39.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:39.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:39.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:39.165 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:51:39.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:39.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:39.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:39.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:39.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:39.165 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:44.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:44.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:44.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:44.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:44.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:44.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:44.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:44.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:44.174 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:44.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:51:44.175 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:51:44.179 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:51:44.179 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:51:44.179 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:44.180 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:44.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:44.180 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:51:44.181 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:51:44.181 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:51:44.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:44.181 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:51:44.181 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:51:44.182 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:44.182 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:44.182 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:44.182 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:51:44.182 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:51:44.182 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:51:44.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:44.184 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:51:44.184 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:51:44.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:51:44.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:51:44.187 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:51:44.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:51:44.192 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:51:44.675 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:51:44.710 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:51:44.713 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:51:44.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:44.715 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:51:44.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:44.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:44.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:44.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:44.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:44.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:44.741 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:44.741 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:44.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:44.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:44.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:44.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:44.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:44.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:45.153 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:51:45.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:45.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:45.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:45.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:45.631 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:51:46.108 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:51:46.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:46.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:46.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:46.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:46.586 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:51:47.064 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:51:47.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:47.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:47.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:47.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:47.542 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:51:47.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:47.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:47.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:47.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:47.904 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=794 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:47.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:47.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:47.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:47.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:47.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:47.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:47.925 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:47.925 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:47.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:47.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:47.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:47.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:47.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:48.020 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:51:48.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:48.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:48.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:48.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:48.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:48.498 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:51:48.976 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:51:49.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:49.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:49.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:49.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:49.454 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:51:49.932 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:51:50.409 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:51:50.888 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:51:51.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:51.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:51.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:51.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:51.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:51.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:51.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:51.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:51.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:51.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:51.167 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:51.167 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:51.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:51.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:51.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:51.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:51.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:51.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:51.365 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:51:51.843 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:51:52.321 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:51:52.798 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:51:53.276 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:51:53.753 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:51:54.231 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:51:54.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:54.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:54.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:54.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:54.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:54.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:54.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:51:54.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:54.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:54.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:54.381 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:51:54.381 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:51:54.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:54.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:51:54.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:51:54.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:54.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:54.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:54.708 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:51:55.186 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:51:55.663 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:51:56.141 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:51:56.618 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:51:57.096 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:51:57.574 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:51:57.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:51:57.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:51:57.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:51:57.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:51:57.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:51:57.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:51:57.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:51:57.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:51:57.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:51:57.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:51:57.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:51:57.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:51:57.647 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:51:57.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:51:57.648 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:51:57.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2874 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:02.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:52:02.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:52:02.650 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:02.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:02.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:02.650 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:02.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:02.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:52:02.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:02.662 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:52:02.662 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:52:02.667 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:52:02.668 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:52:02.668 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:52:02.668 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:02.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:02.669 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:52:02.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:52:02.670 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:52:02.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:02.672 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:52:02.672 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:52:02.672 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:52:02.672 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:02.673 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:02.673 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:52:02.673 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:52:02.673 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:52:02.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:02.675 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:52:02.675 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:52:02.676 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:52:02.676 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:02.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:02.676 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:52:02.676 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:52:02.676 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:52:02.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:52:02.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:52:02.680 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:52:02.680 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:52:02.680 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:02.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:02.685 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:52:03.168 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:52:03.213 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:52:03.215 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:52:03.217 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:52:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:52:03.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:52:03.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:52:03.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:52:03.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:03.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:52:03.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:52:03.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:52:03.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:52:03.642 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:52:03.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:03.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:03.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:03.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:04.120 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:52:04.598 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:52:04.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:04.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:04.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:04.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:05.076 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:52:05.554 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:52:05.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:05.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:05.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:05.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:06.032 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:52:06.509 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:52:06.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:06.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:06.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:06.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:06.986 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:52:07.463 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:52:07.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:07.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:07.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:07.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:07.942 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:52:08.419 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:52:08.897 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:52:09.374 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:52:09.852 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:52:10.329 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:52:10.806 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:52:11.284 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:52:11.762 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:52:12.240 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:52:12.717 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:52:13.195 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:52:13.673 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:52:14.150 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:52:14.627 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:52:15.105 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:52:15.583 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:52:16.061 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:52:16.538 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:52:17.016 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:52:17.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:52:17.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:52:17.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:17.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:17.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:17.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:17.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:17.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:17.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:17.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:17.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:52:17.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:52:17.315 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:52:17.315 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:17.315 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:17.315 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:17.315 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:17.315 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:17.315 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:22.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:52:22.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:52:22.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:22.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:22.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:22.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:22.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:22.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:52:22.326 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:22.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:52:22.326 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:52:22.327 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:52:22.327 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:52:22.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:52:22.327 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:22.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:22.328 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:52:22.328 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:52:22.328 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:52:22.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:22.329 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:52:22.329 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:52:22.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:52:22.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:22.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:22.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:52:22.330 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:52:22.330 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:52:22.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:22.331 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:52:22.331 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:52:22.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:52:22.331 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:22.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:22.331 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:52:22.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:52:22.331 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:52:22.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.334 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:52:22.334 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:52:22.334 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:52:22.334 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:22.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:22.339 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:52:22.822 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:52:22.862 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:52:22.864 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:52:22.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:52:22.866 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:52:22.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:52:22.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:52:22.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:52:22.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:22.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:52:22.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:52:22.888 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:52:22.888 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:52:22.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:52:22.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:52:22.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:52:22.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:22.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:23.300 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:52:23.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:23.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:23.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:23.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:23.777 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:52:24.255 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:52:24.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:24.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:24.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:24.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:24.733 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:52:24.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:24.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:52:24.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:52:24.929 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=554 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:24.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:52:24.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:24.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:52:24.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:52:24.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:52:24.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:52:25.211 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:52:25.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:25.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:25.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:25.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:25.689 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:52:26.167 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:52:26.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:26.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:26.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:26.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:26.644 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:52:27.121 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:52:27.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:27.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:27.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:27.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:27.599 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:52:28.076 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:52:28.554 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:52:29.032 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:52:29.510 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:52:29.987 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:52:30.465 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:52:30.942 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:52:31.420 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:52:31.898 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:52:32.375 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:52:32.853 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:52:33.331 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:52:33.808 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:52:34.286 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:52:34.764 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:52:35.242 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:52:35.719 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:52:36.198 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:52:36.675 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:52:37.153 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:52:37.630 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:52:38.108 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:52:38.585 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:52:39.063 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:52:39.540 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:52:39.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:52:39.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:52:39.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:52:39.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:39.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:39.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:39.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:39.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:39.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:39.844 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:52:39.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:52:39.844 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:52:39.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:39.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:39.844 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3739 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:52:44.845 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:52:44.845 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:52:44.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:44.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:44.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:44.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:44.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:52:44.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:52:44.869 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:44.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:52:44.869 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:52:44.873 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:52:44.873 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:52:44.873 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:52:44.874 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:44.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:52:44.874 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:52:44.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:52:44.875 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:52:44.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:44.875 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:52:44.875 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:52:44.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:52:44.876 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:44.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:52:44.876 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:52:44.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:52:44.876 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:52:44.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:52:44.878 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:52:44.878 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:52:44.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:44.880 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:52:44.881 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:52:44.881 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:52:44.881 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:52:44.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:52:44.886 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:52:45.368 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:52:45.406 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:52:45.407 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:52:45.409 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:52:45.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:52:45.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:52:45.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:52:45.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:52:45.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:52:45.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:52:45.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:52:45.412 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:52:45.412 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:52:45.845 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:52:45.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:45.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:45.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:45.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:46.323 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:52:46.800 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:52:46.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:46.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:46.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:46.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:47.278 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:52:47.755 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:52:47.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:47.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:47.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:47.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:48.233 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:52:48.710 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:52:48.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:48.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:48.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:48.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:49.188 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:52:49.666 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:52:49.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:52:49.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:52:49.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:52:49.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:52:50.143 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:52:50.621 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:52:51.099 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:52:51.576 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:52:52.054 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:52:52.532 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:52:53.009 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:52:53.487 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:52:53.964 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:52:54.443 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:52:54.920 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:52:55.398 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:52:55.876 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:52:56.354 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:52:56.832 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:52:57.310 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:52:57.787 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:52:58.265 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:52:58.743 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:52:59.221 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:52:59.698 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:53:00.176 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:53:00.654 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:53:01.132 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:53:01.609 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:53:02.087 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:53:02.565 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:53:03.043 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:53:03.520 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:53:03.997 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:53:04.475 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:53:04.953 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:53:05.431 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:53:05.908 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:53:06.385 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:53:06.863 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:53:06.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:53:06.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:53:06.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:06.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:06.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:06.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:06.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:53:06.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:53:06.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:53:06.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:53:06.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:53:06.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:53:06.907 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:06.908 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4703 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:11.906 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:53:11.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:53:11.908 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:53:11.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:53:11.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:53:11.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:53:11.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:53:11.917 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:53:11.918 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:11.918 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:53:11.918 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:53:11.920 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:53:11.920 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:53:11.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:53:11.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:11.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:53:11.921 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:53:11.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:53:11.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:53:11.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:53:11.922 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:53:11.922 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:53:11.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:53:11.924 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:53:11.924 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:53:11.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.926 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:53:11.926 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:53:11.926 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:53:11.927 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:11.931 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:53:12.414 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:53:12.448 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:53:12.450 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:53:12.452 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:53:12.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:53:12.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:53:12.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:53:12.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:53:12.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:53:12.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:53:12.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:53:12.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:53:12.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:53:12.892 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:53:12.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:12.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:12.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:12.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:13.369 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:53:13.847 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:53:13.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:13.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:13.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:13.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:14.324 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:53:14.802 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:53:14.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:14.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:14.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:14.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:15.280 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:53:15.757 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:53:15.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:15.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:15.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:15.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:16.235 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:53:16.712 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:53:16.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:16.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:16.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:16.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:17.187 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:53:17.665 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:53:18.142 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:53:18.620 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:53:19.098 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:53:19.576 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:53:20.053 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:53:20.531 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:53:21.009 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:53:21.486 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:53:21.964 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:53:22.441 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:53:22.919 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:53:23.396 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:53:23.873 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:53:24.350 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:53:24.828 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:53:25.306 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:53:25.783 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:53:26.257 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:53:26.733 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:53:27.211 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:53:27.689 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:53:28.165 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:53:28.643 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:53:29.121 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:53:29.598 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:53:30.076 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:53:30.554 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:53:31.032 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:53:31.509 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:53:31.987 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:53:32.464 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:53:32.942 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:53:33.420 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:53:33.896 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:53:33.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:53:33.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:53:33.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:53:33.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:53:33.947 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:53:33.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:33.948 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4705 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:53:38.950 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:53:38.950 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:53:38.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:53:38.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:53:38.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:53:38.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:53:38.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:53:38.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:53:38.965 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:38.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:53:38.965 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:53:38.968 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:53:38.968 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:53:38.969 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:53:38.969 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:38.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:53:38.970 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:53:38.970 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:53:38.970 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:53:38.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:38.971 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:53:38.971 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:53:38.971 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:53:38.971 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:38.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:53:38.972 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:53:38.972 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:53:38.972 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:53:38.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:38.973 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:53:38.973 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:53:38.974 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:53:38.974 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:53:38.974 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:53:38.974 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:53:38.974 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:53:38.974 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:53:38.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.977 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:53:38.977 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:53:38.977 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:53:38.978 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:53:38.982 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:53:39.466 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:53:39.506 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:53:39.508 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:53:39.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:53:39.510 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:53:39.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:53:39.513 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:53:39.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:53:39.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:53:39.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:53:39.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:53:39.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:53:39.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:53:39.944 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:53:39.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:39.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:39.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:39.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:40.421 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:53:40.898 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:53:40.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:40.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:40.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:40.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:41.375 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:53:41.850 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:53:41.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:41.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:41.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:41.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:42.327 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:53:42.805 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:53:42.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:42.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:42.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:42.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:43.283 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:53:43.760 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:53:43.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:53:43.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:53:43.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:53:43.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:53:44.238 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:53:44.716 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:53:45.194 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:53:45.671 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:53:46.149 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:53:46.627 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:53:47.104 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:53:47.582 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:53:48.060 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:53:48.537 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:53:49.015 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:53:49.493 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:53:49.970 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:53:50.448 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:53:50.925 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:53:51.402 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:53:51.880 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:53:52.357 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:53:52.835 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:53:53.312 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:53:53.787 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:53:54.265 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:53:54.743 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:53:55.221 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:53:55.699 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:53:56.176 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:53:56.654 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:53:57.132 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:53:57.610 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:53:58.087 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:53:58.564 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:53:59.042 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:53:59.520 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:53:59.998 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:54:00.475 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:54:00.953 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:54:01.430 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:54:01.907 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:54:02.385 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:54:02.863 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:54:03.340 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:54:03.818 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:54:04.295 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:54:04.773 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:54:05.250 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:54:05.727 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:54:06.205 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:54:06.683 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:54:07.160 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:54:07.637 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:54:08.115 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:54:08.592 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:54:09.068 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:54:09.546 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:54:10.024 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:54:10.501 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:54:10.979 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:54:11.457 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:54:11.935 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:54:12.412 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:54:12.890 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:54:13.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:54:13.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:54:13.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:13.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:13.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:13.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:13.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:13.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:13.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:13.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:13.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:13.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:13.008 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:54:13.008 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7269 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:13.008 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7269 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:13.009 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7269 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:13.009 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7269 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:13.009 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7269 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:13.009 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7269 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:18.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:18.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:18.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:18.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:18.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:18.012 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:18.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:18.019 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:54:18.020 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:18.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:54:18.020 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:54:18.023 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:54:18.023 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:54:18.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:54:18.024 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:18.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:18.024 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:54:18.025 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:54:18.025 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:54:18.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:18.026 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:54:18.026 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:54:18.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:54:18.027 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:18.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:18.027 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:54:18.027 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:54:18.027 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:54:18.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:18.029 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:54:18.029 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:54:18.029 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:54:18.029 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:18.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:18.030 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:54:18.030 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:54:18.030 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:54:18.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:18.033 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:54:18.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:54:18.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:54:18.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:54:18.033 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:54:18.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.034 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:54:18.034 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:54:18.034 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:54:18.035 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:18.039 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:54:18.523 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:54:18.554 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:54:18.555 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:54:18.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:54:18.557 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:54:18.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:54:18.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:54:18.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:54:18.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:54:18.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:54:18.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:54:18.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:54:18.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:54:19.000 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:54:19.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:19.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:19.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:19.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:19.478 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:54:19.955 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:54:20.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:20.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:20.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:20.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:20.433 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:54:20.911 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:54:21.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:21.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:21.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:21.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:21.388 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:54:21.866 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:54:22.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:22.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:22.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:22.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:22.343 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:54:22.821 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:54:23.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:23.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:23.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:23.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:23.299 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:54:23.776 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:54:24.254 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:54:24.732 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:54:25.210 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:54:25.688 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:54:26.166 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:54:26.644 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:54:27.121 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:54:27.599 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:54:28.077 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:54:28.555 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:54:29.033 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:54:29.510 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:54:29.988 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:54:30.465 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:54:30.943 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:54:31.420 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:54:31.898 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:54:32.375 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:54:32.853 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:54:33.331 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:54:33.809 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:54:34.286 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:54:34.765 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:54:35.242 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:54:35.720 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:54:36.198 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:54:36.676 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:54:37.153 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:54:37.631 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:54:38.108 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:54:38.585 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:54:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:54:39.540 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:54:40.017 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:54:40.494 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:54:40.971 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:54:41.449 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:54:41.927 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:54:42.404 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:54:42.881 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:54:43.359 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:54:43.836 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:54:44.314 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:54:44.791 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:54:45.269 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:54:45.746 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:54:46.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:54:46.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:54:46.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:46.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:46.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:46.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:46.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:46.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:46.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:46.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:46.079 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:54:46.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:46.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:46.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:51.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:51.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:51.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:51.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:51.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:51.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:51.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:54:51.097 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:51.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:54:51.098 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:54:51.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:54:51.104 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:54:51.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:54:51.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:51.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:51.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:54:51.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:54:51.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:54:51.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:51.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:54:51.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:54:51.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:54:51.107 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:51.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:51.107 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:54:51.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:54:51.108 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:54:51.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:51.109 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:54:51.110 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:54:51.110 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:54:51.110 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:51.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:51.110 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:54:51.110 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:54:51.110 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:54:51.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:54:51.114 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:54:51.114 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:54:51.114 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:51.119 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:54:51.602 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:54:51.648 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:54:51.650 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:54:51.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:54:51.652 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:54:51.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:51.666 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:51.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:51.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:51.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:51.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:51.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:51.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:51.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:51.669 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:54:51.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.669 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.670 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.670 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.670 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.670 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:51.670 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:56.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:56.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:56.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:56.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:56.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:56.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:56.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:56.682 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:54:56.682 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:56.683 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:54:56.683 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:54:56.687 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:54:56.687 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:54:56.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:54:56.688 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:56.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:56.689 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:54:56.689 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:54:56.689 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:54:56.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:56.690 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:54:56.690 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:54:56.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:54:56.690 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:56.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:56.691 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:54:56.691 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:54:56.691 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:54:56.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:54:56.693 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:54:56.693 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:54:56.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:56.695 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:54:56.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:54:56.696 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:54:56.696 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:54:56.696 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:54:56.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:54:56.701 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:54:57.185 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:54:57.221 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:54:57.224 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:54:57.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:54:57.226 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:54:57.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:54:57.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:54:57.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:54:57.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:54:57.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:54:57.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:54:57.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:54:57.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:54:57.243 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:54:57.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:54:57.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:54:57.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:02.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:02.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:02.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:02.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:02.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:02.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:02.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:02.254 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:02.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:02.254 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:55:02.258 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:55:02.258 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:55:02.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:02.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:02.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:02.259 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:55:02.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:02.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:55:02.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:02.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:55:02.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:55:02.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:02.262 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:02.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:02.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:55:02.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:02.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:55:02.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:02.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:55:02.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:55:02.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:02.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:02.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:02.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:55:02.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:02.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:55:02.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:55:02.270 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:55:02.270 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:55:02.270 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:02.275 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:55:02.758 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:55:02.797 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:55:02.799 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:55:02.802 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:55:02.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:55:02.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:02.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:02.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:02.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:02.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:02.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:02.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:02.819 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:55:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:02.819 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.819 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.820 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.820 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.820 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.820 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:02.820 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:07.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:07.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:07.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:07.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:07.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:07.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:07.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:07.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:07.832 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:07.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:07.832 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:55:07.833 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:55:07.833 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:55:07.833 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:07.833 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:07.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:07.834 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:55:07.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:07.834 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:55:07.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:07.835 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:07.835 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:55:07.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:07.837 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:07.837 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:55:07.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:55:07.840 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:55:07.840 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:55:07.840 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:07.845 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:55:08.329 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:55:08.362 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:55:08.363 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:55:08.363 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:55:08.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:55:08.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:08.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:08.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:55:08.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:55:08.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:55:08.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:55:08.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:55:08.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:55:08.806 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:55:08.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:08.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:08.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:08.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:09.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:55:09.762 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:55:09.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:09.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:09.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:09.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:10.239 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:55:10.716 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:55:10.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:10.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:10.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:10.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:11.194 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:55:11.671 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:55:11.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:11.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:11.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:11.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:12.149 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:55:12.627 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:55:12.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:12.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:12.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:12.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:13.104 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:55:13.582 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:55:14.059 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:55:14.537 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:55:15.015 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:55:15.492 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:55:15.970 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:55:16.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:16.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:16.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:16.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:16.380 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:55:16.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:21.385 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:21.385 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:21.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:21.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:21.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:21.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:21.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:21.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:21.391 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:21.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:21.391 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:55:21.392 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:55:21.392 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:55:21.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:21.393 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:21.393 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:55:21.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:21.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:21.393 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:55:21.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:21.395 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:21.395 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:55:21.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:21.397 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:21.397 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:55:21.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.399 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:55:21.399 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:55:21.400 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:55:21.400 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:21.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:21.404 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:55:21.888 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:55:21.921 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:55:21.923 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:55:21.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:55:21.925 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:55:21.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:21.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:21.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:55:21.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:55:21.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:55:21.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:55:21.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:55:21.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:55:22.362 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:55:22.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:22.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:22.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:22.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:22.832 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:55:23.308 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:55:23.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:23.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:23.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:23.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:23.785 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:55:24.263 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:55:24.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:24.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:24.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:24.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:24.741 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:55:25.219 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:55:25.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:25.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:25.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:25.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:25.697 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:55:26.175 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:55:26.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:26.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:26.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:26.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:26.652 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:55:27.130 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:55:27.608 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:55:28.085 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:55:28.563 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:55:29.041 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:55:29.518 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:55:29.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:29.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:29.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:29.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:29.945 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:29.945 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:29.945 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:55:29.945 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1828 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:29.945 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1828 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:29.945 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1828 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:29.946 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1828 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:29.946 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1828 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:29.946 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1828 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:34.948 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:34.948 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:34.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:34.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:34.951 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:34.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:34.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:34.960 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:34.960 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:34.960 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:34.960 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:55:34.964 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:55:34.964 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:55:34.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:34.964 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:34.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:34.964 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:55:34.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:34.964 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:55:34.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:34.967 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:55:34.967 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:55:34.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:34.967 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:34.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:34.968 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:55:34.968 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:34.968 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:55:34.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:34.970 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:55:34.970 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:55:34.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:34.970 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:34.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:34.971 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:55:34.971 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:34.971 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:55:34.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.974 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:55:34.975 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:55:34.975 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:55:34.975 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:55:34.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:34.980 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:55:35.463 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:55:35.512 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:55:35.514 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:55:35.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:55:35.516 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:55:35.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:35.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:35.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:55:35.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:55:35.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:55:35.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:55:35.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:55:35.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:55:35.940 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:55:35.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:35.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:35.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:35.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:36.418 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:55:36.895 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:55:36.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:36.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:36.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:36.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:37.373 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:55:37.851 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:55:37.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:37.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:37.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:37.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:38.329 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:55:38.806 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:55:38.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:38.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:38.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:38.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:39.283 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:55:39.761 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:55:39.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:39.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:39.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:39.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:40.239 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:55:40.716 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:55:41.194 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:55:41.672 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:55:42.150 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:55:42.628 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:55:43.105 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:55:43.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:43.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:43.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:43.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:43.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:43.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:43.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:43.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:43.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:43.565 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:55:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:48.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:48.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:48.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:48.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:48.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:48.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:48.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:48.582 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:48.582 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:48.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:55:48.583 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:55:48.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:55:48.586 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:55:48.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:48.586 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:48.587 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:48.587 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:55:48.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:55:48.587 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:55:48.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:48.588 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:55:48.588 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:55:48.589 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:48.589 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:48.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:48.589 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:55:48.589 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:55:48.589 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:55:48.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:48.591 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:55:48.591 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:55:48.591 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:48.591 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:55:48.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:48.591 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:55:48.591 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:55:48.591 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:55:48.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:55:48.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:55:48.595 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:55:48.595 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:55:48.595 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:55:48.600 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:55:49.084 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:55:49.128 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:55:49.130 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:55:49.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:55:49.132 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:55:49.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:49.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:49.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:55:49.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:55:49.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:55:49.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:55:49.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:55:49.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:55:49.561 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:55:49.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:49.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:49.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:49.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:50.039 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:55:50.517 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:55:50.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:50.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:50.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:50.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:50.994 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:55:51.472 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:55:51.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:51.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:51.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:51.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:51.950 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:55:52.428 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:55:52.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:52.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:52.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:52.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:52.905 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:55:53.383 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:55:53.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:53.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:53.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:53.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:53.860 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:55:54.338 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:55:54.813 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:55:55.291 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:55:55.769 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:55:56.247 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:55:56.724 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:55:57.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:55:57.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:55:57.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:55:57.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:55:57.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:55:57.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:55:57.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:55:57.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:55:57.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:55:57.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:55:57.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:55:57.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:55:57.191 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:55:57.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:55:57.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:02.194 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:02.194 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:02.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:02.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:02.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:02.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:02.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:02.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:02.205 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:02.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:02.206 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:56:02.211 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:56:02.211 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:56:02.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:02.212 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:02.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:02.213 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:56:02.213 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:02.214 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:56:02.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:02.215 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:56:02.215 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:56:02.215 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:02.215 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:02.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:02.216 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:56:02.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:02.216 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:56:02.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:02.218 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:02.218 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:56:02.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:56:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:56:02.222 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:56:02.222 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:56:02.222 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:02.227 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:56:02.711 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:56:02.755 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:56:02.757 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:56:02.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:56:02.759 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:56:02.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:02.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:02.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:56:02.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:56:02.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:56:02.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:56:02.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:56:02.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:56:03.188 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:56:03.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:03.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:03.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:03.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:03.666 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:56:04.143 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:56:04.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:04.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:04.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:04.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:04.621 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:56:05.099 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:56:05.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:05.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:05.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:05.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:05.577 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:56:06.054 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:56:06.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:06.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:06.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:06.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:06.532 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:56:07.009 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:56:07.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:07.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:07.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:07.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:07.487 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:56:07.964 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:56:08.441 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:56:08.919 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:56:09.397 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:56:09.875 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:56:10.352 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:56:10.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:10.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:10.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:10.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:10.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:10.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:10.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:10.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:10.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:10.808 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:10.808 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:10.808 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:56:10.808 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:15.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:15.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:15.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:15.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:15.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:15.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:15.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:15.825 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:15.825 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:15.826 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:15.826 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:56:15.830 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:56:15.830 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:56:15.831 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:15.831 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:15.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:15.831 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:56:15.831 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:15.831 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:56:15.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:15.833 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:56:15.834 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:56:15.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:15.834 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:15.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:15.835 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:56:15.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:15.835 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:56:15.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:15.836 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:56:15.837 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:56:15.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:15.837 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:15.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:15.837 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:56:15.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:15.837 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:56:15.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:56:15.841 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:56:15.841 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:56:15.841 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:15.845 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:56:16.329 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:56:16.369 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:56:16.369 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:56:16.370 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:56:16.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:56:16.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:16.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:16.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:56:16.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:56:16.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:56:16.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:56:16.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:56:16.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:56:16.806 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:56:16.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:16.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:16.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:16.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:17.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:56:17.761 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:56:17.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:17.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:17.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:17.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:18.240 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:56:18.717 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:56:18.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:18.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:18.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:18.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:19.195 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:56:19.673 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:56:19.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:19.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:19.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:19.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:20.150 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:56:20.628 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:56:20.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:20.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:20.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:20.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:21.105 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:56:21.582 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:56:22.060 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:56:22.538 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:56:23.016 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:56:23.492 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:56:23.970 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:56:24.448 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:56:24.925 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:56:25.403 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:56:25.881 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:56:26.358 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:56:26.836 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:56:27.313 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:56:27.791 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:56:28.269 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:56:28.747 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:56:29.224 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:56:29.702 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:56:30.180 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:56:30.657 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:56:31.135 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:56:31.613 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:56:32.090 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:56:32.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:32.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:32.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:32.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:32.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:32.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:32.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:32.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:32.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:32.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:32.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:32.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:32.443 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:56:32.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3546 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:32.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3546 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:32.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3546 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:32.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3546 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:32.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3546 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:32.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3546 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:37.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:37.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:37.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:37.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:37.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:37.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:37.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:37.458 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:37.458 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:37.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:37.459 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:56:37.463 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:56:37.463 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:56:37.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:37.464 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:37.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:37.464 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:56:37.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:37.464 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:56:37.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:37.467 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:56:37.467 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:56:37.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:37.467 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:37.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:37.467 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:56:37.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:37.467 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:56:37.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:37.470 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:37.470 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:56:37.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:56:37.474 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:56:37.474 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:56:37.474 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:37.479 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:56:37.963 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:56:38.002 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:56:38.004 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:56:38.007 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:56:38.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:56:38.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:38.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:38.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:56:38.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:56:38.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:56:38.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:56:38.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:56:38.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:56:38.440 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:56:38.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:38.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:38.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:38.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:38.918 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:56:39.396 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:56:39.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:39.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:39.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:39.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:39.873 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:56:40.351 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:56:40.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:40.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:40.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:40.829 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:56:41.307 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:56:41.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:41.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:41.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:41.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:41.784 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:56:42.262 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:56:42.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:42.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:42.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:42.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:42.739 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:56:43.216 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:56:43.694 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:56:44.172 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:56:44.650 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:56:45.128 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:56:45.606 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:56:46.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:46.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:46.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:46.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:46.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:46.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:46.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:46.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:46.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:46.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:46.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:46.079 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:56:46.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:46.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:56:51.078 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:56:51.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:56:51.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:51.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:51.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:51.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:51.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:56:51.092 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:51.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:51.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:56:51.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:56:51.098 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:56:51.099 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:56:51.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:51.099 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:51.100 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:56:51.100 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:56:51.100 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:56:51.101 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:56:51.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:51.102 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:56:51.102 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:56:51.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:51.102 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:51.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:56:51.102 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:56:51.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:56:51.102 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:56:51.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:51.105 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:56:51.105 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:56:51.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:56:51.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:56:51.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:56:51.109 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:56:51.109 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:56:51.114 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:56:51.598 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:56:51.633 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:56:51.636 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:56:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:56:51.638 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:56:51.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:56:51.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:56:51.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:56:51.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:56:51.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:56:51.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:56:51.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:56:51.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:56:52.076 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:56:52.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:52.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:52.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:52.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:52.554 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:56:53.031 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:56:53.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:53.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:53.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:53.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:53.508 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:56:53.986 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:56:54.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:54.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:54.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:54.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:54.463 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:56:54.940 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:56:55.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:55.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:55.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:55.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:55.418 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:56:55.896 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:56:56.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:56:56.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:56:56.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:56:56.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:56:56.373 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:56:56.851 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:56:57.328 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:56:57.806 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:56:58.284 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:56:58.761 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:56:59.239 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:56:59.717 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:57:00.192 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:57:00.670 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:57:01.147 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:57:01.625 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:57:02.099 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:57:02.577 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:57:03.050 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:57:03.528 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:57:04.005 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:57:04.483 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:57:04.960 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:57:05.438 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:57:05.912 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:57:06.390 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:57:06.868 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:57:07.346 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:57:07.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:07.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:07.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:07.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:07.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:07.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:07.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:07.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:07.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:07.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:07.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:07.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:07.717 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:07.717 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3550 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:07.717 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3550 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:07.717 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3550 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:07.717 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3550 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:07.717 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3550 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:07.717 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3550 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:12.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:12.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:12.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:12.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:12.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:12.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:12.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:12.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:12.734 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:12.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:12.735 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:12.738 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:12.738 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:12.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:12.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:12.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:12.739 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:12.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:12.740 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:12.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:12.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:12.741 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:12.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:12.743 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:12.743 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:12.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:12.743 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:12.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:12.743 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:12.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:12.744 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:12.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.746 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:12.747 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:12.747 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:12.747 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:12.752 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:13.234 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:13.274 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:13.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:13.277 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:13.280 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:13.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:13.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:13.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:13.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:13.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:13.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:13.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:13.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:13.321 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:13.321 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:13.321 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:13.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:13.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:13.321 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:13.321 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:13.321 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:13.321 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:13.321 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:13.321 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:13.321 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:18.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:18.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:18.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:18.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:18.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:18.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:18.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:18.337 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:18.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:18.338 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:18.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:18.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:18.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:18.343 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:18.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:18.344 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:18.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:18.344 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:18.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:18.345 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:18.345 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:18.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:18.346 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:18.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:18.346 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:18.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:18.346 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:18.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:18.348 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:18.348 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:18.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:18.348 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:18.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:18.348 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:18.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:18.349 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:18.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:18.351 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:18.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:18.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:18.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:18.351 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:18.352 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:18.352 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:18.352 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:18.357 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:18.841 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:18.877 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:18.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:18.879 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:18.883 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:18.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:18.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:18.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:18.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:18.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:18.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:18.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:18.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:18.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:18.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:18.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:18.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:18.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:18.942 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:18.942 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:23.945 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:23.945 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:23.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:23.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:23.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:23.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:23.957 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:23.958 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:23.958 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:23.959 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:23.959 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:23.963 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:23.963 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:23.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:23.964 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:23.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:23.965 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:23.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:23.965 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:23.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:23.966 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:23.966 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:23.966 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:23.966 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:23.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:23.967 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:23.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:23.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:23.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:23.969 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:23.969 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:23.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:23.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:23.973 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:23.973 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:23.973 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:23.978 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:24.461 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:24.501 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:24.503 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:24.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:24.506 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:24.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:24.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:24.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:24.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:24.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:24.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:24.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:24.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:24.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:24.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:24.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:24.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:24.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:24.548 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:24.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:24.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:24.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:24.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:24.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:24.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:29.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:29.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:29.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:29.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:29.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:29.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:29.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:29.556 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:29.556 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:29.556 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:29.556 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:29.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:29.557 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:29.557 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:29.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:29.558 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:29.558 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:29.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:29.559 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:29.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:29.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:29.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:29.560 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:29.560 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:29.560 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:29.565 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:30.049 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:30.086 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:30.088 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:30.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:30.089 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:30.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:30.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:30.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:30.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:30.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:30.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:30.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:30.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:30.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:30.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:30.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:30.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:30.135 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:30.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:30.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:57:35.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:35.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:35.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:35.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:35.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:35.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:35.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:35.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:35.148 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:35.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:35.148 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:35.149 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:35.149 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:35.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:35.150 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:35.150 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:35.150 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:35.150 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:35.151 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:35.151 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:35.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:35.152 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:35.152 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:35.152 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:35.157 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:35.639 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:35.681 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:35.684 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:35.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:35.686 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:35.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:35.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:35.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:35.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:35.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:35.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:35.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:35.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:35.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:35.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:35.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:35.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:35.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:35.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:35.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:35.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:35.735 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:40.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:40.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:40.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:40.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:40.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:40.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:40.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:40.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:40.752 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:40.753 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:40.753 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:40.757 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:40.757 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:40.758 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:40.758 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:40.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:40.758 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:40.758 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:40.758 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:40.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:40.761 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:40.761 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:40.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:40.761 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:40.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:40.761 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:40.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:40.762 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:40.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:40.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:40.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:40.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:40.768 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:40.768 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:40.768 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:40.773 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:41.256 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:41.293 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:41.294 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:41.295 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:41.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:41.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:41.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:41.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:41.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:41.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:41.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:41.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:41.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:41.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:41.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:41.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:41.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:41.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:41.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:41.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:41.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:41.343 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:57:46.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:57:46.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:57:46.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:46.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:46.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:46.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:46.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:57:46.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:46.356 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:46.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:57:46.357 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:57:46.358 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:57:46.359 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:57:46.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:46.359 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:46.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:57:46.360 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:57:46.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:57:46.360 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:57:46.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:46.361 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:57:46.361 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:57:46.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:46.363 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:57:46.363 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:57:46.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:46.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:57:46.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:57:46.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:57:46.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:57:46.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:57:46.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:57:46.366 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:57:46.366 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:57:46.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:57:46.855 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:57:46.898 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:57:46.900 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:57:46.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:57:46.902 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:57:46.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:57:46.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:57:46.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:57:46.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:57:46.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:57:46.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:57:46.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:57:46.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:57:47.332 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:57:47.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:47.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:47.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:47.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:47.810 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:57:48.287 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:57:48.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:48.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:48.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:48.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:48.765 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:57:49.243 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:57:49.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:49.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:49.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:49.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:49.721 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:57:50.198 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:57:50.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:50.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:50.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:50.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:50.676 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:57:51.153 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:57:51.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:57:51.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:57:51.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:57:51.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:57:51.631 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:57:52.108 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:57:52.586 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:57:53.064 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:57:53.541 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:57:54.018 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:57:54.495 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:57:54.974 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 01:57:55.451 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 01:57:55.929 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 01:57:56.406 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 01:57:56.884 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 01:57:57.362 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 01:57:57.839 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 01:57:58.317 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 01:57:58.795 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 01:57:59.273 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 01:57:59.751 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 01:58:00.229 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 01:58:00.706 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 01:58:01.184 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 01:58:01.662 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 01:58:02.140 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 01:58:02.618 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 01:58:03.096 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 01:58:03.574 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 01:58:04.052 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 01:58:04.529 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 01:58:05.007 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 01:58:05.485 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 01:58:05.963 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 01:58:06.440 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 01:58:06.918 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 01:58:07.395 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 01:58:07.873 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 01:58:08.350 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 01:58:08.827 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 01:58:09.304 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 01:58:09.781 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 01:58:10.259 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 01:58:10.737 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 01:58:11.215 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 01:58:11.693 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 01:58:12.170 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 01:58:12.648 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 01:58:13.126 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 01:58:13.603 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 01:58:14.081 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 01:58:14.559 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 01:58:15.037 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 01:58:15.514 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 01:58:15.992 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 01:58:16.470 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 01:58:16.948 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 01:58:17.425 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 01:58:17.903 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 01:58:18.381 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 01:58:18.859 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 01:58:19.337 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 01:58:19.814 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 01:58:20.291 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 01:58:20.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:58:20.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:58:20.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:20.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:20.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:20.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:20.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:20.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:20.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:20.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:20.400 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:20.400 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:58:20.400 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7267 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:20.400 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7267 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:20.400 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7267 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:20.400 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7267 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:20.400 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7267 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:20.400 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7267 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:25.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:25.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:25.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:25.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:25.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:25.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:25.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:25.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:25.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:25.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:25.413 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:58:25.416 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:58:25.416 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:58:25.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:25.417 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:25.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:25.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:58:25.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:25.417 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:58:25.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:25.420 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:58:25.420 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:58:25.420 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:25.420 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:25.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:25.421 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:58:25.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:25.421 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:58:25.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:25.423 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:58:25.423 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:58:25.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:25.424 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:25.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:25.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:58:25.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:25.424 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:58:25.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:58:25.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:58:25.428 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:58:25.428 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:58:25.428 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:25.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:25.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:25.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:25.433 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:58:25.916 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:58:25.959 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:58:25.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:58:25.963 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:58:25.966 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:58:26.394 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:58:26.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:26.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:26.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:26.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:26.872 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:58:27.353 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:58:27.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:27.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:27.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:27.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:27.832 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:58:28.311 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:58:28.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:28.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:28.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:28.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:28.790 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:58:28.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:58:28.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:28.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:28.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:28.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:28.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:28.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:28.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:28.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:28.997 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:28.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:28.997 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:28.997 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=760 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:34.000 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:34.001 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:34.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:34.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:34.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:34.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:34.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:34.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:34.012 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:34.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:34.012 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:58:34.014 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:58:34.014 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:58:34.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:34.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:34.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:34.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:58:34.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:34.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:58:34.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:34.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:58:34.017 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:58:34.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:34.017 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:34.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:34.017 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:58:34.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:34.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:58:34.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:34.019 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:58:34.020 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:58:34.020 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:34.020 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:34.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:34.020 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:58:34.020 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:34.020 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:58:34.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.023 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:58:34.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:58:34.024 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:58:34.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:34.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:58:34.511 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:58:34.557 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:58:34.559 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:58:34.559 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:58:34.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:58:34.990 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:58:35.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:35.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:35.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:35.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:35.468 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:58:35.948 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:58:36.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:36.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:36.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:36.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:36.427 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:58:36.907 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:58:37.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:37.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:37.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:37.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:37.389 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:58:37.870 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:58:38.031 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:38.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:38.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:38.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:38.351 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:58:38.828 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:58:39.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:39.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:39.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:39.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:39.306 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:58:39.787 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:58:40.264 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:58:40.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:40.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:40.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:40.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:40.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:40.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:40.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:40.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:40.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:40.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:40.574 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:40.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:58:45.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:45.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:45.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:45.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:45.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:45.580 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:45.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:45.588 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:45.588 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:45.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:45.589 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:58:45.592 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:58:45.592 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:58:45.593 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:45.593 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:45.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:45.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:58:45.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:45.595 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:58:45.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:45.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:58:45.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:58:45.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:45.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:45.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:45.597 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:58:45.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:45.597 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:58:45.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:45.599 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:58:45.599 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:58:45.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:45.599 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:45.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:45.599 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:58:45.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:45.600 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:58:45.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.603 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:58:45.604 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:58:45.604 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:58:45.604 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:45.609 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:58:46.093 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:58:46.136 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:58:46.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:58:46.138 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:58:46.140 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:58:46.562 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:58:46.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:46.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:46.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:46.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:47.031 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:58:47.507 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:58:47.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:47.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:47.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:47.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:47.985 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:58:48.466 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:58:48.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:48.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:48.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:48.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:48.945 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:58:49.423 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:58:49.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:49.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:49.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:49.619 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:49.895 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:58:50.370 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:58:50.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:50.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:50.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:50.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:50.849 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:58:51.330 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:58:51.811 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:58:52.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:52.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:52.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:52.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:52.155 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:58:57.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:58:57.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:58:57.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:57.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:57.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:57.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:57.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:58:57.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:57.170 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:57.171 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:58:57.171 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:58:57.175 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:58:57.175 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:58:57.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:57.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:57.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:58:57.177 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:58:57.177 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:58:57.177 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:58:57.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:57.178 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:58:57.179 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:58:57.179 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:57.179 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:57.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:58:57.179 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:58:57.179 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:58:57.179 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:58:57.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:57.181 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:58:57.181 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:58:57.181 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:57.181 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:58:57.181 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:58:57.181 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:58:57.181 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:58:57.181 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:58:57.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.184 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:58:57.184 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:58:57.184 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:58:57.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:58:57.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:58:57.189 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:58:57.673 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:58:57.709 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:58:57.710 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:58:57.711 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:58:57.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:58:58.150 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:58:58.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:58.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:58.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:58.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:58.623 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:58:59.092 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:58:59.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:58:59.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:58:59.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:58:59.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:58:59.572 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:59:00.049 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:59:00.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:00.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:00.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:00.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:00.528 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:59:01.005 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:59:01.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:01.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:01.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:01.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:01.486 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:59:01.959 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:59:02.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:02.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:02.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:02.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:02.430 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:59:02.908 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:59:03.386 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:59:03.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:03.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:03.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:03.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:03.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:03.722 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:03.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:03.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:03.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:03.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:03.722 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:08.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:08.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:08.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:08.726 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:08.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:08.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:08.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:08.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:08.738 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:08.738 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:08.738 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:08.743 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:08.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:08.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:08.743 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:08.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:08.744 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:08.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:08.744 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:08.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:08.746 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:08.746 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:08.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:08.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:08.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:08.747 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:08.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:08.747 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:08.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:08.749 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:08.749 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:08.749 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:08.749 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:08.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:08.750 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:08.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:08.750 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:08.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.753 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:08.753 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:08.754 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:08.754 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:08.759 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:09.242 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:09.285 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:09.286 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:09.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:09.287 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:09.719 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:59:09.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:09.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:09.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:09.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:10.200 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:59:10.681 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:59:10.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:10.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:10.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:10.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:11.162 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:59:11.644 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:59:11.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:11.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:11.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:11.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:12.118 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:59:12.597 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:59:12.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:12.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:12.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:12.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:13.076 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:59:13.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:13.554 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 01:59:13.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:13.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:13.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:13.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:14.033 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 01:59:14.513 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 01:59:14.994 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 01:59:15.472 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 01:59:15.953 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 01:59:16.434 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 01:59:16.915 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 01:59:17.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:17.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:17.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:17.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:17.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:17.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:17.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:17.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:17.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:17.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:17.308 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:17.308 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1821 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:22.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:22.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:22.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:22.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:22.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:22.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:22.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:22.326 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:22.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:22.326 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:22.329 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:22.329 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:22.329 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:22.329 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:22.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:22.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:22.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:22.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:22.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:22.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:22.332 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:22.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:22.334 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:22.334 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:22.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:22.334 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:22.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:22.335 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:22.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:22.335 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:22.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:22.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:22.338 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:22.338 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:22.338 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:22.343 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:22.826 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:22.862 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:22.863 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:22.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:22.864 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:23.307 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:59:23.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:23.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:23.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:23.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:23.785 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:59:24.263 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:59:24.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:24.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:24.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:24.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:24.744 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:59:25.225 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:59:25.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:25.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:25.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:25.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:25.706 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:59:26.188 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 01:59:26.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:26.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:26.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:26.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:26.669 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 01:59:26.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:26.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:26.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:26.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:26.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:26.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:26.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:26.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:26.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:26.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:26.876 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:26.876 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=964 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:31.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:31.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:31.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:31.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:31.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:31.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:31.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:31.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:31.895 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:31.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:31.896 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:31.899 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:31.900 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:31.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:31.900 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:31.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:31.901 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:31.902 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:31.902 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:31.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:31.903 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:31.903 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:31.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:31.904 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:31.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:31.904 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:31.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:31.904 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:31.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:31.906 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:31.906 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:31.906 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:31.906 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:31.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:31.907 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:31.907 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:31.907 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:31.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:31.909 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:31.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:31.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:31.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:31.909 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:31.910 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:31.910 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:31.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:31.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:31.915 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:32.399 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:32.433 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:32.434 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:32.436 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:32.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:32.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:32.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:32.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:32.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:32.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:32.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:32.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:32.451 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:32.451 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:32.451 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:32.451 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:37.450 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:37.450 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:37.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:37.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:37.453 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:37.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:37.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:37.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:37.459 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:37.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:37.459 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:37.462 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:37.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:37.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:37.463 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:37.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:37.463 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:37.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:37.463 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:37.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:37.467 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:37.468 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:37.468 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:37.468 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:37.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:37.468 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:37.468 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:37.468 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:37.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:37.470 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:37.470 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:37.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:37.470 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:37.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:37.470 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:37.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:37.470 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:37.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.473 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:37.473 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:37.473 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:37.474 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:37.478 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:37.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:38.007 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:38.009 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:38.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:38.011 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:38.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:38.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:38.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:38.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:38.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:38.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:38.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:38.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:38.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:38.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:38.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:38.030 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:38.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:38.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:43.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:43.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:43.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:43.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:43.033 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:43.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:43.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:43.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:43.045 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:43.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:43.045 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:43.048 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:43.048 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:43.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:43.049 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:43.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:43.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:43.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:43.050 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:43.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:43.051 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:43.051 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:43.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:43.053 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:43.053 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:43.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:43.056 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:43.056 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:43.056 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:43.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:43.061 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:43.545 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:43.585 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:43.588 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:43.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:43.589 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:43.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:43.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:43.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:43.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:43.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:43.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:43.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:43.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:43.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:43.606 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:43.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:43.607 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:43.607 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:43.607 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:43.607 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:43.607 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:43.607 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:48.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:48.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:48.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:48.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:48.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:48.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:48.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:48.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:48.619 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:48.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:48.620 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:48.623 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:48.623 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:48.624 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:48.624 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:48.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:48.625 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:48.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:48.625 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:48.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:48.626 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:48.626 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:48.626 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:48.626 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:48.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:48.626 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:48.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:48.627 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:48.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:48.628 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:48.629 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:48.629 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:48.629 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:48.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:48.629 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:48.629 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:48.629 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:48.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:48.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:48.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:48.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:48.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:48.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:48.632 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:48.632 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:48.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:48.637 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:49.120 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:49.157 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:49.158 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:49.159 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:49.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:49.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:59:49.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:59:49.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:59:49.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:59:49.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:59:49.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:59:49.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:59:49.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:59:49.592 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:59:49.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:49.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:49.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:49.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:50.066 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:59:50.544 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:59:50.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:50.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:50.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:50.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:51.021 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 01:59:51.498 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 01:59:51.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:51.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:51.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:51.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:51.976 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 01:59:52.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:59:52.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:59:52.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:59:52.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:59:52.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:59:52.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:59:52.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:52.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:52.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:52.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:52.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:52.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:52.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:52.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:52.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:52.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:52.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:52.274 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 01:59:52.274 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=780 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:52.274 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=780 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:52.274 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=780 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:52.274 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=780 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:52.274 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=780 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:52.274 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=780 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 01:59:57.275 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 01:59:57.276 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 01:59:57.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:57.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:57.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:57.280 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:57.287 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 01:59:57.288 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:57.289 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:57.289 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 01:59:57.289 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 01:59:57.292 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 01:59:57.293 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 01:59:57.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:57.293 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:57.294 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 01:59:57.294 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 01:59:57.295 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 01:59:57.295 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 01:59:57.295 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:57.296 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 01:59:57.296 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 01:59:57.296 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:57.296 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:57.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 01:59:57.297 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 01:59:57.297 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 01:59:57.297 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 01:59:57.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:57.300 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 01:59:57.300 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 01:59:57.300 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:57.300 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 01:59:57.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 01:59:57.300 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 01:59:57.301 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 01:59:57.301 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 01:59:57.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:57.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 01:59:57.305 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 01:59:57.305 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 01:59:57.305 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 01:59:57.310 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 01:59:57.793 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 01:59:57.823 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 01:59:57.823 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 01:59:57.824 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 01:59:57.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 01:59:57.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 01:59:57.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 01:59:57.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 01:59:57.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 01:59:57.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 01:59:57.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 01:59:57.827 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 01:59:57.827 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 01:59:58.270 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 01:59:58.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:58.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:58.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:58.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:58.748 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 01:59:59.225 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 01:59:59.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 01:59:59.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 01:59:59.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 01:59:59.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 01:59:59.703 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:00:00.181 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:00:00.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:00.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:00.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:00.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:00.659 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:00:00.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:00.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:00.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:00.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:01.137 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:00:01.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:01.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:01.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:01.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:01.614 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:00:01.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:01.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:01.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:01.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:01.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:01.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:01.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:01.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:01.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:01.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:01.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:01.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:01.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:01.637 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:01.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:06.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:06.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:06.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:06.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:06.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:06.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:06.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:06.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:06.650 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:06.651 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:06.651 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:00:06.653 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:00:06.653 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:00:06.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:06.654 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:06.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:06.654 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:00:06.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:06.655 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:00:06.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:06.656 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:00:06.656 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:00:06.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:06.657 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:06.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:06.657 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:00:06.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:06.657 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:00:06.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:06.659 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:06.659 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:00:06.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.662 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:00:06.662 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:00:06.662 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:00:06.663 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:06.667 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:00:07.151 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:00:07.195 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:00:07.197 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:00:07.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:07.200 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:00:07.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:07.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:07.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:00:07.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:07.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:07.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:07.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:00:07.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:00:07.643 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:00:07.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:07.666 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:07.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:07.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:08.121 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:00:08.598 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:00:08.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:08.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:08.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:08.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:09.076 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:00:09.554 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:00:09.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:09.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:09.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:09.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:10.031 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:00:10.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:10.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:10.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:10.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:10.509 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:00:10.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:10.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:10.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:10.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:10.987 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:00:11.464 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:00:11.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:11.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:11.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:11.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:11.942 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:00:12.420 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:00:12.898 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:00:13.375 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:00:13.853 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:00:14.330 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:00:14.808 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:00:15.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:15.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:15.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:15.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:15.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:15.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:15.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:15.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:15.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:15.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:15.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:15.281 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:15.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:15.281 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:15.281 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:20.280 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:20.280 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:20.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:20.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:20.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:20.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:20.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:20.291 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:20.291 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:20.291 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:20.291 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:00:20.295 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:00:20.295 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:00:20.295 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:20.295 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:20.295 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:20.296 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:00:20.296 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:20.296 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:00:20.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:20.299 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:00:20.299 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:00:20.299 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:20.299 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:20.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:20.299 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:00:20.300 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:20.300 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:00:20.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:20.302 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:00:20.302 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:00:20.302 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:20.302 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:20.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:20.303 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:00:20.303 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:20.303 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:00:20.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.306 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:00:20.307 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:00:20.307 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:00:20.307 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:00:20.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:20.312 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:00:20.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:00:20.835 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:00:20.837 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:00:20.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:20.839 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:00:20.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:20.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:20.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:00:20.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:20.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:20.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:20.848 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:00:20.848 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:00:21.272 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:00:21.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:21.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:21.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:21.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:21.749 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:00:22.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:00:22.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:22.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:22.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:22.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:22.704 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:00:23.182 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:00:23.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:23.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:23.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:23.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:23.660 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:00:23.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:23.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:23.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:23.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:24.138 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:00:24.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:24.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:24.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:24.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:24.615 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:00:25.093 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:00:25.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:25.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:25.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:25.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:25.570 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:00:26.048 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:00:26.526 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:00:27.003 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:00:27.481 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:00:27.959 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:00:28.436 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:00:28.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:28.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:28.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:28.914 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:00:28.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:28.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:28.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:28.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:28.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:28.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:28.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:28.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:28.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:28.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:28.926 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:28.926 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:33.926 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:33.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:33.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:33.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:33.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:33.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:33.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:33.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:33.937 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:33.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:33.937 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:00:33.940 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:00:33.940 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:00:33.940 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:33.941 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:33.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:33.941 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:00:33.942 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:33.942 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:00:33.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:33.942 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:00:33.943 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:00:33.943 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:33.943 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:33.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:33.943 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:00:33.944 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:33.944 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:00:33.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:33.945 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:33.945 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:00:33.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:33.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:00:33.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:00:33.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:00:33.949 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:33.953 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:00:34.436 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:00:34.474 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:00:34.474 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:00:34.476 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:00:34.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:34.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:34.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:34.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:00:34.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:34.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:34.484 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:34.484 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:00:34.484 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:00:34.914 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:00:34.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:34.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:34.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:34.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:35.391 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:00:35.865 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:00:35.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:35.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:35.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:35.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:36.336 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:00:36.814 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:00:36.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:36.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:36.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:36.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:37.291 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:00:37.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:37.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:37.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:37.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:37.769 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:00:37.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:37.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:37.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:37.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:38.246 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:00:38.719 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:00:38.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:38.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:38.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:38.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:39.197 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:00:39.675 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:00:40.153 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:00:40.631 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:00:41.109 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:00:41.587 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:00:42.064 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:00:42.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:42.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:42.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:42.541 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:00:42.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:42.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:42.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:42.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:42.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:42.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:42.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:42.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:42.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:42.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:42.556 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:42.557 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:47.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:47.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:47.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:47.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:47.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:47.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:47.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:47.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:47.573 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:47.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:47.574 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:00:47.579 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:00:47.579 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:00:47.580 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:47.580 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:47.580 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:47.580 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:00:47.580 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:47.580 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:00:47.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:47.583 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:00:47.583 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:00:47.583 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:47.584 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:47.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:47.584 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:00:47.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:47.584 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:00:47.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:47.586 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:00:47.586 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:00:47.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:47.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:47.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:47.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:00:47.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:47.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:00:47.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:00:47.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:00:47.591 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:00:47.591 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:00:47.591 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:47.596 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:00:48.080 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:00:48.118 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:00:48.120 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:00:48.122 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:00:48.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:48.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:48.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:48.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:00:48.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:48.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:48.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:48.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:00:48.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:00:48.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:48.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:48.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:48.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:48.557 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:00:48.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:48.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:48.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:48.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:49.034 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:00:49.512 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:00:49.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:49.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:49.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:49.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:49.990 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:00:50.468 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:00:50.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:50.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:50.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:50.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:50.945 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:00:51.423 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:00:51.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:51.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:51.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:51.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:51.901 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:00:52.379 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:00:52.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:52.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:52.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:52.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:52.856 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:00:53.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:53.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:53.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:53.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:53.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:53.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:53.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:53.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:53.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:53.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:53.185 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:53.185 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:00:53.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1194 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:53.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1195 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:00:58.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:00:58.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:00:58.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:58.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:58.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:58.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:58.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:00:58.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:58.197 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:58.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:00:58.197 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:00:58.199 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:00:58.200 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:00:58.200 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:58.200 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:58.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:00:58.200 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:00:58.200 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:00:58.200 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:00:58.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:58.202 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:00:58.203 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:00:58.203 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:58.203 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:58.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:00:58.203 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:00:58.203 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:00:58.203 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:00:58.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:58.205 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:00:58.205 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:00:58.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:58.207 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:00:58.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:00:58.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:00:58.207 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:00:58.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:00:58.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:00:58.208 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:00:58.208 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:00:58.208 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:00:58.213 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:00:58.696 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:00:58.729 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:00:58.730 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:00:58.730 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:00:58.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:00:58.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:00:58.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:00:58.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:00:58.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:00:58.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:00:58.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:00:58.735 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:00:58.735 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:00:59.173 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:00:59.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:00:59.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:00:59.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:00:59.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:00:59.650 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:01:00.128 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:01:00.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:00.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:00.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:00.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:00.606 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:01:01.084 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:01:01.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:01.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:01.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:01.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:01.562 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:01:01.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:01.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:01.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:01.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:02.039 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:01:02.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:02.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:02.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:02.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:02.517 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:01:02.995 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:01:03.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:03.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:03.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:03.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:03.472 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:01:03.950 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:01:04.428 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:01:04.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:04.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:04.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:04.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:04.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:04.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:04.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:04.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:04.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:04.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:04.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:04.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:04.485 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:01:04.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:09.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:09.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:09.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:09.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:09.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:09.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:09.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:09.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:09.490 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:09.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:09.491 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:01:09.491 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:01:09.491 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:09.492 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:09.492 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:09.492 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:09.492 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:01:09.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:09.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:09.493 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:01:09.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:09.494 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:01:09.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:01:09.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:01:09.495 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:01:09.495 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:01:09.495 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:09.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:09.500 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:01:09.971 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:01:10.010 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:01:10.010 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:01:10.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:10.011 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:01:10.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:10.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:10.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:01:10.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:10.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:10.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:10.014 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:01:10.014 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:01:10.440 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:01:10.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:10.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:10.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:10.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:10.908 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:01:11.377 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:01:11.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:11.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:11.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:11.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:11.845 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:01:12.314 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:01:12.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:12.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:12.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:12.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:12.782 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:01:13.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:13.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:13.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:13.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:13.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:13.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:13.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:13.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:13.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:13.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:13.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:13.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:13.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:13.098 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:01:18.099 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:18.099 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:18.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:18.099 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:18.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:18.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:18.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:18.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:18.104 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:18.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:18.104 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:18.105 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:18.105 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:01:18.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:18.106 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:18.106 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:01:18.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:18.107 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:01:18.107 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:01:18.107 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:18.107 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:18.107 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:01:18.108 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:18.108 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:18.108 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:01:18.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:01:18.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:01:18.109 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:01:18.110 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:18.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:18.114 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:01:18.583 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:01:18.622 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:01:18.622 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:01:18.623 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:01:18.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:18.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:18.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:18.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:01:18.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:18.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:18.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:18.626 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:01:18.626 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:01:19.051 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:01:19.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:19.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:19.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:19.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:19.519 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:01:19.989 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:01:20.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:20.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:20.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:20.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:20.457 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:01:20.925 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:01:21.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:21.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:21.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:21.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:21.394 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:01:21.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:21.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:21.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:21.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:21.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:21.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:21.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:21.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:21.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:21.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:21.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:21.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:21.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:21.712 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:01:26.711 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:26.711 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:26.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:26.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:26.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:26.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:26.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:26.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:26.717 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:26.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:26.717 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:26.718 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:26.718 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:01:26.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:26.719 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:26.719 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:01:26.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:26.720 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:26.720 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:01:26.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:01:26.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:01:26.722 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:01:26.722 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:01:26.722 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:26.727 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:01:27.197 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:01:27.235 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:01:27.235 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:01:27.236 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:01:27.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:27.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:27.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:27.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:01:27.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:27.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:27.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:27.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:01:27.238 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:01:27.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:27.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:27.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:27.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:27.513 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:01:32.514 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:32.514 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:32.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:32.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:32.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:32.516 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:32.518 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:32.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:32.519 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:32.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:32.519 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:01:32.519 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:01:32.520 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:01:32.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:32.520 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:32.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:32.520 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:01:32.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:32.520 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:01:32.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:32.521 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:32.521 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:01:32.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:32.522 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:32.522 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:01:32.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:01:32.524 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:01:32.524 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:01:32.524 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:32.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:32.529 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:01:32.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:01:33.037 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:01:33.038 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:01:33.038 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:01:33.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:33.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:33.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:33.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:01:33.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:33.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:33.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:33.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:01:33.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:01:33.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:33.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:33.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:33.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:33.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:33.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:33.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:33.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:33.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:33.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:33.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:33.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:33.080 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:01:38.081 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:38.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:38.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:38.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:38.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:38.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:38.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:38.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:38.087 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:38.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:38.087 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:38.088 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:38.088 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:01:38.088 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:38.089 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:38.089 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:01:38.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:38.089 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:38.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:38.090 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:01:38.090 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:38.090 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:01:38.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:01:38.091 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:01:38.091 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:01:38.091 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:38.096 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:01:38.565 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:01:38.603 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:01:38.603 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:01:38.604 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:01:38.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:38.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:38.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:38.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:01:38.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:38.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:38.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:38.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:01:38.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:01:39.035 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:01:39.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:39.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:39.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:39.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:39.507 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:01:39.978 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:01:40.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:40.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:40.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:40.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:40.449 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:01:40.919 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:01:41.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:41.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:41.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:41.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:41.390 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:01:41.861 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:01:42.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:42.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:42.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:42.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:42.332 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:01:42.803 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:01:43.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:43.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:43.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:43.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:43.273 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:01:43.744 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:01:44.214 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:01:44.685 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:01:45.155 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:01:45.624 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:01:46.092 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:01:46.562 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:01:47.034 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:01:47.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:47.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:47.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:47.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:47.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:47.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:47.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:47.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:47.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:47.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:47.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:47.324 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:01:47.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:52.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:01:52.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:01:52.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:52.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:52.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:52.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:52.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:01:52.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:52.329 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:52.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:01:52.329 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:52.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:01:52.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:01:52.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:52.331 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:01:52.331 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:01:52.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:52.331 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:01:52.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:01:52.332 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:01:52.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:01:52.332 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:01:52.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:01:52.333 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:01:52.333 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:01:52.333 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:01:52.338 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:01:52.806 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:01:52.846 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:01:52.847 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:01:52.847 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:01:52.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:01:52.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:01:52.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:01:52.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:01:52.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:01:52.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:01:52.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:01:52.850 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:01:52.850 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:01:53.277 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:01:53.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:53.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:53.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:53.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:53.744 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:01:54.212 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:01:54.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:54.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:54.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:54.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:54.681 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:01:55.152 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:01:55.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:55.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:55.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:55.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:55.622 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:01:56.092 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:01:56.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:56.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:56.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:56.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:56.563 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:01:57.034 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:01:57.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:01:57.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:01:57.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:01:57.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:01:57.505 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:01:57.976 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:01:58.446 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:01:58.917 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:01:59.388 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:01:59.856 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:02:00.324 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:02:00.796 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:02:01.266 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:02:01.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:02:01.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:02:01.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:01.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:01.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:01.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:01.597 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:01.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:01.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:01.597 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:01.597 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:01.597 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:01.597 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:02:06.598 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:06.598 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:06.598 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:06.598 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:06.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:06.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:06.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:06.602 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:06.602 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:06.602 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:06.602 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:02:06.603 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:02:06.603 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:02:06.603 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:06.603 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:06.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:06.603 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:06.604 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:06.604 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:06.604 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:02:06.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:06.605 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:06.605 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:02:06.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:02:06.606 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:02:06.606 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:02:06.606 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:06.611 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:02:07.082 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:02:07.119 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:02:07.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:07.120 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:02:07.121 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:07.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:02:07.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:02:07.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:02:07.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:02:07.123 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:02:07.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:02:07.123 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:02:07.123 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:02:07.551 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:02:07.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:07.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:07.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:07.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:08.023 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:02:08.493 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:02:08.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:08.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:08.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:08.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:08.962 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:02:09.429 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:02:09.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:09.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:09.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:09.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:09.896 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:02:10.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:02:10.134 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:02:10.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:02:10.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:02:10.180 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.221 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.263 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.300 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.341 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.363 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:02:10.378 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.415 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.457 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.498 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.535 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.577 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:10.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:10.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:10.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:10.618 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:10.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:02:10.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:02:10.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:10.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:10.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:10.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:10.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:10.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:10.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:10.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:10.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:10.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:10.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:10.658 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:02:15.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:15.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:15.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:15.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:15.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:15.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:15.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:15.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:15.680 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:15.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:15.681 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:02:15.682 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:02:15.682 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:02:15.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:15.683 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:15.683 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:15.683 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:02:15.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:15.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:02:15.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:15.684 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:15.684 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:02:15.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:15.685 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:15.685 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:02:15.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:15.686 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:02:15.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:02:15.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:02:15.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:02:15.686 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:02:15.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:02:15.687 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:02:15.687 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:02:15.687 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:15.692 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:02:16.175 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:02:16.210 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:02:16.212 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:02:16.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:16.214 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:16.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:16.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:16.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:16.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:16.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:16.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:16.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:16.278 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:16.278 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:16.278 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:02:16.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:16.278 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:02:21.280 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:21.280 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:21.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:21.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:21.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:21.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:21.294 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:21.295 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:21.296 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:21.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:21.296 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:02:21.300 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:02:21.300 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:02:21.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:21.301 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:21.301 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:21.301 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:02:21.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:21.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:02:21.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:21.303 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:02:21.303 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:02:21.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:21.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:21.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:21.304 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:02:21.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:21.304 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:02:21.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:21.305 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:02:21.305 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:02:21.306 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:21.306 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:21.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:21.306 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:02:21.306 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:21.306 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:02:21.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:21.308 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.309 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:02:21.309 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:02:21.309 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:02:21.309 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:21.314 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:02:21.798 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:02:21.836 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:02:21.839 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:02:21.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:21.841 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:22.275 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:02:22.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:22.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:22.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:22.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:22.753 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:02:23.231 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:02:23.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:23.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:23.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:23.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:23.704 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:02:24.186 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:02:24.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:24.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:24.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:24.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:24.666 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:02:25.141 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:02:25.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:25.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:25.319 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:25.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:25.610 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:02:26.079 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:02:26.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:26.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:26.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:26.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:26.547 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:02:27.018 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:02:27.488 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:02:27.957 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:02:28.432 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:02:28.900 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:02:29.367 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:02:29.836 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:02:30.305 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:02:30.773 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:02:30.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:30.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:30.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:30.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:30.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:30.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:30.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:30.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:30.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:30.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:30.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:30.869 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:02:35.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:35.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:35.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:35.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:35.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:35.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:35.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:35.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:35.886 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:35.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:35.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:02:35.891 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:02:35.891 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:02:35.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:35.892 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:35.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:35.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:02:35.893 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:35.893 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:02:35.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:35.894 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:02:35.894 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:02:35.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:35.894 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:35.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:35.895 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:02:35.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:35.895 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:02:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:35.896 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:02:35.896 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:02:35.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:35.896 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:35.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:35.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:02:35.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:35.897 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:02:35.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:35.899 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:02:35.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:02:35.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:02:35.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:02:35.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:02:35.900 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:02:35.900 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:35.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:02:36.381 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:02:36.429 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:02:36.430 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:02:36.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:36.432 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:36.850 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:02:36.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:36.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:36.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:36.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:37.319 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:02:37.796 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:02:37.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:37.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:37.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:37.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:38.266 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:02:38.738 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:02:38.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:38.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:38.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:38.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:39.215 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:02:39.692 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:02:39.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:39.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:39.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:39.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:40.166 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:02:40.642 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:02:40.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:40.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:40.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:40.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:41.118 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:02:41.588 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:02:42.059 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:02:42.536 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:02:43.013 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:02:43.483 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:02:43.951 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:02:44.434 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:02:44.908 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:02:45.376 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:02:45.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:45.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:45.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:45.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:45.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:45.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:45.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:45.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:45.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:45.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:45.458 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:02:45.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:50.459 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:50.459 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:50.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:50.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:50.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:50.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:50.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:50.466 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:50.467 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:50.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:50.467 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:50.468 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:50.468 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:02:50.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:50.469 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:50.469 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:02:50.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:50.471 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:50.471 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:02:50.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:02:50.474 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:02:50.474 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:50.478 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:02:50.955 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:02:50.988 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:02:50.989 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:02:50.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:50.990 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:51.424 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:02:51.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:51.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:51.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:51.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:51.893 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:02:52.367 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:02:52.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:52.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:52.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:52.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:52.835 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:02:53.304 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:02:53.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:53.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:53.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:53.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:53.772 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:02:54.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:54.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:54.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:54.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:54.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:54.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:54.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:54.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:54.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:54.001 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:54.001 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:54.001 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:02:59.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:02:59.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:02:59.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:59.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:59.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:59.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:59.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:02:59.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:59.014 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:59.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:02:59.014 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:02:59.017 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:02:59.017 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:02:59.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:59.018 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:59.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:02:59.018 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:02:59.018 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:02:59.018 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:02:59.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:02:59.020 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:02:59.020 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:02:59.020 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:59.020 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:59.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:02:59.021 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:02:59.021 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:02:59.021 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:02:59.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:59.023 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:02:59.023 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:02:59.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.026 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:02:59.026 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:02:59.026 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:02:59.026 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:02:59.031 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:02:59.515 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:02:59.556 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:02:59.558 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:02:59.559 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:02:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:59.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:02:59.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:02:59.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:02:59.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:02:59.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:02:59.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:02:59.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:02:59.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:02:59.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:59.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:02:59.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:02:59.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:02:59.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:02:59.990 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:02:59.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:02:59.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:03:00.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:00.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:00.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:00.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:00.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:00.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:00.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:00.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:00.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:00.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:00.011 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:00.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:00.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:00.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:05.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:05.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:05.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:05.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:05.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:05.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:05.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:05.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:05.021 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:05.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:05.021 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:05.021 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:05.022 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:05.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:05.022 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:05.022 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:05.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:05.023 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:05.023 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:05.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:05.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:05.025 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:05.025 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:05.030 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:05.508 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:05.557 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:05.557 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:05.558 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:05.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:05.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:05.562 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:05.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:10.563 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:10.563 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:10.563 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:10.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:10.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:10.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:10.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:10.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:10.573 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:10.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:10.574 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:10.576 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:10.576 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:10.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:10.578 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:10.578 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:10.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:10.578 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:10.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:10.579 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:10.579 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:10.579 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:10.579 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:10.580 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:10.581 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:10.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:10.581 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:10.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:10.581 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:10.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:10.581 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:10.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:10.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.584 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:10.584 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:10.584 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:10.584 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:10.589 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:11.066 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:11.104 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:11.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:11.105 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:11.106 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:11.541 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:03:11.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:11.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:11.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:11.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:12.017 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:03:12.493 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:03:12.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:12.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:12.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:12.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:12.970 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:03:13.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:13.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:13.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:13.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:13.124 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:13.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:13.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:13.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:13.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:13.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:13.124 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:18.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:18.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:18.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:18.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:18.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:18.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:18.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:18.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:18.128 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:18.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:18.128 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:18.129 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:18.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:18.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:18.130 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:18.130 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:18.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:18.131 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:18.131 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:18.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.132 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:18.132 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:18.132 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:18.132 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:18.137 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:18.617 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:18.645 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:18.646 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:18.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:18.646 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:18.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:18.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:18.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:03:18.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:03:18.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:03:18.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:03:18.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:03:18.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:03:19.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:03:19.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:19.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:19.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:19.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:19.568 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:03:20.045 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:03:20.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:20.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:20.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:20.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:20.523 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:03:21.001 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:03:21.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:21.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:21.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:21.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:21.478 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:03:21.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:21.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:21.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:21.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:21.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:21.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:21.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:21.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:21.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:21.503 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:21.503 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:21.503 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:21.503 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:21.503 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:26.505 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:26.505 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:26.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:26.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:26.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:26.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:26.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:26.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:26.516 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:26.517 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:26.517 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:26.520 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:26.520 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:26.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:26.523 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:26.523 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:26.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:26.525 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:26.525 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:26.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:26.525 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:26.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:26.525 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:26.526 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:26.526 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:26.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:26.529 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:26.529 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:26.529 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:26.534 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:27.016 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:27.063 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:27.066 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:27.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:27.069 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:27.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:27.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:27.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:03:27.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:03:27.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:03:27.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:03:27.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:03:27.074 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:03:27.494 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:03:27.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:27.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:27.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:27.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:27.971 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:03:28.449 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:03:28.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:28.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:28.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:28.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:28.927 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:03:29.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:29.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:29.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:29.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:29.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:29.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:29.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:29.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:29.186 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:29.186 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:29.186 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:29.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:29.186 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:29.186 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:34.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:34.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:34.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:34.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:34.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:34.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:34.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:34.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:34.204 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:34.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:34.204 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:34.206 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:34.207 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:34.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:34.207 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:34.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:34.208 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:34.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:34.209 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:34.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:34.210 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:34.210 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:34.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:34.210 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:34.211 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:34.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:34.211 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:34.211 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:34.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:34.214 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:34.214 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:34.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:34.214 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:34.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:34.214 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:34.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:34.214 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:34.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:34.217 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:34.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.218 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:34.218 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:34.218 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:34.219 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:34.223 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:34.708 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:34.742 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:34.743 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:34.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:34.745 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:34.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:34.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:34.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:03:34.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:03:34.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:03:34.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:03:34.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:03:34.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:03:35.185 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:03:35.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:35.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:35.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:35.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:35.663 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:03:36.140 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:03:36.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:36.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:36.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:36.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:36.617 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:03:37.095 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:03:37.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:37.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:37.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:37.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:37.573 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:03:37.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:37.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:37.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:37.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:37.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:37.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:37.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:37.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:37.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:37.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:37.595 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:37.595 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:37.595 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:42.597 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:42.597 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:42.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:42.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:42.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:42.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:42.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:42.608 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:42.608 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:42.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:42.609 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:42.610 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:42.611 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:42.611 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:42.611 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:42.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:42.612 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:42.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:42.612 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:42.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:42.614 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:42.614 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:42.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:42.615 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:42.615 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:42.615 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:42.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:42.615 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:42.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:42.618 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:42.618 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:42.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:42.618 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:42.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:42.618 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:42.619 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:42.619 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:42.619 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:42.622 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:42.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:42.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:42.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:42.622 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.623 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:42.623 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:42.623 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:42.624 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:42.629 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:43.112 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:43.152 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:43.154 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:43.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:43.156 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:43.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:43.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:43.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:03:43.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:03:43.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:03:43.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:03:43.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:03:43.163 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:03:43.590 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:03:43.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:43.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:43.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:43.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:44.067 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:03:44.545 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:03:44.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:44.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:44.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:44.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:45.023 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:03:45.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:45.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:45.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:45.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:45.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:45.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:45.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:45.286 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:45.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:45.286 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:45.286 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:45.286 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:45.286 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:45.287 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:50.291 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:50.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:50.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:50.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:50.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:50.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:50.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:50.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:50.299 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:50.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:50.299 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:50.301 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:50.302 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:50.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:50.302 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:50.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:50.302 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:50.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:50.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:50.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:50.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:50.304 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:50.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:50.305 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:50.305 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:50.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:50.305 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:50.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:50.305 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:50.306 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:50.306 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:50.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:50.308 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:50.308 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:50.308 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:50.312 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:03:50.796 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:03:50.829 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:03:50.831 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:03:50.833 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:03:50.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:03:50.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:50.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:03:50.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:03:50.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:03:50.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:03:50.840 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:03:50.840 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:03:51.273 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:03:51.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:51.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:51.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:51.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:51.750 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:03:52.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:03:52.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:52.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:52.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:52.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:52.705 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:03:53.183 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:03:53.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:53.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:53.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:53.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:53.660 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:03:54.138 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:03:54.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:54.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:54.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:54.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:54.615 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:03:54.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:03:54.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:03:54.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:54.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:54.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:54.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:54.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:54.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:54.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:54.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:54.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:54.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:54.640 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:03:54.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:54.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:54.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:54.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:54.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:54.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:03:59.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:03:59.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:03:59.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:59.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:59.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:59.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:59.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:03:59.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:59.675 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:59.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:03:59.675 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:03:59.676 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:03:59.676 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:03:59.677 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:59.677 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:59.677 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:03:59.678 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:03:59.678 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:03:59.679 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:03:59.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:03:59.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:03:59.681 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:03:59.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:59.681 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:59.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:03:59.682 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:03:59.682 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:03:59.682 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:03:59.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:03:59.684 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:03:59.685 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:03:59.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:59.685 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:03:59.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:03:59.685 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:03:59.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:03:59.685 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:03:59.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:03:59.689 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:03:59.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:03:59.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:03:59.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:03:59.689 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:03:59.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.690 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:03:59.690 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:03:59.690 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:03:59.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:03:59.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:00.180 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:00.220 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:00.222 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:00.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:00.226 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:00.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:04:00.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:04:00.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:04:00.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:04:00.231 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:04:00.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:04:00.231 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:04:00.231 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:04:00.657 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:04:00.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:00.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:00.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:00.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:01.134 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:04:01.612 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:04:01.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:01.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:01.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:01.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:02.090 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:04:02.568 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:04:02.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:02.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:02.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:02.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:03.045 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:04:03.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:04:03.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:04:03.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:03.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:03.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:03.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:03.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:03.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:03.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:03.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:03.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:03.310 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:03.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=772 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:03.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:08.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:08.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:08.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:08.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:08.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:08.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:08.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:08.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:08.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:08.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:08.322 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:08.324 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:08.324 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:08.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:08.325 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:08.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:08.325 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:08.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:08.326 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:08.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:08.326 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:08.326 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:08.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:08.327 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:08.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:08.327 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:08.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:08.327 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:08.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:08.329 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:08.329 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:08.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:08.331 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:08.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:08.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:08.332 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:08.332 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:08.332 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:08.337 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:08.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:08.861 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:08.863 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:08.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:08.864 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:09.301 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:04:09.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:09.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:09.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:09.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:09.781 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:04:10.261 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:04:10.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:10.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:10.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:10.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:10.729 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:04:10.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:10.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:10.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:10.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:10.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:10.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:10.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:10.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:10.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:10.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:10.875 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:10.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:15.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:15.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:15.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:15.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:15.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:15.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:15.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:15.891 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:15.891 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:15.891 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:15.891 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:15.895 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:15.895 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:15.895 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:15.895 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:15.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:15.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:15.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:15.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:15.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:15.898 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:15.899 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:15.899 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:15.899 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:15.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:15.900 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:15.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:15.900 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:15.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:15.901 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:15.901 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:15.902 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:15.902 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:15.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:15.902 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:15.902 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:15.902 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:15.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:15.904 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:15.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:15.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:15.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:15.904 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:15.905 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:15.905 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:15.905 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:15.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:15.910 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:16.394 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:16.443 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:16.444 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:16.446 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:16.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:16.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:04:16.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:04:16.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:04:16.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:16.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:16.874 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:04:16.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:16.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:16.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:16.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:17.355 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:04:17.833 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:04:17.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:17.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:17.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:17.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:18.311 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:04:18.789 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:04:18.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:18.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:18.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:18.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:19.268 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:04:19.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:19.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:19.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:19.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:19.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:19.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:19.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:19.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:19.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:19.501 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:19.501 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:19.501 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:19.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:24.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:24.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:24.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:24.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:24.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:24.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:24.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:24.514 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:24.514 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:24.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:24.515 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:24.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:24.517 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:24.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:24.517 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:24.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:24.518 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:24.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:24.519 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:24.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:24.519 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:24.519 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:24.519 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:24.519 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:24.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:24.520 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:24.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:24.520 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:24.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:24.521 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:24.521 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:24.521 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:24.521 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:24.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:24.522 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:24.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:24.522 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:24.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:24.525 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:24.525 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:24.525 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:24.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:25.012 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:25.052 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:25.054 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:25.054 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:25.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:25.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:04:25.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:04:25.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:04:25.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:25.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:25.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:25.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:25.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:25.095 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:30.097 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:30.097 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:30.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:30.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:30.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:30.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:30.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:30.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:30.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:30.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:30.109 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:30.111 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:30.111 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:30.112 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:30.112 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:30.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:30.112 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:30.113 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:30.113 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:30.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:30.113 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:30.113 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:30.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:30.113 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:30.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:30.114 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:30.114 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:30.114 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:30.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:30.115 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:30.115 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:30.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:30.115 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:30.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:30.116 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:30.116 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:30.116 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:30.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.118 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:30.118 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:30.118 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:30.119 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.123 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:30.607 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:30.644 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:30.646 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:30.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:30.648 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:30.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:04:30.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:04:30.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:04:30.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:30.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:31.085 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:04:31.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:31.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:31.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:31.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:31.565 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:04:32.046 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:04:32.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:32.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:32.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:32.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:32.525 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:04:33.003 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:04:33.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:33.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:33.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:33.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:33.481 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:04:33.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:33.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:33.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:33.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:33.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:33.695 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:33.695 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=762 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:38.698 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:38.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:38.700 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:38.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:38.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:38.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:38.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:38.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:38.711 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:38.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:38.712 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:38.715 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:38.715 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:38.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:38.716 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:38.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:38.716 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:38.717 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:38.717 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:38.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:38.718 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:38.718 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:38.718 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:38.718 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:38.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:38.719 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:38.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:38.719 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:38.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:38.720 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:38.720 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:38.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:38.720 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:38.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:38.721 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:38.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:38.721 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:38.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:38.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:38.724 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:38.724 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:38.724 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:38.729 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:39.213 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:39.250 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:39.253 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:39.255 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:39.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:39.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:04:39.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:04:39.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:04:39.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:39.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:39.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:39.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:39.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:39.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:39.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:39.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:39.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:39.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:39.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:39.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:39.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:39.311 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:39.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:39.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:44.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:44.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:44.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:44.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:44.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:44.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:44.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:44.324 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:44.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:44.324 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:44.327 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:44.327 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:44.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:44.327 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:44.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:44.328 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:44.328 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:44.328 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:44.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:44.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:44.331 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:44.331 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:44.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.333 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:44.333 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:44.333 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:44.334 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:44.338 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:44.823 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:44.857 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:44.859 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:44.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:44.862 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:44.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:44.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:44.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:44.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:44.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:44.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:44.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:44.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:44.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:44.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:44.875 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:44.875 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:49.874 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:49.874 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:49.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:49.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:49.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:49.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:49.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:49.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:49.887 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:49.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:49.887 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:49.892 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:49.892 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:49.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:49.892 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:49.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:49.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:49.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:49.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:49.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:49.895 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:49.895 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:49.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:49.895 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:49.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:49.896 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:49.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:49.896 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:49.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:49.898 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:49.898 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:49.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:49.898 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:49.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:49.899 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:49.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:49.899 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:49.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.902 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:49.902 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:49.902 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:49.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:49.907 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:50.392 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:50.438 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:50.440 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:50.442 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:50.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:50.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:50.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:50.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:50.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:50.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:50.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:50.459 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:50.459 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:50.459 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:50.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:50.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:55.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:55.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:55.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:55.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:55.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:55.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:55.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:55.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:55.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:55.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:04:55.473 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:04:55.476 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:04:55.476 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:04:55.477 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:55.477 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:55.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:55.478 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:04:55.478 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:04:55.478 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:04:55.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:55.479 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:04:55.479 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:04:55.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:55.480 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:55.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:55.480 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:04:55.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:04:55.480 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:04:55.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:55.481 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:04:55.481 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:04:55.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:55.482 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:04:55.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:55.482 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:04:55.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:04:55.482 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:04:55.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:55.484 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:04:55.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:04:55.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:04:55.485 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:04:55.485 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:04:55.485 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:04:55.490 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:04:55.974 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:04:56.014 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:04:56.016 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:04:56.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:04:56.019 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:04:56.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:04:56.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:04:56.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:04:56.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:04:56.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:04:56.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:04:56.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:04:56.037 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:04:56.037 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:04:56.037 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:04:56.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.038 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.039 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.039 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.039 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.039 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:04:56.039 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:01.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:01.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:01.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:01.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:01.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:01.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:01.050 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:01.050 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:01.050 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:01.050 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:01.053 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:01.053 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:01.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:01.053 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:01.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:01.054 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:01.054 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:01.054 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:01.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:01.055 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:01.056 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:01.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:01.056 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:01.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:01.056 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:01.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:01.056 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:01.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:01.058 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:01.058 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:01.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:01.061 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:01.061 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:01.061 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:01.065 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:01.549 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:01.584 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:01.587 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:01.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:01.589 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:01.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:01.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:01.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:01.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:01.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:01.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:01.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:01.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:01.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:01.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:01.606 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:01.606 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:06.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:06.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:06.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:06.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:06.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:06.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:06.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:06.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:06.616 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:06.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:06.616 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:06.620 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:06.620 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:06.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:06.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:06.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:06.621 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:06.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:06.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:06.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:06.624 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:06.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:06.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:06.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:06.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:06.625 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:06.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:06.625 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:06.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:06.627 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:06.627 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:06.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:06.628 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:06.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:06.628 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:06.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:06.628 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:06.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:06.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:06.633 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:06.633 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:06.633 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:06.637 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:07.121 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:07.168 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:07.169 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:07.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:07.171 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:07.590 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:05:07.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:07.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:07.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:08.059 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:05:08.529 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:05:08.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:08.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:08.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:08.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:09.007 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:05:09.485 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:05:09.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:09.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:09.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:09.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:09.966 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:05:10.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:10.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:10.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:05:10.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:05:10.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:05:10.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:05:10.194 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:05:10.194 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:05:10.445 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:05:10.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:10.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:10.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:10.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:10.924 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:05:11.401 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:05:11.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:11.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:11.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:11.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:11.880 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:05:12.357 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:05:12.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:12.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:12.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:12.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:12.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:12.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:12.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:12.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:12.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:12.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:12.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:12.518 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:12.518 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:12.518 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:12.519 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1260 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:12.519 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1260 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:12.519 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1260 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:12.519 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1260 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:12.519 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1260 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:12.519 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1260 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:17.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:17.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:17.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:17.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:17.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:17.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:17.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:17.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:17.531 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:17.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:17.531 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:17.534 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:17.534 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:17.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:17.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:17.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:17.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:17.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:17.535 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:17.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:17.538 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:17.538 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:17.538 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:17.538 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:17.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:17.539 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:17.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:17.539 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:17.540 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:17.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:17.541 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:17.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:17.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:17.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:17.544 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:17.544 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:17.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:18.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:18.072 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:18.074 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:18.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:18.076 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:18.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:18.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:18.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:05:18.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:18.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:18.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:18.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:18.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:18.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:18.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:18.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:18.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:18.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:18.116 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:18.116 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:23.117 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:23.117 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:23.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:23.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:23.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:23.121 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:23.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:23.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:23.132 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:23.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:23.133 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:23.137 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:23.138 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:23.138 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:23.138 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:23.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:23.138 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:23.138 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:23.139 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:23.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:23.141 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:23.141 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:23.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:23.141 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:23.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:23.141 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:23.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:23.142 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:23.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:23.145 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:23.145 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:23.145 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:23.145 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:23.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:23.146 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:23.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:23.146 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:23.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:23.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:23.150 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:23.150 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:23.150 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:23.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.155 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:23.638 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:23.681 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:23.683 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:23.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:23.685 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:23.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:23.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:23.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:05:23.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:23.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:23.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:23.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:23.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:23.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:23.724 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:23.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:23.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:23.724 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:23.724 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:23.724 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:23.724 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:28.730 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:28.730 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:28.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:28.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:28.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:28.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:28.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:28.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:28.740 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:28.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:28.740 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:28.743 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:28.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:28.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:28.744 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:28.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:28.745 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:28.745 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:28.745 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:28.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:28.746 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:28.747 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:28.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:28.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:28.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:28.748 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:28.748 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:28.748 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:28.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:28.749 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:28.750 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:28.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:28.750 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:28.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:28.750 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:28.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:28.750 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:28.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:28.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:28.754 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:28.754 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:28.754 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:28.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:28.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:28.759 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:29.243 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:29.295 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:29.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:29.296 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:29.297 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:29.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:29.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:29.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:05:29.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:29.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:29.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:29.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:29.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:29.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:29.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:29.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:29.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:29.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:29.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:29.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:29.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:29.317 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:34.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:34.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:34.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:34.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:34.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:34.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:34.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:34.336 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:34.336 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:34.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:34.337 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:34.341 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:34.341 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:34.341 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:34.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:34.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:34.343 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:34.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:34.343 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:34.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:34.344 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:34.344 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:34.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:34.345 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:34.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:34.345 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:34.345 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:34.345 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:34.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:34.347 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:34.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:34.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:34.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:34.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:34.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:34.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:34.348 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:34.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:34.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:34.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.351 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:34.351 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:34.351 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:34.351 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.356 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:34.841 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:34.874 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:34.875 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:34.876 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:34.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:34.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:34.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:05:34.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:34.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:34.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:34.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:34.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:34.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:34.924 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:34.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:34.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:34.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:34.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:34.924 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:34.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:34.924 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:34.925 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:39.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:39.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:39.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:39.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:39.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:39.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:39.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:39.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:39.937 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:39.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:39.937 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:39.940 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:39.940 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:39.941 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:39.941 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:39.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:39.942 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:39.942 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:39.942 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:39.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:39.943 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:39.943 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:39.944 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:39.944 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:39.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:39.944 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:39.945 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:39.945 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:39.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:39.945 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:39.946 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:39.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:39.946 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:39.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:39.946 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:39.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:39.946 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:39.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:39.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:39.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:39.949 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:39.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:39.954 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:40.437 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:40.481 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:40.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:40.484 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:40.488 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:40.491 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 02:05:40.491 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 200
2026-03-02 02:05:40.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 02:05:40.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:40.918 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:05:40.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:41.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:41.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:41.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:41.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:41.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:41.398 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:05:41.879 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:05:41.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:42.126 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 02:05:42.126 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 0
2026-03-02 02:05:42.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 02:05:42.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:42.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:42.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:42.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:42.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:42.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:42.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:42.136 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:47.138 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:47.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:47.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:47.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:47.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:47.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:47.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:47.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:47.153 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:47.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:47.153 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:47.155 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:47.156 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:47.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:47.156 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:47.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:47.157 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:47.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:47.158 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:47.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:47.158 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:47.158 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:47.158 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:47.158 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:47.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:47.159 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:47.159 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:47.159 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:47.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:47.161 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:47.161 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:47.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:47.165 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:47.165 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:47.165 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:47.170 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:47.654 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:47.694 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:47.696 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:47.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:47.699 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:47.701 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 02:05:47.701 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 200
2026-03-02 02:05:47.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 02:05:47.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:48.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:48.132 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:05:48.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:48.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:48.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:48.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:48.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:48.610 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:05:48.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:48.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.090 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:05:49.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.331 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 02:05:49.331 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 0
2026-03-02 02:05:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 02:05:49.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:49.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:49.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:49.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:49.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:49.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:49.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:49.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:49.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:49.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:49.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:49.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:49.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:49.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:49.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:49.341 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:54.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:54.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:54.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:54.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:54.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:54.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:54.355 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:54.355 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:54.355 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:54.355 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:54.355 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:54.355 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:54.356 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:54.356 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:54.356 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:54.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:54.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:54.357 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:54.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:54.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:54.358 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:54.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:54.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:54.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:54.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:54.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:54.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:05:54.847 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:05:54.889 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:05:54.891 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:05:54.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:54.893 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:05:54.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:05:54.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:05:54.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:05:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:54.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:05:54.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:54.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:54.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:54.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:54.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:54.946 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:54.946 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:54.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:54.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:54.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:54.947 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:54.947 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:05:59.946 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:05:59.946 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:05:59.948 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:59.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:59.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:59.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:59.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:05:59.954 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:59.954 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:59.954 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:05:59.954 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:05:59.955 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:05:59.955 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:05:59.956 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:59.956 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:59.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:05:59.956 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:05:59.957 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:05:59.957 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:05:59.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:05:59.957 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:05:59.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:05:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:59.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:59.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:05:59.958 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:05:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:05:59.958 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:05:59.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:59.960 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:05:59.960 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:05:59.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.963 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:05:59.963 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:05:59.963 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:05:59.963 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:05:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:05:59.968 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:06:00.451 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:06:00.488 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:06:00.489 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:06:00.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:00.490 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:06:00.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:00.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:00.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:00.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:00.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:00.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:00.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:00.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:00.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:00.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:00.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:00.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:00.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:06:00.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:06:00.525 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:06:00.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:05.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:06:05.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:06:05.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:05.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:05.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:05.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:05.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:05.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:06:05.535 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:05.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:06:05.535 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:06:05.538 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:06:05.538 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:06:05.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:06:05.539 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:05.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:05.539 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:06:05.540 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:06:05.540 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:06:05.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:05.541 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:06:05.541 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:06:05.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:06:05.541 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:05.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:05.541 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:06:05.542 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:06:05.542 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:06:05.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:05.543 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:06:05.543 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:06:05.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:06:05.544 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:05.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:05.544 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:06:05.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:06:05.544 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:06:05.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:06:05.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:06:05.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:06:05.547 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:06:05.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:05.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:06:06.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:06:06.076 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:06:06.078 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:06:06.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:06.080 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:06:06.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:06.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:06.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:06.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:06.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:06.103 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:06.103 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:06.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:06.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:06.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:06.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:06.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:06.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:06.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:06.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:06.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:06.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:06.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:06.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:06.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:06.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:06.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:06.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:06.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:06.510 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:06:06.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:06.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:06.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:06.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:06.988 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:06:07.466 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:06:07.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:07.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:07.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:07.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:07.944 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:06:08.421 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:06:08.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:08.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:08.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:08.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:08.899 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:06:09.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:09.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:09.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:09.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:09.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:09.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:09.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:09.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:09.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:09.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:09.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:09.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:09.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:09.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:09.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:09.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:09.375 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:06:09.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:09.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:09.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:09.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:09.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:09.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:09.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:09.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:09.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:09.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:09.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:09.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:09.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:09.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:09.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:09.848 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:06:10.326 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:06:10.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:10.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:10.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:10.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:10.804 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:06:11.282 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:06:11.760 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:06:12.238 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:06:12.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:12.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:12.437 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:12.437 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:12.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:12.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:12.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:12.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:12.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:12.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:12.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:12.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:12.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:12.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:12.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:12.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:12.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:12.715 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:06:13.193 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:06:13.671 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:06:14.146 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:06:14.622 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:06:15.100 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:06:15.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:15.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:15.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:15.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:15.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:15.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:15.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:15.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:15.495 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:15.495 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:15.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:15.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:15.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:15.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:15.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:15.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:15.577 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:06:15.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:15.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:15.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:15.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:15.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:15.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:15.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:15.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:15.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:15.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:15.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:15.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.054 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:06:16.532 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:06:16.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:16.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:16.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:16.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:16.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:16.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:16.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:16.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:16.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:16.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:16.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:16.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:16.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:16.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:16.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:16.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:16.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:16.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:16.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:16.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:16.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:16.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:16.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:16.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:16.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:16.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:16.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:16.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:17.009 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:06:17.487 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:06:17.965 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:06:18.443 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:06:18.922 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:06:19.400 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:06:19.878 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:06:19.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:19.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:19.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:19.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:19.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:19.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:19.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:19.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:19.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:19.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:19.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:19.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:20.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:20.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:20.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:20.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:20.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:20.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:20.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:20.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:20.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:20.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:20.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:20.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:20.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:20.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:20.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:20.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:20.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:20.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:20.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:20.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:20.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:20.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:20.355 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:06:20.833 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:06:21.311 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:06:21.789 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:06:22.267 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:06:22.745 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:06:23.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:23.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:23.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:23.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:23.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:23.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:23.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:23.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:23.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:23.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:23.139 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:23.139 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:23.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:23.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:23.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:23.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:23.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:23.222 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:06:23.699 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:06:24.177 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:06:24.655 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:06:25.132 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:06:25.610 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:06:26.088 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:06:26.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:26.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:26.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:26.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:26.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:26.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:26.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.204 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:26.204 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:26.204 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:26.204 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:26.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:26.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:26.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:26.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:26.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:26.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:26.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:26.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:26.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:26.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:26.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:26.318 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:26.318 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:26.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:26.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:26.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:26.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:26.565 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:06:27.042 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:06:27.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:27.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:27.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:27.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:27.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:27.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:27.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:27.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:27.236 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:27.236 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:27.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:27.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:27.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:27.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:27.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:27.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:27.520 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:06:27.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:27.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:27.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:27.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:27.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:27.532 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:27.532 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:27.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:27.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:27.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:27.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:27.997 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:06:28.474 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:06:28.952 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:06:29.430 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:06:29.908 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:06:30.385 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:06:30.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:30.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:30.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:30.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:30.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:30.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:30.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:30.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:30.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:30.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:30.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:30.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:30.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:30.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:30.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:30.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:30.862 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:06:30.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:30.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:30.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:30.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:30.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:30.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:30.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:30.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:30.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:30.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:30.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:30.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:31.339 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:06:31.817 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:06:32.295 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:06:32.773 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:06:33.250 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:06:33.727 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:06:33.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:33.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:33.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:33.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:33.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:33.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:33.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:33.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:33.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:33.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:33.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:33.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:33.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:33.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:33.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:33.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:33.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:34.204 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:06:34.682 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:06:35.160 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:06:35.637 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:06:36.115 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:06:36.593 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:06:36.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:36.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:36.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:36.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:36.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:36.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:36.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:36.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:36.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:36.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:36.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:36.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:37.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:37.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:37.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:37.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:37.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:37.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:37.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:37.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:37.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:37.070 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:06:37.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:37.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:37.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:37.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:37.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:37.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:37.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:37.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:37.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:37.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:37.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:37.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:37.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:37.548 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:06:38.025 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:06:38.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:38.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:38.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:38.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:38.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:38.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:38.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:38.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:38.087 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:38.087 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:38.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:38.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:38.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:38.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:38.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:38.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:38.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:38.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:38.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:38.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:38.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:38.205 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:38.205 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:38.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:38.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:38.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:38.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:38.502 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:06:38.979 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:06:39.457 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:06:39.935 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:06:40.413 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:06:40.890 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:06:41.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:41.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:41.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:41.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:41.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:41.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:41.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:41.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:41.235 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:41.235 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:41.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:41.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:41.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:41.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.368 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:06:41.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:41.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:41.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:41.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:41.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:41.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:41.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:41.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:41.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:41.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:41.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:41.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:41.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:41.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:41.844 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:06:42.322 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:06:42.800 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:06:43.277 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:06:43.755 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:06:44.233 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:06:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:44.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:44.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:44.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:44.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:44.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:44.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:44.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:44.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:44.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:44.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:44.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:44.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:44.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:44.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:44.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:44.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:44.710 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:06:45.188 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:06:45.666 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:06:46.144 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:06:46.622 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:06:47.099 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:06:47.578 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:06:47.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:47.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:47.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:47.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:47.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:47.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:47.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:47.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:47.643 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:47.643 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:47.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:47.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:47.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:47.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:47.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:47.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:47.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:47.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:47.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:47.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.756 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:47.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:47.756 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:47.756 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:47.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:47.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:47.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:47.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:47.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:48.055 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:06:48.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:48.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:48.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:48.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:48.532 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:06:48.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:48.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:48.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:48.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:48.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:48.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:48.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:48.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:06:48.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:06:48.538 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:06:48.539 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:48.539 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9183 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:48.539 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9183 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:48.539 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9183 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:48.539 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9183 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:53.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:06:53.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:06:53.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:53.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:53.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:53.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:53.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:53.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:06:53.553 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:53.553 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:06:53.553 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:06:53.557 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:06:53.558 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:06:53.558 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:06:53.558 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:53.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:53.559 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:06:53.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:06:53.560 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:06:53.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:53.561 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:06:53.561 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:06:53.561 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:06:53.561 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:53.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:53.561 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:06:53.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:06:53.562 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:06:53.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:06:53.564 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:06:53.564 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:06:53.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:06:53.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:06:53.568 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:06:53.568 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:06:53.568 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:53.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:53.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:53.573 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:06:54.058 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:06:54.096 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:06:54.098 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:06:54.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.099 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:06:54.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:54.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:54.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:54.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:54.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:54.238 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:54.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.241 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.241 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:54.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:54.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:54.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:06:54.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:06:54.473 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:06:54.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:06:54.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:06:54.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.533 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:06:54.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:54.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:54.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:54.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:54.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:06:54.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:06:54.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:06:54.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:06:54.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:54.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:54.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:54.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:54.627 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:54.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:54.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:54.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:54.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:06:54.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:06:54.627 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:06:54.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=227 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:54.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=227 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:54.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=227 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:54.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=227 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:54.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=227 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:54.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=227 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:06:59.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:06:59.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:06:59.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:59.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:59.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:59.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:59.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:06:59.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:06:59.640 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:59.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:06:59.640 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:06:59.644 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:06:59.644 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:06:59.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:06:59.645 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:59.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:06:59.645 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:06:59.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:06:59.645 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:06:59.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:06:59.648 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:06:59.648 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:06:59.648 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:06:59.648 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:59.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:06:59.648 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:06:59.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:06:59.649 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:06:59.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:06:59.651 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:06:59.651 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:06:59.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:06:59.651 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:06:59.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:06:59.651 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:06:59.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:06:59.652 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:06:59.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:06:59.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:06:59.656 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:06:59.656 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:06:59.656 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:06:59.661 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:07:00.143 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:07:00.184 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:07:00.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:00.188 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:07:00.190 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:07:00.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:00.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:00.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:00.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:00.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:00.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:00.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:00.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:00.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:00.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:00.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:00.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:00.615 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:07:00.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:00.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:00.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:00.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:01.092 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:07:01.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:01.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:01.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:01.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:01.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:01.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:01.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:01.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:01.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:01.133 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:01.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:01.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:01.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:01.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.569 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:07:01.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:01.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:01.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:01.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:01.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:01.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:01.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:01.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:01.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:01.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:01.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:01.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:01.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:01.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:01.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:01.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:01.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:01.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:01.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:02.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:02.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:02.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:02.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:02.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:02.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:02.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:02.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:02.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:02.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:02.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:02.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:02.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:02.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:02.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:02.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:02.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:02.046 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:07:02.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:02.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:02.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:02.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:02.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:02.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:02.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:02.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:02.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:02.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:02.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:02.453 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:02.453 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:02.453 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:07:02.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=599 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:02.454 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:07.455 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:07.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:07.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:07.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:07.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:07.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:07.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:07.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:07.465 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:07.465 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:07.465 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:07:07.469 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:07:07.470 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:07:07.470 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:07.470 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:07.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:07.470 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:07:07.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:07.471 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:07:07.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:07.473 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:07:07.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:07:07.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:07.473 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:07.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:07.474 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:07:07.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:07.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:07:07.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:07.476 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:07.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:07:07.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:07:07.480 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:07:07.480 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:07:07.480 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:07.485 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:07:07.969 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:07:08.014 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:07:08.016 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:07:08.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.019 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:07:08.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:08.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:08.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:08.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:08.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:08.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:08.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.446 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:07:08.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:08.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:08.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:08.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:08.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:08.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:08.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:08.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.923 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:07:08.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:08.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:08.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:08.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:08.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:08.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:08.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:08.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:08.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:08.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:09.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:09.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:09.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:09.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:09.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:09.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:09.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:09.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:09.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:09.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:09.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:09.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:09.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:09.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:09.328 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:07:09.328 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:09.328 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:09.328 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:09.328 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:09.328 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:09.329 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:09.329 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:14.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:14.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:14.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:14.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:14.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:14.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:14.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:14.343 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:14.343 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:14.343 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:14.343 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:07:14.346 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:07:14.346 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:07:14.347 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:14.347 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:14.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:14.348 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:07:14.348 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:14.348 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:07:14.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:14.350 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:07:14.350 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:07:14.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:14.350 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:14.350 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:14.350 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:07:14.351 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:14.351 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:07:14.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:14.353 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:07:14.353 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:07:14.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:14.354 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:14.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:14.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:07:14.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:14.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:07:14.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:07:14.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:07:14.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:07:14.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:07:14.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:14.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:07:14.848 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:07:14.896 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:07:14.897 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:07:14.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:14.899 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:07:14.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:14.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:14.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:14.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:14.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:14.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:14.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:14.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:14.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:14.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:14.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:14.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:14.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:15.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:15.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:15.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:15.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:15.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:15.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:15.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:15.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:15.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:15.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:15.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:15.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:15.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.325 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:07:15.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:15.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:15.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:15.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:15.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:15.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:15.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:15.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:15.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:15.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:15.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:15.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:15.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:15.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:15.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:15.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:15.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:15.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:15.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:15.801 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:07:15.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:15.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:15.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:15.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:15.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:15.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:15.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:15.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:15.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:15.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:15.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:15.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:16.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:16.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:16.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:16.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:16.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:16.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:16.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:16.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:16.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:16.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:16.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:16.205 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:16.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:16.206 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:07:16.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:16.206 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.206 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.206 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.206 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.207 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.207 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.207 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:16.207 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:21.205 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:21.205 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:21.209 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:21.209 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:21.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:21.209 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:21.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:21.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:21.222 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:21.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:21.222 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:07:21.224 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:07:21.225 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:07:21.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:21.225 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:21.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:21.225 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:07:21.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:21.226 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:07:21.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:21.226 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:07:21.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:07:21.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:21.227 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:21.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:21.227 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:07:21.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:21.227 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:07:21.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:21.228 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:07:21.228 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:07:21.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:21.228 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:21.229 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:21.229 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:07:21.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:21.229 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:07:21.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:07:21.231 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:07:21.231 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:07:21.231 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:07:21.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:21.236 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:07:21.719 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:07:21.765 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:07:21.768 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:07:21.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:21.770 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:07:21.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:21.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:21.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:21.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:21.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:21.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:21.798 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:21.798 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:21.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:21.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:21.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:21.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:21.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:22.196 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:07:22.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:22.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:22.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:22.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:22.674 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:07:23.151 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:07:23.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:23.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:23.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:23.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:23.629 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:07:23.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:23.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:23.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:23.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:23.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:23.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:23.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:23.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:23.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:23.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:23.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:23.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:23.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:23.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:23.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:23.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:23.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:24.106 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:07:24.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:24.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:24.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:24.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:24.584 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:07:25.062 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:07:25.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:25.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:25.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:25.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:25.541 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:07:25.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:25.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:25.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:25.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:25.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:25.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:25.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:25.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:25.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:25.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:25.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:25.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:25.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:25.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:25.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:25.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:25.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:26.018 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:07:26.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:26.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:26.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:26.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:26.496 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:07:26.973 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:07:27.451 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:07:27.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:27.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:27.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:27.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:27.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:27.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:27.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:27.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:27.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:27.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:27.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:27.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:27.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:27.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:27.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:27.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:27.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:27.928 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:07:28.406 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:07:28.883 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:07:29.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:29.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:29.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:29.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:29.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:29.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:29.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:29.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:29.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:29.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:29.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:29.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:29.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:29.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:29.355 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:07:29.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1736 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:29.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1736 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:29.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1736 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:29.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1736 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:07:34.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:34.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:34.360 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:34.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:34.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:34.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:34.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:34.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:34.374 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:34.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:34.374 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:34.377 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:34.377 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:07:34.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:34.379 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:07:34.379 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:07:34.379 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:34.379 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:34.379 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:34.379 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:07:34.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:34.380 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:07:34.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:34.381 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:34.381 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:07:34.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:07:34.383 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:07:34.383 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:07:34.383 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:34.388 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:07:34.871 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:07:34.910 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:07:34.912 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:07:34.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:34.914 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:07:34.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:34.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:34.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:34.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:34.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:34.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:34.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:34.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:34.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:34.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:34.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:34.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:34.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:35.348 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:07:35.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:35.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:35.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:35.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:35.826 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:07:36.304 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:07:36.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:36.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:36.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:36.781 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:07:36.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:36.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:36.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:36.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:36.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:36.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:36.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:36.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:36.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:36.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:36.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:36.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:36.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:36.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:36.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:36.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:36.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:37.258 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:07:37.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:37.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:37.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:37.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:37.736 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:07:38.211 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:07:38.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:38.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:38.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:38.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:38.688 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:07:39.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:39.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:39.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:39.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:39.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:39.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:39.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:39.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:39.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:39.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:39.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:39.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:39.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:39.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:39.070 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:39.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:39.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:39.165 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:07:39.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:39.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:39.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:39.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:39.643 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:07:40.121 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:07:40.599 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:07:40.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:40.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:40.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:40.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:40.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:40.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:40.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:40.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:40.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:40.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:40.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:40.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:40.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:40.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:40.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:40.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:40.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:41.076 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:07:41.553 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:07:42.031 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:07:42.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:42.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:42.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:42.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:42.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:42.508 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:07:42.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:42.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:42.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:42.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:42.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:42.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:42.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:42.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:42.512 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:07:42.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:47.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:07:47.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:07:47.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:47.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:47.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:47.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:47.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:07:47.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:47.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:47.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:07:47.525 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:07:47.527 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:07:47.528 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:07:47.528 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:47.528 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:47.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:07:47.529 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:07:47.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:07:47.529 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:07:47.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:47.530 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:07:47.530 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:07:47.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:47.532 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:07:47.532 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:07:47.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:47.534 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:07:47.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:07:47.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:07:47.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:07:47.534 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:07:47.535 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:07:47.535 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:07:47.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:07:47.540 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:07:48.022 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:07:48.062 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:07:48.064 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:07:48.065 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:07:48.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:48.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:48.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:48.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:48.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:48.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:48.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:48.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:48.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:48.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:48.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:48.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:48.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:48.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:48.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:48.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:48.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:48.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:48.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:48.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:48.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:48.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:48.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:48.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:48.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:48.500 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:07:48.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:48.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:48.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:48.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:48.978 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:07:49.455 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:07:49.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:49.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:49.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:49.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:49.933 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:07:50.410 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:07:50.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:50.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:50.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:50.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:50.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:50.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:50.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:50.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:50.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:50.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:50.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:50.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:50.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:50.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:50.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:50.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:50.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:50.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:50.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:50.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:50.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:50.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:50.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:50.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:50.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:50.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:50.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:50.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:50.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:50.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:50.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:50.888 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:07:51.365 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:07:51.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:51.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:51.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:51.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:51.843 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:07:52.320 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:07:52.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:07:52.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:07:52.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:07:52.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:07:52.798 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:07:52.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:52.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:52.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:52.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:52.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:52.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:52.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:52.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:52.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:52.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:52.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:52.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:52.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:52.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:52.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:52.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:52.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:53.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:53.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:53.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:53.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:53.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:53.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:53.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:53.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:53.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:53.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:53.235 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:53.235 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:53.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:53.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:53.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:53.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:53.275 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:07:53.752 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:07:54.231 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:07:54.709 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:07:55.187 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:07:55.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:55.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:55.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:55.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:55.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:55.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:55.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:55.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:55.591 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:55.591 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:55.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:55.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:55.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:55.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.664 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:07:55.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:55.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:55.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:55.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:55.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:55.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:55.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:55.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:55.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:55.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:55.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:55.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:55.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:55.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:55.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:56.141 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:07:56.619 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:07:57.096 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:07:57.574 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:07:57.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:58.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:58.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:58.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:58.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:58.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:58.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:58.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:58.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:58.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:58.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:58.051 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:07:58.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:58.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:58.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.529 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:07:58.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:58.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:58.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:58.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:07:58.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:07:58.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:07:58.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:58.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:58.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:07:58.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:07:58.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:07:58.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:07:58.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:07:58.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:58.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:07:59.005 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:07:59.484 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:07:59.961 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:08:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:00.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:00.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:00.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:00.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:00.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:00.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:00.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:00.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:00.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:00.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:00.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:00.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:00.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:00.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:00.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:00.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:00.438 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:08:00.916 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:08:01.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:01.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:01.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:01.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:01.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:01.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:01.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:01.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:01.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:01.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:01.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:01.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:01.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:01.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:01.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:01.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:01.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:01.393 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:08:01.871 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:08:02.349 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:08:02.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:02.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:02.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:02.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:02.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:02.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:02.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:02.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:02.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:02.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:02.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:02.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:02.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:02.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:02.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:02.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:02.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:02.825 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:08:03.302 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:08:03.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:03.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:03.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:03.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:03.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:03.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:03.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:03.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:03.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:03.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:03.408 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:03.408 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:03.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:03.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:03.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:03.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:03.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:03.780 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:08:04.257 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:08:04.735 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:08:05.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:05.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:05.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:05.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:05.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:05.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:05.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:05.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:05.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:05.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:05.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:05.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:05.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:05.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.212 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:08:05.690 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:08:05.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:05.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:05.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:05.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:05.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:05.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:05.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:05.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:05.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:05.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:05.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:05.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:05.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:05.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:05.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:06.167 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:08:06.645 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:08:07.122 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:08:07.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:07.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:07.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:07.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:07.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:07.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:07.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:07.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:07.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:07.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:07.531 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:07.531 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:07.531 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:07.531 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:07.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4271 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4271 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:07.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4272 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:12.532 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:12.532 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:12.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:12.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:12.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:12.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:12.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:12.547 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:12.547 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:12.547 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:12.547 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:08:12.549 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:08:12.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:08:12.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:12.550 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:12.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:12.551 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:08:12.551 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:12.551 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:08:12.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:12.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:08:12.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:08:12.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:12.553 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:12.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:12.553 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:08:12.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:12.553 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:08:12.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:12.555 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:08:12.555 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:08:12.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:12.556 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:12.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:12.556 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:08:12.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:12.557 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:08:12.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:08:12.560 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:08:12.560 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:08:12.560 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:12.565 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:08:13.046 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:08:13.091 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:08:13.093 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:08:13.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.095 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:08:13.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:13.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:13.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:13.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:13.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.227 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:13.227 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:13.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:13.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:13.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:13.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.521 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:08:13.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:13.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:13.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:13.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:13.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:13.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:13.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:13.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:13.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:13.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:13.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:13.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:13.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:13.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:13.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:13.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:13.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:13.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:13.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:13.997 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:08:14.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:14.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:14.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:14.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:14.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:14.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:14.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:14.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:14.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:14.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:14.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:14.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:14.243 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:14.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:14.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:14.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:14.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:14.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:14.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:14.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:14.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:14.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:14.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:14.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:14.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:14.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:14.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.474 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:08:14.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:14.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:14.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:14.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:14.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:14.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:14.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:14.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:14.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:14.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:14.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:14.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:14.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:14.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:14.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:14.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:14.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:14.574 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:14.574 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=431 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:19.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:19.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:19.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:19.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:19.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:19.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:19.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:19.588 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:19.589 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:19.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:19.589 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:08:19.594 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:08:19.595 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:08:19.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:19.595 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:19.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:19.595 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:08:19.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:19.596 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:08:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:19.598 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:08:19.599 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:08:19.599 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:19.599 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:19.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:19.599 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:08:19.599 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:19.599 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:08:19.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:19.602 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:19.602 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:08:19.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:19.605 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.606 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:08:19.606 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:08:19.606 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:19.611 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:08:20.095 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:08:20.138 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:08:20.140 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:08:20.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:20.142 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:08:20.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:20.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:20.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:20.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:20.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:20.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:20.173 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:20.173 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:20.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:20.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:20.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:20.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:20.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:20.573 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:08:20.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:20.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:20.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:20.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:21.051 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:08:21.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:21.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:21.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:21.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:21.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:21.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:21.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:21.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:21.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:21.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:21.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:21.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:21.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:21.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.528 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:08:21.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:21.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:21.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:21.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:21.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:21.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:21.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:21.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:21.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:21.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:21.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:21.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:21.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:21.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:21.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:21.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:21.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:21.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:21.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.005 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:08:22.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:22.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:22.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:22.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:22.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:22.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:22.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:22.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:22.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:22.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:22.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:22.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:22.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:22.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.483 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:08:22.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:22.619 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:22.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:22.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:22.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:22.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:22.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:22.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:22.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:22.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:22.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:22.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:22.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:22.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:22.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:22.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:22.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:22.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:22.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:22.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:22.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:22.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:22.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:22.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:22.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:22.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:22.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:22.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:22.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:22.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:22.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:22.961 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:08:23.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:23.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:23.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:23.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:23.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:23.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:23.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:23.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:23.403 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:23.403 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:23.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:23.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:23.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:23.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.437 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:08:23.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:23.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:23.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:23.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:23.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:23.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:23.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:23.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:23.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:23.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:23.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:23.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:23.846 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:23.846 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:23.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:23.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:23.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:23.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:23.915 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:08:24.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:24.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:24.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:24.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:24.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:24.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:24.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:24.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:24.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:24.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:24.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:24.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:24.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:24.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:24.323 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:24.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:24.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:24.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:24.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:24.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:24.323 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:29.322 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:29.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:29.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:29.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:29.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:29.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:29.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:29.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:29.331 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:29.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:29.331 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:08:29.334 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:08:29.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:08:29.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:29.335 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:29.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:29.335 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:08:29.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:29.335 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:08:29.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:29.337 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:08:29.337 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:08:29.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:29.338 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:29.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:29.338 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:08:29.338 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:29.338 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:08:29.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:29.340 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:29.340 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:08:29.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:08:29.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:08:29.344 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:08:29.344 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:08:29.344 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:29.349 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:08:29.831 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:08:29.876 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:08:29.877 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:08:29.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:29.878 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:08:29.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:29.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:29.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:29.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:29.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:29.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:29.902 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:29.902 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:29.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:29.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:29.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:29.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:29.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:29.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:29.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:29.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:29.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.012 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.012 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.305 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:08:30.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:30.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:30.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:30.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:30.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.394 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.394 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.780 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:08:30.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:30.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:30.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:30.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:30.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:30.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:30.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:30.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:30.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:30.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:31.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:31.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:31.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:31.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:31.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:31.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:31.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:31.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:31.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:31.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:31.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:31.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:31.180 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:31.180 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:31.180 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:36.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:36.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:36.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:36.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:36.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:36.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:36.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:36.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:36.197 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:36.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:36.198 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:08:36.202 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:08:36.202 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:08:36.203 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:36.203 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:36.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:36.204 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:08:36.204 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:36.205 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:08:36.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:36.206 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:08:36.206 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:08:36.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:36.206 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:36.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:36.207 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:08:36.207 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:36.207 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:08:36.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:36.209 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:08:36.209 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:08:36.209 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:36.209 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:36.210 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:36.210 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:08:36.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:36.210 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:08:36.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:08:36.214 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:08:36.214 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:08:36.214 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:08:36.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:36.219 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:08:36.703 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:08:36.741 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:08:36.744 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:08:36.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:36.745 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:08:36.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:36.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:36.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:36.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:36.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:36.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:36.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:36.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:36.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:36.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:36.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:36.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:36.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:37.180 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:08:37.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:37.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:37.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:37.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:37.658 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:08:37.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:37.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:37.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:37.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:37.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:37.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:37.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:37.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:37.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:37.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:37.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:37.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:37.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:37.762 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:37.762 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:37.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:37.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:38.140 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:08:38.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:38.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:38.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:38.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:38.617 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:08:38.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:38.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:38.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:38.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:38.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:38.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:38.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:38.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:38.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:38.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:38.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:38.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:38.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:38.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:38.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:38.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:38.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:39.094 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:08:39.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:39.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:39.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:39.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:39.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:08:39.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:39.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:39.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:39.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:39.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:39.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:39.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:39.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:39.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:39.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:39.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:39.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:39.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:39.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:39.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:39.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:39.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:40.044 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:08:40.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:40.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:40.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:40.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:40.522 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:08:40.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:40.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:40.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:40.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:40.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:40.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:40.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:40.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:40.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:40.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:40.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:40.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:40.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:40.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:40.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:40.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:40.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:40.999 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:08:41.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:41.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:41.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:41.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:41.477 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:08:41.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:41.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:41.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:41.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:41.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:41.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:41.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:41.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:41.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:41.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:41.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:41.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:41.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:41.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:41.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:41.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:41.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:41.954 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:08:42.432 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:08:42.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:42.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:42.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:42.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:42.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:42.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:42.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:42.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:42.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:42.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:42.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:42.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:42.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:42.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:42.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:42.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:42.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:42.904 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:08:43.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:43.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:43.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:43.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:43.377 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:08:43.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:43.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:43.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:43.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:43.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:43.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:43.382 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:43.382 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:43.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:43.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:43.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:43.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:43.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:43.853 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:08:44.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:44.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:44.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:44.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:44.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:44.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:44.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:44.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:44.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:44.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:44.330 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:44.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:44.330 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:49.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:49.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:49.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:49.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:49.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:49.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:49.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:49.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:49.345 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:49.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:49.345 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:08:49.347 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:08:49.348 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:08:49.348 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:49.348 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:49.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:49.349 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:08:49.349 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:49.349 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:08:49.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:49.349 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:08:49.350 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:08:49.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:49.350 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:49.350 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:49.350 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:08:49.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:49.350 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:08:49.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:49.351 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:08:49.352 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:08:49.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:49.352 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:49.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:49.352 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:08:49.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:49.352 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:08:49.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.354 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:08:49.354 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:08:49.354 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:08:49.355 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:49.359 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:08:49.842 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:08:49.881 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:08:49.882 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:08:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:49.883 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:08:49.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:49.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:49.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:49.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:49.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:49.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:49.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:49.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:49.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:49.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:49.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:49.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:49.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:50.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:50.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:50.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:50.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:50.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:50.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:50.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:50.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:50.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:50.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:50.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:50.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:50.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:50.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.317 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:08:50.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:50.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:50.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:50.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:50.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:50.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:50.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:50.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:50.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:50.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:50.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:50.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.795 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:08:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:50.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:50.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:50.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:50.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:50.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:50.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:50.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:50.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:50.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:50.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:50.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:50.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:50.968 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:50.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:50.969 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:55.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:55.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:55.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:55.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:55.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:55.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:55.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:55.980 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:55.980 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:55.980 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:08:55.981 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:08:55.984 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:08:55.984 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:08:55.984 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:55.984 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:55.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:55.985 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:08:55.985 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:08:55.985 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:08:55.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:55.987 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:08:55.987 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:08:55.987 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:55.988 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:55.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:55.988 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:08:55.988 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:08:55.988 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:08:55.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:55.990 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:08:55.990 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:08:55.990 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:55.990 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:08:55.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:55.990 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:08:55.990 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:08:55.990 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:08:55.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.993 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:08:55.994 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:08:55.994 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:08:55.994 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:08:55.999 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:08:56.482 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:08:56.525 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:08:56.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:56.529 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:08:56.531 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:08:56.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:56.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:56.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:56.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:56.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:56.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:56.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:56.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:56.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:56.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:56.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:56.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:56.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:56.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:56.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:56.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:56.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:56.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:56.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:56.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:56.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:56.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:56.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:56.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:56.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:56.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:56.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:56.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:56.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:56.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:56.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:56.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:56.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:56.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:56.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:56.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:56.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:56.958 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:08:56.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:56.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:56.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:57.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:57.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:57.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:57.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:57.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:57.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:57.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:08:57.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:57.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:57.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:57.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:08:57.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:08:57.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:57.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:08:57.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:08:57.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:57.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:57.432 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:08:57.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:08:57.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:08:57.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:08:57.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:08:57.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:08:57.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:08:57.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:08:57.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:08:57.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:08:57.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:08:57.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:08:57.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:08:57.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:08:57.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:08:57.599 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:08:57.599 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:57.599 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:57.599 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:57.599 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:57.599 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:08:57.599 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:02.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:02.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:02.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:02.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:02.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:02.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:02.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:02.608 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:02.609 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:02.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:02.609 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:02.613 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:02.613 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:02.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:02.614 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:02.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:02.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:02.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:02.615 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:02.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:02.615 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:02.616 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:02.616 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:02.616 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:02.616 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:02.616 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:02.616 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:02.616 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:02.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:02.618 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:02.618 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:02.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:02.622 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:02.622 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:02.622 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:02.627 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:03.110 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:03.152 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:03.154 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:03.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.157 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:03.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:03.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:03.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:03.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:03.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:03.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:03.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:03.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:03.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.584 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:09:03.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:03.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:03.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:03.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:03.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:03.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:03.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:03.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:03.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:03.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:03.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:03.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:03.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:03.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:03.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:03.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:03.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:03.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:03.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:03.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:03.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:03.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:03.985 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:03.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:03.985 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.985 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.986 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.986 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.986 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.986 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.986 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:03.986 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:08.987 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:08.987 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:08.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:08.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:08.991 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:08.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:09.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:09.001 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:09.001 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:09.002 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:09.002 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:09.005 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:09.005 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:09.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:09.006 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:09.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:09.007 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:09.007 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:09.007 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:09.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:09.008 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:09.008 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:09.008 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:09.008 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:09.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:09.009 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:09.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:09.009 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:09.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:09.010 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:09.011 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:09.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:09.011 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:09.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:09.011 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:09.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:09.011 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:09.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.014 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:09.014 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:09.014 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:09.014 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:09.019 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:09.545 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:09.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:09.548 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:09.550 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:09.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:09.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:09.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:09.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:09.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:09.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:09.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:09.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:09.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:09.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:09.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:09.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:09.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:09.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:09.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:09.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:09.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:09.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:09.726 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:09.726 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:09.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:09.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:09.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:09.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:09.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:09.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:09.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:09.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:09.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:09.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:09.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:09.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:09.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:09.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:09.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:09.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:09.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:09.977 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:09:10.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:10.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:10.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:10.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:10.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:10.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:10.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:10.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:10.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:10.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:10.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:10.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:10.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:10.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:10.226 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:10.226 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:10.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:10.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:10.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:10.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:10.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:10.454 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:09:10.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:10.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:10.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:10.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:10.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:10.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:10.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:10.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:10.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:10.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:10.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:10.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:10.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:10.625 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:10.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:10.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:10.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:15.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:15.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:15.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:15.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:15.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:15.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:15.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:15.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:15.641 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:15.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:15.642 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:15.645 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:15.645 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:15.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:15.646 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:15.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:15.646 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:15.647 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:15.647 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:15.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:15.648 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:15.649 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:15.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:15.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:15.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:15.649 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:15.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:15.650 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:15.650 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:15.651 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:15.651 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:15.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:15.651 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:15.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:15.652 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:15.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:15.652 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:15.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:15.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:15.656 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:15.656 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:15.656 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:15.661 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:16.144 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:16.178 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:16.179 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:16.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:16.181 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:16.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:16.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:16.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:16.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:16.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:16.208 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:16.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:16.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:16.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:16.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:16.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:16.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:16.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:16.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:16.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:16.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:16.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:16.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:16.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:16.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:16.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:16.621 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:09:16.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:16.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:16.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:16.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:16.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:16.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:16.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:17.099 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:09:17.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:17.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:17.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:17.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:17.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:17.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:17.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:17.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:17.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:17.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:17.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:17.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:17.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:17.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:17.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:17.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:17.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:17.576 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:09:17.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:17.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:17.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:17.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:18.054 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:09:18.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:18.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:18.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:18.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:18.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:18.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:18.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:18.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:18.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:18.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:18.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:18.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:18.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:18.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:18.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:18.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:18.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:18.531 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:09:18.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:18.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:18.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:18.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:19.009 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:09:19.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:19.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:19.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:19.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:19.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:19.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:19.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:19.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:19.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:19.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:19.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:19.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:19.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:19.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:19.337 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:19.337 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:24.339 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:24.340 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:24.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:24.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:24.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:24.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:24.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:24.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:24.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:24.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:24.350 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:24.352 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:24.352 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:24.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:24.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:24.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:24.353 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:24.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:24.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:24.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:24.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:24.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:24.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:24.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:24.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:24.355 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:24.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:24.355 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:24.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:24.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:24.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:24.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:24.357 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:24.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:24.357 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:24.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:24.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:24.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:24.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:24.360 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:24.360 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:24.360 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:24.365 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:24.850 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:24.890 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:24.892 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:24.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:24.895 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:24.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:24.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:24.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:24.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:24.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:24.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:24.924 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:24.924 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:24.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:24.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:24.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:24.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:24.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:25.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:25.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:25.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:25.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:25.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:25.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:25.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:25.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:25.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:25.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:25.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:25.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:25.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.327 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:09:25.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:25.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:25.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:25.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:25.805 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:09:25.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:25.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:25.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:25.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:25.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:25.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:25.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:25.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:25.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:25.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:25.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:25.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:25.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:25.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:25.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:26.282 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:09:26.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:26.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:26.384 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:26.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:26.760 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:09:26.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:26.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:26.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:26.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:26.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:26.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:26.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:26.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:26.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:26.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:26.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:26.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:26.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:26.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:26.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:26.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:26.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:27.237 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:09:27.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:27.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:27.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:27.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:27.716 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:09:28.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:28.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:28.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:28.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:28.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:28.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:28.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:28.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:28.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:28.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:28.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:28.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:28.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:28.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:28.052 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:28.053 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:28.053 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:28.053 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:28.053 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:28.053 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:28.053 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:33.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:33.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:33.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:33.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:33.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:33.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:33.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:33.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:33.064 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:33.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:33.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:33.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:33.069 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:33.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:33.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:33.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:33.070 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:33.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:33.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:33.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:33.072 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:33.072 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:33.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:33.073 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:33.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:33.073 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:33.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:33.073 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:33.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:33.075 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:33.075 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:33.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:33.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:33.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:33.076 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:33.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:33.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:33.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:33.079 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:33.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:33.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:33.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:33.079 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:33.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:33.080 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:33.080 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:33.080 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:33.085 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:33.570 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:33.605 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:33.606 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:33.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:33.607 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:33.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:33.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:33.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:33.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:33.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:33.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:33.626 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:33.626 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:33.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:33.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:33.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:33.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:33.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:33.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:33.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:33.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:33.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:34.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:34.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:34.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:34.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:34.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:34.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:34.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:34.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:34.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:34.047 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:09:34.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:34.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:34.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:34.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:34.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:34.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:34.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:34.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:34.525 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:09:34.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:34.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:34.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:34.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:34.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:34.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:34.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:34.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:34.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:34.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:34.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:34.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:34.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:34.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:34.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:34.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:34.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:35.002 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:09:35.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:35.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:35.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:35.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:35.480 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:09:35.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:35.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:35.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:35.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:35.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:35.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:35.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:35.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:35.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:35.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:35.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:35.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:35.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:35.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:35.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:35.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:35.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:35.958 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:09:36.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:36.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:36.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:36.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:36.435 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:09:36.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:36.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:36.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:36.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:36.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:36.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:36.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:36.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:36.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:36.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:36.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:36.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:36.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:36.770 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:36.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:36.770 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:36.770 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:36.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:36.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:36.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:36.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:36.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:41.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:41.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:41.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:41.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:41.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:41.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:41.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:41.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:41.781 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:41.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:41.781 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:41.785 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:41.785 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:41.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:41.786 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:41.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:41.787 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:41.787 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:41.787 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:41.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:41.788 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:41.788 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:41.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:41.790 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:41.790 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:41.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:41.790 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:41.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:41.791 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:41.791 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:41.791 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:41.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:41.793 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:41.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:41.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:41.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:41.793 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:41.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:41.794 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:41.794 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:41.794 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:41.799 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:42.282 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:42.324 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:42.326 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:42.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:42.327 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:42.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:42.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:42.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:42.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:42.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:42.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:42.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:42.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:42.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:42.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:42.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:42.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:42.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:42.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:42.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:42.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:42.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:42.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:42.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:42.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:42.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:42.758 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:09:42.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:42.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:42.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:42.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:42.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:42.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:42.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:43.235 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:09:43.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:43.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:43.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:43.243 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:43.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:43.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:43.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:43.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:43.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:43.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:43.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:43.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:43.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:43.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:43.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:43.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:43.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:43.713 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:09:43.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:43.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:43.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:43.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:44.190 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:09:44.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:44.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:44.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:44.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:44.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:44.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:44.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:44.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:44.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:44.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:44.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:09:44.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:09:44.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:44.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:09:44.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:09:44.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:44.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:44.666 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:09:44.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:44.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:44.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:44.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:45.144 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:09:45.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:45.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:09:45.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:45.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:45.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:45.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:45.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:45.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:45.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:45.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:45.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:45.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:45.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:45.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:45.478 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:50.481 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:50.481 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:50.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:50.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:50.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:50.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:50.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:50.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:50.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:50.493 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:50.493 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:50.497 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:50.497 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:50.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:50.498 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:50.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:50.499 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:50.499 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:50.499 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:50.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:50.501 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:50.501 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:50.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:50.501 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:50.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:50.502 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:50.502 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:50.502 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:50.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:50.503 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:50.503 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:50.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:50.504 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:50.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:50.504 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:50.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:50.504 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:50.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:50.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:50.508 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:50.508 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:50.508 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:50.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:50.513 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:50.996 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:51.043 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:51.045 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:51.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:51.047 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:51.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:51.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:51.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:51.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:51.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:51.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:51.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:51.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:51.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:51.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:51.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:51.095 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:51.095 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:51.095 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:51.095 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:09:56.095 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:56.095 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:56.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:56.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:56.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:56.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:56.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:56.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:56.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:56.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:09:56.110 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:09:56.113 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:09:56.113 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:09:56.113 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:56.114 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:56.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:56.114 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:09:56.115 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:09:56.115 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:09:56.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:56.116 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:09:56.116 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:09:56.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:56.116 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:56.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:56.116 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:09:56.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:09:56.116 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:09:56.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:56.118 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:09:56.118 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:09:56.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:56.118 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:09:56.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:56.119 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:09:56.119 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:09:56.119 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:09:56.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:56.121 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:09:56.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:09:56.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:09:56.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:09:56.121 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:09:56.122 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:09:56.122 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:09:56.122 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:09:56.127 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:09:56.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:09:56.654 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:09:56.656 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:09:56.658 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:09:56.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:56.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:56.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:56.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:56.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:09:56.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:09:56.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:09:56.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:09:56.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:09:56.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:09:56.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:09:56.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:09:56.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:09:56.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:09:56.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:09:56.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:09:56.716 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:09:56.716 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:09:56.716 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:10:01.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:01.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:01.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:01.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:01.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:01.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:01.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:01.726 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:01.726 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:01.726 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:01.726 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:10:01.728 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:10:01.728 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:10:01.728 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:01.728 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:01.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:01.729 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:10:01.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:01.729 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:10:01.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:01.730 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:01.730 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:10:01.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:01.731 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:10:01.731 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:10:01.731 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:01.731 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:01.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:01.732 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:10:01.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:01.732 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:10:01.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:10:01.734 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:10:01.734 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:10:01.734 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:10:01.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:01.739 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:10:02.222 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:10:02.257 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:10:02.258 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:10:02.259 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:10:02.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:02.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:02.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:02.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:02.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:02.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:02.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:02.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:02.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:02.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:02.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:02.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:02.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:02.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:02.285 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:02.285 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:07.287 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:07.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:07.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:07.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:07.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:07.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:07.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:07.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:07.299 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:07.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:07.299 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:10:07.299 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:10:07.299 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:10:07.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:07.300 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:07.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:07.300 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:10:07.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:07.300 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:10:07.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:07.301 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:07.301 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:10:07.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:07.303 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:07.303 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:10:07.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:10:07.307 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:10:07.307 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:10:07.307 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:10:07.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:07.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:07.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:07.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:07.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:07.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:07.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:07.309 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:10:12.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:12.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:12.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:12.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:12.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:12.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:12.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:12.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:12.327 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:12.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:12.327 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:10:12.330 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:10:12.330 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:10:12.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:12.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:12.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:12.331 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:10:12.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:12.331 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:12.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:12.332 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:10:12.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:12.334 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:12.334 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:10:12.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:10:12.337 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:10:12.337 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:10:12.337 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:12.342 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:10:12.826 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:10:12.857 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:10:12.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:12.860 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:10:12.862 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:10:12.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:12.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:12.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:12.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:12.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:12.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:12.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:12.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:12.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:12.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:12.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:12.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:12.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:13.303 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:10:13.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:13.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:13.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:13.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:13.781 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:10:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:13.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:13.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:13.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:13.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:13.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:13.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:13.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:13.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:13.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:13.915 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:13.915 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:13.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:13.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:13.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:13.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:13.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:14.257 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:10:14.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:14.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:14.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:14.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:14.735 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:10:14.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:14.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:14.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:14.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:14.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:14.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:14.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:14.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:14.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:14.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:14.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:14.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:14.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:14.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:14.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:14.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:15.212 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:10:15.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:15.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:15.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:15.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:15.689 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:10:15.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:15.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:15.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:15.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:15.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:15.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:15.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:15.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:15.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:15.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:15.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:15.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:15.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:15.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:15.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:15.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:15.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:16.166 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:10:16.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:16.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:16.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:16.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:16.644 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:10:16.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:16.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:16.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:16.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:16.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:16.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:16.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:16.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:16.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:16.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:16.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:16.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:16.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:16.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:16.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:16.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:16.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:17.122 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:10:17.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:17.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:17.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:17.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:17.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:17.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:17.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:17.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:17.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:17.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:17.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:17.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:17.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:17.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:17.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:17.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:17.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:17.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:17.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:17.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:17.599 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:10:18.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:18.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:18.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:18.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:18.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:18.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:18.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:18.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:18.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:18.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:18.076 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:10:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:18.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:18.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:18.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.554 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:10:18.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:18.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:18.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:18.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:18.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:18.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:18.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:18.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:18.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:18.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:18.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:18.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:18.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:18.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:18.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:18.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:19.032 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:10:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:19.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:19.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:19.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:19.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:19.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:19.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:19.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:19.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:19.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:19.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:19.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:19.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:19.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:19.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:19.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:19.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:19.509 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:10:19.987 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:10:20.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:20.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:20.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:20.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:20.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:20.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:20.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:20.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:20.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:20.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:20.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:20.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:20.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:20.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:20.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.464 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:10:20.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:20.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:20.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:20.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:20.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:20.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:20.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:20.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:20.652 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:20.652 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:20.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:20.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:20.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:20.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:20.940 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:10:21.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:21.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:21.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:21.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:21.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:21.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:21.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:21.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:21.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:21.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:21.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:21.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:21.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:21.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:21.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:21.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:21.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:21.417 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:10:21.894 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:10:21.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:21.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:21.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:21.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:22.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:22.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:22.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:22.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:22.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:22.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:22.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:22.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:22.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:22.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:22.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:22.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:22.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:22.371 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:10:22.849 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:10:22.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:22.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:22.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:22.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:22.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:22.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:22.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:22.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:22.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:22.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:22.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:22.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:22.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:22.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:22.900 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:22.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:22.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:23.327 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:10:23.804 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:10:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:23.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:23.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:23.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:23.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:23.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:23.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:23.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:23.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:23.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:23.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:23.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:23.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:23.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:23.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:23.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:23.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:24.281 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:10:24.759 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:10:24.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:24.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:24.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:24.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:24.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:24.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:24.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:24.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:24.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:24.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:24.818 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:24.818 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:24.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:24.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:24.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:24.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:24.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:25.236 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:10:25.714 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:10:25.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:25.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:25.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:25.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:25.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:25.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:25.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:25.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:25.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:25.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:25.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:25.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:25.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:25.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:25.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:25.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:25.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:26.191 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:10:26.670 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:10:26.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:26.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:26.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:26.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:26.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:26.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:26.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:26.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:26.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:26.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:26.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:26.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:26.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:26.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:26.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:26.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:26.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:27.148 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:10:27.626 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:10:27.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:27.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:27.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:27.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:27.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:27.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:27.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:27.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:27.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:27.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:27.772 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:27.772 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:27.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:27.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:27.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:27.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:27.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:28.103 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:10:28.581 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:10:28.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:28.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:28.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:28.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:28.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:28.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:28.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:28.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:28.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:28.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:28.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:28.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:28.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:28.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:28.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:28.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:28.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:29.058 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:10:29.536 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:10:29.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:29.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:29.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:29.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:29.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:29.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:29.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:29.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:29.686 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:29.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:29.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:29.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:29.686 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:29.686 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:29.686 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:10:34.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:34.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:34.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:34.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:34.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:34.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:34.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:34.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:34.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:34.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:34.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:10:34.707 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:10:34.708 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:10:34.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:34.708 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:34.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:34.708 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:10:34.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:34.709 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:10:34.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:34.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:34.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:10:34.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:34.711 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:34.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:10:34.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.713 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:10:34.713 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:10:34.713 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:10:34.714 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:34.718 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:10:35.200 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:10:35.234 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:10:35.234 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:10:35.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:35.236 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:10:35.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:35.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:35.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:35.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:35.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:35.263 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:35.263 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:35.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:35.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:35.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:35.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:35.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:35.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:35.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:35.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:35.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:35.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.559 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:35.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:35.559 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:35.559 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:35.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:35.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:35.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:35.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.677 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:10:35.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:35.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:35.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:35.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:35.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:35.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:35.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:35.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:35.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:35.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:35.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:35.819 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:35.819 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:35.819 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:35.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:35.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:35.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:35.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:35.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:36.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:36.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:36.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:36.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:36.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:36.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:36.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:10:36.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:36.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:36.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:36.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:10:36.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:10:36.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:36.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:10:36.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:10:36.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:36.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:36.154 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:10:36.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:10:36.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:10:36.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:10:36.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:10:36.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:36.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:36.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:36.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:36.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:36.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:36.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:36.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:36.342 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:10:36.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:36.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:36.342 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:10:41.339 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:10:41.339 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:10:41.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:41.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:41.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:41.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:41.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:10:41.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:41.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:41.351 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:10:41.351 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:10:41.353 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:10:41.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:10:41.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:41.354 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:41.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:10:41.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:10:41.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:10:41.355 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:10:41.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:10:41.355 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:10:41.355 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:10:41.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:41.356 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:41.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:10:41.356 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:10:41.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:10:41.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:10:41.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:10:41.357 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:10:41.357 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:10:41.358 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:41.358 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:10:41.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:10:41.358 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:10:41.358 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:10:41.358 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:10:41.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:10:41.360 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:10:41.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:10:41.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:10:41.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:10:41.360 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:10:41.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:10:41.361 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:10:41.361 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:10:41.361 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:10:41.366 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:10:41.849 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:10:42.330 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:10:42.811 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:10:43.293 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:10:43.774 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:10:44.255 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:10:44.737 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:10:45.220 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:10:45.701 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:10:46.182 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:10:46.663 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:10:47.145 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:10:47.626 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:10:48.104 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:10:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:10:49.066 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:10:49.547 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:10:50.028 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:10:50.510 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:10:50.991 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:10:51.472 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:10:51.953 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:10:52.434 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:10:52.915 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:10:53.396 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:10:53.874 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:10:54.354 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:10:54.834 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:10:55.315 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:10:55.796 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:10:56.274 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:10:56.755 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:10:57.235 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:10:57.713 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:10:58.191 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:10:58.671 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:10:59.153 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:10:59.633 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:11:00.112 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:11:00.592 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:11:01.073 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:11:01.554 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:11:02.035 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:11:02.516 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:11:02.996 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:11:03.474 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:11:03.952 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:11:04.431 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:11:04.906 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:11:05.374 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:11:05.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:11:05.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:11:05.396 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:11:05.396 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:11:05.396 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:11:05.396 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:11:05.396 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:05.397 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5107 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:10.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:11:10.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:11:10.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:11:10.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:11:10.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:11:10.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:11:10.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:11:10.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:11:10.411 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:10.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:11:10.411 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:11:10.417 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:11:10.417 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:11:10.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:11:10.417 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:10.418 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:11:10.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:11:10.418 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:11:10.418 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:11:10.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:11:10.421 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:11:10.422 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:11:10.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:11:10.422 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:10.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:11:10.422 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:11:10.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:11:10.422 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:11:10.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:11:10.425 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:11:10.425 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:11:10.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:11:10.430 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:11:10.430 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:11:10.430 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:10.435 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:11:10.916 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:11:11.397 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:11:11.878 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:11:12.359 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:11:12.841 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:11:13.320 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:11:13.802 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:11:14.284 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:11:14.765 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:11:15.246 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:11:15.728 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:11:16.209 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:11:16.690 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:11:17.171 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:11:17.652 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:11:18.133 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:11:18.615 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:11:19.096 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:11:19.578 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:11:20.060 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:11:20.541 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:11:21.022 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:11:21.503 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:11:21.984 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:11:22.466 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:11:22.946 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:11:23.423 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:11:23.901 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:11:24.379 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:11:24.857 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:11:25.339 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:11:25.819 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:11:26.297 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:11:26.778 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:11:27.260 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:11:27.741 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:11:28.219 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:11:28.697 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:11:29.178 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:11:29.659 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:11:30.139 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:11:30.620 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:11:31.101 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:11:31.581 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:11:32.059 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:11:32.537 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:11:33.006 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:11:33.477 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:11:33.958 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:11:34.439 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:11:34.921 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:11:35.402 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:11:35.883 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:11:36.364 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:11:36.845 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:11:37.327 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:11:37.808 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:11:38.288 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:11:38.766 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:11:39.245 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:11:39.727 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:11:40.208 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:11:40.689 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:11:41.170 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:11:41.651 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:11:42.132 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:11:42.611 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:11:43.091 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:11:43.570 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:11:44.048 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:11:44.525 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:11:45.003 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:11:45.484 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:11:45.965 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:11:46.446 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:11:46.915 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:11:47.384 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:11:47.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:47.863 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:11:48.369 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:11:48.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:48.849 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:11:49.318 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:11:49.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:49.789 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:11:50.271 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:11:50.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:50.753 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:11:51.234 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:11:51.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:51.716 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:11:52.197 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:11:52.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:52.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:11:52.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:11:52.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:11:52.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:11:52.471 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:11:52.471 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:11:52.471 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:11:52.472 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8935 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:52.472 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8935 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:52.472 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8935 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:52.472 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8935 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:52.472 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8935 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:52.472 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8935 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:11:57.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:11:57.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:11:57.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:11:57.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:11:57.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:11:57.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:11:57.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:11:57.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:11:57.485 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:57.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:11:57.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:11:57.487 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:11:57.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:11:57.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:11:57.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:57.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:11:57.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:11:57.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:11:57.490 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:11:57.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:11:57.491 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:11:57.491 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:11:57.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:11:57.492 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:57.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:11:57.492 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:11:57.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:11:57.492 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:11:57.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:11:57.494 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:11:57.494 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:11:57.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:11:57.494 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:11:57.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:11:57.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:11:57.495 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:11:57.495 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:11:57.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:11:57.499 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:11:57.499 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:11:57.499 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:11:57.504 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:11:57.986 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:11:58.037 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:11:58.039 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:11:58.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:11:58.041 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:11:58.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:11:58.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:11:58.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:11:58.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:11:58.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:11:58.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:11:58.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:11:58.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:11:58.125 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:11:58.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:11:58.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:11:58.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:11:58.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:11:58.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:11:58.463 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:11:58.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:58.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:11:58.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:11:58.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:11:58.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:11:59.418 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:11:59.443 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:11:59.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:11:59.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:11:59.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:11:59.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:11:59.896 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:12:00.375 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:12:00.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:00.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:00.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:00.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:00.853 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:12:01.330 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:12:01.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:01.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:01.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:01.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:01.808 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:12:02.286 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:12:02.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:02.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:02.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:02.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:02.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:02.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:02.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:02.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:02.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:02.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:02.392 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:02.392 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:02.425 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:02.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:02.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:02.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:02.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:02.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:02.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:02.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:02.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:02.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:02.764 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:12:03.241 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:12:03.581 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:03.714 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:12:04.193 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:12:04.671 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:12:05.149 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:12:05.627 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:12:06.105 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:12:06.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:06.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:06.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:06.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:06.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:06.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:06.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:06.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:06.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:06.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:06.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:06.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:06.575 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:06.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:06.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:06.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:06.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:06.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:06.581 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:12:07.017 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:07.058 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:12:07.535 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:12:08.013 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:12:08.490 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:12:08.968 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:12:09.445 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:12:09.923 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:12:10.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:10.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:10.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:10.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:10.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:10.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:10.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:10.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:10.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:10.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:10.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:10.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:10.390 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:10.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:10.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:10.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:10.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:10.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:10.400 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:12:10.877 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:12:11.267 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:11.356 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:12:11.746 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:11.833 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:12:12.311 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:12:12.701 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:12.789 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:12:13.266 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:12:13.744 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:12:14.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:14.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:14.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:14.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:14.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:14.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:14.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:14.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:14.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:12:14.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:12:14.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:12:14.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:12:14.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:12:14.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:12:14.152 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:14.152 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3558 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:19.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:12:19.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:12:19.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:12:19.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:12:19.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:12:19.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:12:19.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:12:19.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:12:19.163 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:19.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:12:19.164 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:12:19.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:12:19.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:12:19.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:12:19.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:19.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:12:19.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:12:19.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:12:19.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:12:19.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:19.168 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:12:19.168 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:12:19.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:12:19.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:19.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:12:19.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:12:19.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:12:19.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:12:19.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:12:19.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:12:19.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:12:19.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:12:19.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:12:19.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:12:19.174 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:12:19.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:19.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:19.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:19.179 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:12:19.663 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:12:19.704 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:12:19.706 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:19.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:19.709 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:12:19.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:19.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:19.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:19.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:19.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:19.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:19.746 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:19.746 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:19.755 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:19.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:19.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:19.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:19.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:19.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:20.136 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:12:20.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:20.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:20.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:20.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:20.615 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:12:20.631 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:20.634 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:21.092 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:12:21.117 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:21.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:21.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:21.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:21.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:21.570 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:12:21.604 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:22.048 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:12:22.092 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:22.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:22.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:22.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:22.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:22.526 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:12:22.579 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:23.004 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:12:23.066 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:23.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:23.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:23.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:23.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:23.481 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:12:23.553 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:23.959 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:12:24.040 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:24.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:24.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:24.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:24.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:24.437 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:12:24.527 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:24.915 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:12:25.014 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:25.392 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:12:25.500 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:25.870 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:12:25.988 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:26.348 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:12:26.475 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:26.825 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:12:26.961 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:27.303 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:12:27.448 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:27.781 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:12:27.935 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:27.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:27.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:27.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:27.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:27.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:27.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:27.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:27.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:27.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:27.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:27.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:27.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:28.017 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:28.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:28.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:28.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:28.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:28.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:28.259 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:12:28.663 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:28.737 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:12:29.150 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:29.153 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:29.215 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:12:29.638 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:29.693 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:12:30.125 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:30.172 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:12:30.613 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:30.650 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:12:31.100 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:31.128 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:12:31.587 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:31.606 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:12:32.075 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:32.084 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:12:32.562 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:32.563 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:12:33.041 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:12:33.057 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:33.519 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:12:33.545 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:33.998 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:12:34.032 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:34.475 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:12:34.519 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:34.954 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:12:35.007 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:35.432 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:12:35.494 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:35.910 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:12:35.981 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:35.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:35.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:35.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:35.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:36.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:36.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:36.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:36.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:36.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:36.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:36.006 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:36.006 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:36.050 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:36.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:36.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:36.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:36.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:36.346 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:36.387 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:12:36.822 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:36.825 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:36.864 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:12:37.300 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:37.342 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:12:37.778 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:37.820 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:12:38.256 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:38.298 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:12:38.733 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:38.774 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:12:39.210 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:39.252 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:12:39.687 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:39.730 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:12:40.165 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:40.207 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:12:40.643 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:40.685 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:12:41.120 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:41.162 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:12:41.598 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:41.640 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:12:42.076 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:42.117 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:12:42.553 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:42.595 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:12:43.031 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:43.073 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:12:43.509 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:43.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:43.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:43.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:43.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:43.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:43.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:43.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:43.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:43.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:43.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:43.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:43.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:43.540 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:43.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:43.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:43.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:43.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:43.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:43.550 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:12:43.941 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:44.027 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:12:44.417 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:44.420 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:44.505 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:12:44.895 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:44.898 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:44.983 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:12:45.373 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:45.461 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:12:45.851 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:45.854 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:12:45.938 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:12:46.328 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:46.416 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:12:46.806 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:46.893 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:12:47.283 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:47.371 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:12:47.761 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:47.848 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:12:48.238 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:48.327 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:12:48.717 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:48.804 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:12:49.195 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:49.282 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:12:49.672 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:49.760 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:12:50.150 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:50.238 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:12:50.628 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:50.716 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:12:51.107 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:51.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:51.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:51.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:51.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:51.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:51.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:51.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:51.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:51.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:12:51.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:12:51.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:12:51.131 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:12:51.131 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:12:51.131 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:12:51.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:51.132 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:12:56.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:12:56.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:12:56.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:12:56.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:12:56.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:12:56.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:12:56.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:12:56.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:12:56.144 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:56.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:12:56.144 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:12:56.148 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:12:56.148 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:12:56.149 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:12:56.149 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:56.149 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:12:56.149 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:12:56.149 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:12:56.149 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:12:56.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:56.152 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:12:56.152 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:12:56.152 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:12:56.153 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:56.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:12:56.153 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:12:56.153 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:12:56.153 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:12:56.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:56.155 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:12:56.156 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:12:56.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:12:56.156 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:12:56.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:12:56.156 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:12:56.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:12:56.156 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:12:56.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:56.159 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:12:56.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:12:56.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:12:56.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.160 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:12:56.160 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:12:56.160 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:12:56.161 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:12:56.165 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:12:56.649 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:12:56.696 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:12:56.699 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:12:56.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:56.701 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:12:56.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:56.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:56.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:56.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:56.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:56.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:56.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:56.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:56.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:56.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:56.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:56.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:56.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:57.126 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:12:57.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:57.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:57.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:57.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:57.604 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:12:58.082 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:12:58.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:58.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:58.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:58.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:58.560 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:12:58.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:58.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:58.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:58.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:58.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:12:58.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:12:58.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:12:58.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:58.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:58.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:58.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:12:58.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:12:58.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:12:58.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:12:58.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:12:58.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:58.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:12:59.038 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:12:59.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:12:59.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:12:59.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:12:59.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:12:59.516 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:12:59.994 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:13:00.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:00.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:00.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:00.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:00.472 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:13:00.949 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:13:00.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:00.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:00.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:00.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:01.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:01.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:01.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:01.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:01.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:01.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:01.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:01.017 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:01.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:01.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:01.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:01.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:01.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:01.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:01.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:01.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:01.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:01.427 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:13:01.905 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:13:02.383 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:13:02.860 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:13:03.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:03.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:03.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:03.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:03.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:03.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:03.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:03.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:03.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:03.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:03.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:03.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:03.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:03.154 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:03.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:03.154 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:03.154 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:03.155 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:03.155 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:03.155 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:03.155 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:03.155 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:08.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:08.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:08.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:08.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:08.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:08.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:08.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:08.166 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:08.166 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:08.166 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:08.166 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:13:08.170 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:13:08.170 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:13:08.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:08.171 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:08.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:08.172 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:13:08.172 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:08.172 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:13:08.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:08.173 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:13:08.173 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:13:08.173 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:08.174 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:08.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:08.174 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:13:08.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:08.174 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:13:08.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:08.175 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:13:08.176 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:13:08.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:08.176 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:08.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:08.176 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:13:08.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:08.176 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:13:08.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.179 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:13:08.179 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:13:08.179 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:13:08.180 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:08.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:08.184 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:13:08.666 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:13:08.713 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:13:08.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:08.716 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:13:08.718 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:13:08.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:08.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:08.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:08.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:08.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:08.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:08.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:08.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:08.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:08.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:08.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:08.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:09.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:13:09.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:09.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:09.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:09.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:09.621 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:13:10.099 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:13:10.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:10.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:10.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:10.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:10.577 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:13:10.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:10.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:10.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:10.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:10.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:10.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:10.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:10.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:10.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:10.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:10.896 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:10.896 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:10.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:10.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:10.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:10.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:10.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:11.054 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:13:11.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:11.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:11.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:11.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:11.532 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:13:12.010 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:13:12.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:12.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:12.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:12.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:12.488 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:13:12.966 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:13:13.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:13.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:13.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:13.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:13.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:13.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:13.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:13.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:13.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:13.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:13.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:13.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:13.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:13.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:13.030 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:13.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1035 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:18.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:18.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:18.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:18.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:18.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:18.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:18.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:18.046 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:18.046 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:18.046 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:18.046 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:13:18.049 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:13:18.049 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:13:18.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:18.050 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:18.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:18.051 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:13:18.051 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:18.051 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:13:18.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:18.052 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:13:18.052 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:13:18.053 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:18.053 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:18.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:18.053 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:13:18.053 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:18.053 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:13:18.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:18.055 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:18.055 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:13:18.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.058 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:13:18.059 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:13:18.059 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:13:18.059 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:18.064 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:13:18.547 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:13:18.590 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:13:18.592 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:13:18.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:18.594 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:13:18.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:18.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:18.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:18.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:18.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:18.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:18.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:18.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:18.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:18.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:18.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:18.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:18.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:19.024 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:13:19.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:19.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:19.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:19.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:19.502 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:13:19.980 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:13:20.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:20.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:20.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:20.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:20.458 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:13:20.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:20.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:20.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:20.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:20.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:20.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:20.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:20.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:20.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:20.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:20.764 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:20.764 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:20.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:20.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:20.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:20.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:20.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:20.936 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:13:21.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:21.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:21.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:21.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:21.414 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:13:21.892 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:13:22.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:22.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:22.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:22.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:22.370 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:13:22.848 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:13:22.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:22.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:22.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:22.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:22.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:22.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:22.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:22.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:22.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:22.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:22.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:22.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:22.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:22.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:22.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:22.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:22.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:23.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:23.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:23.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:23.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:23.325 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:13:23.803 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:13:24.281 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:13:24.759 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:13:25.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:25.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:25.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:25.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:25.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:25.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:25.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:25.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:25.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:25.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:25.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:25.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:25.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:25.053 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:25.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:30.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:30.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:30.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:30.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:30.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:30.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:30.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:30.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:30.066 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:30.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:30.066 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:30.067 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:30.067 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:13:30.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:30.069 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:30.069 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:13:30.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:30.070 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:13:30.070 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:13:30.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:30.070 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:30.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:30.070 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:13:30.071 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:30.071 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:13:30.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.073 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:13:30.073 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:13:30.073 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:13:30.074 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:30.078 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:13:30.561 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:13:30.602 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:13:30.604 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:13:30.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:30.605 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:13:30.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:30.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:30.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:30.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:30.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:30.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:30.633 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:30.633 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:30.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:30.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:30.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:30.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:30.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:31.037 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:13:31.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:31.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:31.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:31.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:31.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:13:31.994 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:13:32.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:32.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:32.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:32.472 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:13:32.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:32.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:32.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:32.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:32.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:32.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:32.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:32.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:32.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:32.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:32.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:32.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:32.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:32.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:32.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:32.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:32.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:32.947 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:13:33.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:33.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:33.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:33.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:33.424 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:13:33.902 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:13:34.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:34.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:34.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:34.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:34.380 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:13:34.858 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:13:34.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:34.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:34.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:34.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:34.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:34.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:34.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:34.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:34.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:34.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:34.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:34.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:34.976 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:34.976 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:34.976 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:34.976 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1047 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:34.976 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1047 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:34.976 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1047 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:34.976 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1047 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:39.978 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:39.978 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:39.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:39.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:39.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:39.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:39.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:39.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:39.987 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:39.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:39.987 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:13:39.991 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:13:39.991 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:13:39.991 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:39.992 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:39.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:39.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:13:39.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:39.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:13:39.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:39.995 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:13:39.995 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:13:39.995 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:39.995 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:39.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:39.995 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:13:39.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:39.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:13:39.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:39.998 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:39.998 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:13:39.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:40.000 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:13:40.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:13:40.001 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:13:40.001 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:13:40.001 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:40.006 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:13:40.489 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:13:40.521 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:13:40.524 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:13:40.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:40.526 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:13:40.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:40.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:40.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:40.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:40.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:40.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:40.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:40.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:40.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:40.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:40.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:40.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:40.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:40.963 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:13:41.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:41.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:41.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:41.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:41.441 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:13:41.919 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:13:42.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:42.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:42.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:42.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:42.397 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:13:42.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:42.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:42.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:42.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:42.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:42.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:42.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:42.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:42.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:42.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:42.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:42.791 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:42.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:42.791 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:42.791 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=596 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:42.791 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=597 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:47.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:47.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:47.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:47.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:47.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:47.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:47.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:47.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:47.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:47.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:47.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:13:47.809 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:13:47.809 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:13:47.809 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:47.810 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:47.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:47.810 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:13:47.810 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:47.810 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:13:47.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:47.812 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:13:47.812 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:13:47.812 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:47.812 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:47.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:47.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:13:47.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:47.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:13:47.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:47.814 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:13:47.814 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:13:47.814 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:47.814 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:47.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:47.815 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:13:47.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:47.815 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:13:47.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.817 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:13:47.817 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:13:47.817 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:13:47.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:47.822 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:13:48.306 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:13:48.345 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:13:48.346 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:13:48.347 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:13:48.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:48.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:48.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:48.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:48.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:48.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:48.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:48.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:48.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:48.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:48.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:48.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:48.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:48.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:48.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:13:48.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:48.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:48.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:48.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:49.261 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:13:49.740 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:13:49.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:49.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:49.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:49.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:50.218 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:13:50.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:50.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:50.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:50.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:50.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:50.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:50.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:50.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:50.604 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:50.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:50.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:50.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:50.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:50.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:50.604 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:50.604 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=595 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:50.604 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=595 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:50.604 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=595 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:50.604 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=595 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:50.604 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=595 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:50.604 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=595 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:55.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:55.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:55.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:55.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:55.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:55.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:55.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:55.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:55.621 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:55.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:13:55.622 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:13:55.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:13:55.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:13:55.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:55.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:55.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:55.626 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:13:55.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:13:55.626 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:13:55.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:55.629 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:13:55.629 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:13:55.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:55.631 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:13:55.631 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:13:55.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:55.631 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:13:55.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:55.631 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:13:55.632 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:13:55.632 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:13:55.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:13:55.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:13:55.635 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:13:55.635 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:13:55.635 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:13:55.640 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:13:56.124 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:13:56.169 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:13:56.171 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:13:56.172 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:13:56.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:56.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:56.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:56.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:56.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:56.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:56.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:56.205 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:56.205 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:56.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:56.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:56.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:56.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:56.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:56.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:56.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:56.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:56.601 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:13:56.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:56.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:56.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:13:56.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:56.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:56.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:56.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:13:56.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:13:56.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:56.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:56.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:56.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:56.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:56.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:13:56.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:13:56.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:56.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:57.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:13:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:13:57.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:13:57.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:13:57.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:13:57.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:13:57.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:13:57.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:13:57.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:13:57.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:13:57.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:13:57.044 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:13:57.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:13:57.045 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:13:57.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:13:57.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=301 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:13:57.047 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=302 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:02.044 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:02.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:02.046 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:02.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:02.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:02.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:02.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:02.055 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:02.055 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:02.055 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:02.055 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:02.058 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:02.058 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:02.058 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:02.058 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:02.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:02.059 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:02.059 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:02.059 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:02.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:02.061 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:02.062 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:02.062 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:02.062 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:02.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:02.062 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:02.062 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:02.062 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:02.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:02.064 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:02.064 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:02.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:02.064 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:02.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:02.065 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:02.065 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:02.065 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:02.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.068 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:02.068 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:02.069 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:02.069 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:02.073 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:02.556 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:02.588 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:02.589 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:02.590 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:02.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:02.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:02.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:02.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:02.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:02.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:02.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:02.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:02.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:02.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:02.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:02.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:02.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:02.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:03.029 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:03.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:03.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:03.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:03.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:03.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:03.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:03.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:03.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:03.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:03.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:03.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:03.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:03.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:03.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:03.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:03.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:03.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:03.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:03.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:03.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:03.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:03.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:03.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:03.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:03.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:03.504 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:14:03.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:03.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:03.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:03.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:03.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:03.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:03.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:03.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:03.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:03.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:03.512 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:08.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:08.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:08.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:08.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:08.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:08.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:08.526 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:08.528 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:08.528 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:08.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:08.529 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:08.533 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:08.534 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:08.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:08.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:08.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:08.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:08.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:08.536 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:08.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:08.537 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:08.537 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:08.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:08.537 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:08.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:08.538 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:08.538 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:08.538 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:08.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:08.540 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:08.540 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:08.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:08.540 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:08.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:08.540 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:08.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:08.540 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:08.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:08.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:08.544 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:08.545 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:08.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:09.032 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:09.077 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:09.079 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:09.081 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:09.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:09.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:09.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:09.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:09.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:09.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:09.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:09.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:09.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:09.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:09.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:09.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.507 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:09.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:09.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:09.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:09.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:09.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:09.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:09.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:09.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:09.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:09.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:09.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:09.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:09.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:09.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:09.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:09.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:09.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:09.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:09.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:14:10.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:10.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:10.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:10.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:10.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:10.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:10.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:10.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:10.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:10.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:10.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:10.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:10.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:10.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:10.031 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:10.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=318 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:10.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=318 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:10.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=318 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:10.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=318 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:10.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=318 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:10.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=318 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:15.034 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:15.034 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:15.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:15.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:15.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:15.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:15.042 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:15.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:15.044 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:15.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:15.044 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:15.048 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:15.048 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:15.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:15.049 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:15.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:15.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:15.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:15.049 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:15.049 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:15.052 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:15.052 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:15.053 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:15.053 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:15.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:15.053 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:15.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:15.054 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:15.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:15.055 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:15.055 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:15.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:15.058 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.059 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:15.059 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:15.059 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:15.060 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:15.065 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:15.548 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:15.592 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:15.595 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:15.597 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:15.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:15.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:15.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:15.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:15.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:15.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:15.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:15.660 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:15.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:15.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:15.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:15.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:15.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:15.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:16.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:16.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:16.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:16.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:16.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:16.503 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:14:16.981 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:14:17.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:17.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:17.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:17.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:17.458 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:14:17.937 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:14:18.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:18.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:18.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:18.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:18.415 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:14:18.893 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:14:19.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:19.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:19.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:19.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:19.371 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:14:19.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:19.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:19.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:19.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:19.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:19.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:19.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:19.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:19.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:19.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:19.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:19.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:19.704 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:19.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:24.709 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:24.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:24.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:24.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:24.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:24.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:24.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:24.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:24.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:24.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:24.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:24.725 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:24.725 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:24.726 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:24.726 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:24.726 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:24.726 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:24.726 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:24.726 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:24.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:24.728 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:24.729 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:24.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:24.729 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:24.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:24.729 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:24.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:24.729 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:24.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:24.731 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:24.731 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:24.731 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:24.731 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:24.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:24.732 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:24.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:24.732 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:24.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.735 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:24.735 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:24.735 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:24.736 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:24.740 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:25.221 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:25.268 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:25.269 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:25.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:25.272 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:25.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:25.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:25.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:25.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:25.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:25.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:25.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:25.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:25.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:25.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:25.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:25.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:25.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:25.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:25.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:25.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:25.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:25.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:25.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:25.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:25.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:25.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:25.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.695 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:25.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:25.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:25.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:25.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:25.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:25.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:25.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:25.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:25.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:25.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:25.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:25.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:25.877 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:25.877 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=246 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:30.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:30.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:30.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:30.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:30.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:30.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:30.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:30.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:30.888 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:30.889 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:30.889 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:30.891 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:30.892 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:30.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:30.892 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:30.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:30.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:30.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:30.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:30.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:30.895 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:30.895 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:30.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:30.897 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:30.897 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:30.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:30.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:30.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:30.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:30.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:30.898 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:30.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:30.900 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:30.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:30.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:30.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:30.900 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:30.901 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:30.901 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:30.901 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:30.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:30.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:30.906 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:31.389 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:31.436 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:31.438 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:31.439 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:31.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:31.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:31.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:31.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:31.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:31.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:31.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:31.502 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:31.502 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:31.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:31.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:31.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:31.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:31.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:31.866 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:31.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:31.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:31.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:31.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:32.344 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:14:32.822 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:14:32.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:32.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:32.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:32.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:33.300 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:14:33.778 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:14:33.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:33.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:33.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:33.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:34.256 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:14:34.734 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:14:34.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:34.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:34.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:34.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:35.212 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:14:35.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:35.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:35.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:35.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:35.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:35.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:35.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:35.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:35.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:35.547 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:35.547 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:40.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:40.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:40.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:40.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:40.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:40.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:40.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:40.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:40.562 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:40.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:40.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:40.565 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:40.565 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:40.565 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:40.565 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:40.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:40.566 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:40.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:40.566 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:40.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:40.567 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:40.567 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:40.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:40.567 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:40.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:40.568 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:40.568 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:40.568 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:40.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:40.569 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:40.570 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:40.570 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:40.570 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:40.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:40.570 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:40.570 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:40.570 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:40.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.574 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:40.574 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:40.575 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:40.575 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:40.580 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:41.063 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:41.100 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:41.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:41.103 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:41.105 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:41.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:41.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:41.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:41.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:41.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:41.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:41.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:41.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:41.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:41.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:41.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:41.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:41.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:41.535 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:41.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:41.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:41.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:41.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:41.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:41.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:41.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:41.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:41.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:41.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:41.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:41.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:41.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:41.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:41.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:41.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:41.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:41.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:41.941 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:41.941 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:46.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:46.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:46.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:46.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:46.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:46.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:46.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:46.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:46.955 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:46.956 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:46.956 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:46.960 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:46.960 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:46.961 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:46.961 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:46.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:46.962 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:46.962 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:46.962 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:46.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:46.963 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:46.963 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:46.963 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:46.963 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:46.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:46.963 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:46.964 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:46.964 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:46.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:46.965 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:46.965 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:46.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:46.966 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:46.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:46.966 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:46.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:46.966 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:46.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.969 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:46.969 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:46.969 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:46.970 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:46.974 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:47.458 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:47.504 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:47.506 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:47.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:47.508 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:47.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:47.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:47.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:47.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:47.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:47.562 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:47.562 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:47.562 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:47.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:47.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:47.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:47.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:47.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:47.935 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:47.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:47.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:47.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:47.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:48.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:48.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:48.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:48.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:48.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:48.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:48.339 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:48.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:48.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:48.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:48.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:48.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:48.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:48.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:48.344 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:48.344 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:53.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:53.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:53.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:53.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:53.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:53.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:53.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:53.354 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:53.354 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:53.354 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:53.354 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:53.355 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:53.355 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:53.355 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:53.355 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:53.356 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:53.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:53.357 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:53.357 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:53.357 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:53.357 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:53.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:53.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:53.359 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:53.359 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:53.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:53.362 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:53.362 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:53.362 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:53.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:53.367 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:14:53.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:14:53.885 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:14:53.886 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:14:53.886 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:14:53.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:53.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:53.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:53.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:14:53.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:53.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:53.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:53.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:14:53.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:14:53.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:53.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:14:53.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:14:53.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:53.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:54.328 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:14:54.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:54.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:54.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:54.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:54.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:14:54.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:14:54.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:14:54.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:14:54.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:54.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:54.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:54.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:54.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:54.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:54.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:54.736 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:54.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:14:59.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:14:59.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:14:59.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:59.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:59.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:59.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:59.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:14:59.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:59.749 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:59.750 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:14:59.750 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:14:59.753 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:14:59.753 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:14:59.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:59.753 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:59.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:14:59.754 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:14:59.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:14:59.754 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:14:59.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:14:59.756 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:14:59.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:14:59.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:59.757 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:59.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:14:59.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:14:59.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:14:59.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:14:59.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:14:59.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:14:59.759 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:14:59.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:59.760 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:14:59.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:14:59.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:14:59.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:14:59.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:14:59.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.763 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:14:59.763 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:14:59.764 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:14:59.764 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:14:59.769 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:15:00.253 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:15:00.289 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:15:00.290 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:15:00.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:00.291 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:15:00.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:00.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:00.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:00.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:00.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:00.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:00.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:00.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:00.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:00.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:00.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:00.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:00.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:00.730 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:15:00.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:00.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:00.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:00.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:01.208 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:15:01.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:01.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:01.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:01.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:01.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:01.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:01.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:01.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:01.278 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:01.278 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:01.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:01.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:01.278 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:01.279 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:01.279 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:01.279 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:06.281 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:06.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:06.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:06.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:06.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:06.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:06.294 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:06.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:06.296 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:06.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:06.297 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:15:06.302 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:15:06.303 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:15:06.303 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:06.303 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:06.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:06.303 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:15:06.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:06.304 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:15:06.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:06.308 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:15:06.308 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:15:06.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:06.309 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:06.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:06.309 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:15:06.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:06.309 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:15:06.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:06.312 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:15:06.312 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:15:06.312 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:06.312 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:06.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:06.313 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:15:06.313 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:06.313 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:15:06.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:15:06.318 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:15:06.318 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:15:06.318 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:06.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:06.323 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:15:06.806 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:15:06.837 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:15:06.838 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:15:06.839 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:15:06.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:06.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:06.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:06.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:06.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:06.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:06.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:06.888 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:06.888 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:06.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:06.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:06.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:06.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:07.280 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:15:07.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:07.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:07.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:07.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:07.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:07.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:07.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:07.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:07.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:07.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:07.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:07.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:07.642 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:07.642 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:07.642 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:15:07.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.643 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=284 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:07.644 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=285 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:12.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:12.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:12.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:12.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:12.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:12.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:12.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:12.656 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:12.656 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:12.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:12.657 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:15:12.661 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:15:12.661 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:15:12.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:12.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:12.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:12.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:15:12.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:12.664 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:15:12.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:12.665 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:15:12.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:15:12.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:12.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:12.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:12.666 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:15:12.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:12.666 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:15:12.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:12.669 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:15:12.669 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:15:12.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:12.669 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:12.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:12.670 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:15:12.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:12.670 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:15:12.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:12.673 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:15:12.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.674 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:15:12.674 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:15:12.674 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:15:12.675 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:12.679 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:15:13.163 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:15:13.196 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:15:13.197 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:15:13.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:13.198 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:15:13.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:13.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:13.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:13.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:13.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:13.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:13.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:13.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:13.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:13.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:13.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:13.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:13.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:13.637 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:15:13.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:13.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:13.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:13.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:14.115 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:15:14.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:14.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:14.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:14.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:14.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:14.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:14.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:14.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:14.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:14.184 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:14.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:14.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:14.184 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:14.184 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:14.184 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:14.185 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:19.186 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:19.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:19.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:19.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:19.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:19.189 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:19.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:19.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:19.199 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:19.199 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:19.199 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:15:19.202 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:15:19.202 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:15:19.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:19.202 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:19.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:19.202 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:15:19.203 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:19.203 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:15:19.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:19.205 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:15:19.205 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:15:19.205 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:19.205 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:19.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:19.205 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:15:19.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:19.206 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:15:19.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:19.207 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:15:19.208 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:15:19.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:19.208 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:19.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:19.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:15:19.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:19.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:15:19.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:15:19.212 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:15:19.212 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:15:19.212 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:19.217 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:15:19.701 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:15:19.746 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:15:19.749 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:15:19.749 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:15:19.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:19.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:19.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:19.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:19.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:19.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:19.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:19.769 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:19.769 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:20.177 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:15:20.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:20.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:20.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:20.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:20.654 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:15:20.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:20.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:20.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:20.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:20.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:20.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:20.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:20.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:20.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:20.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:20.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:20.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:21.127 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:15:21.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:21.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:21.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:21.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:21.605 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:15:21.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:15:22.083 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:15:22.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:15:22.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:22.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:22.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:22.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:22.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:22.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:22.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:22.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:22.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:22.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:22.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:22.137 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:15:22.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:22.137 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.137 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.137 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.137 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.137 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=625 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=625 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:22.138 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:27.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:27.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:27.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:27.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:27.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:27.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:27.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:27.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:27.146 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:27.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:27.147 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:15:27.150 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:15:27.151 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:15:27.151 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:27.151 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:27.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:27.152 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:15:27.152 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:27.152 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:15:27.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:27.153 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:15:27.153 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:15:27.153 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:27.153 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:27.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:27.154 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:15:27.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:27.154 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:15:27.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:27.156 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:27.156 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:15:27.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:15:27.160 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:15:27.160 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:15:27.160 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:27.165 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:15:27.647 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:15:27.682 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:15:27.683 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:15:27.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:27.684 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:15:27.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:27.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:27.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:27.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:27.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:27.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:27.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:27.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:28.125 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:15:28.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:28.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:28.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:28.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:28.602 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:15:29.080 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:15:29.163 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:29.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:29.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:29.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:29.558 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:15:30.035 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:15:30.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:30.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:30.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:30.168 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:30.512 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:15:30.990 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:15:31.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:31.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:31.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:31.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:31.468 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:15:31.945 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:15:32.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:32.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:32.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:32.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:32.422 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:15:32.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:15:32.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:32.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:32.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:32.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:32.900 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:15:33.374 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:15:33.843 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:15:34.314 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:15:34.784 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:15:35.255 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:15:35.726 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:15:36.201 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:15:36.679 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:15:37.151 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:15:37.630 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:15:38.108 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:15:38.577 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:15:39.046 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:15:39.516 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:15:39.987 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:15:40.458 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:15:40.929 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:15:41.400 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:15:41.871 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:15:42.344 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:15:42.813 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:15:43.282 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:15:43.758 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:15:44.230 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:15:44.702 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:15:45.180 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:15:45.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:15:45.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:45.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:45.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:45.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:45.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:45.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:45.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:45.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:45.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:45.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:45.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:45.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:45.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:45.479 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:15:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3942 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3942 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3942 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3942 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3942 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:45.479 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3942 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:15:50.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:15:50.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:15:50.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:50.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:50.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:50.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:50.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:15:50.487 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:50.487 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:50.487 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:15:50.488 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:15:50.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:15:50.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:15:50.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:50.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:50.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:15:50.491 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:15:50.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:15:50.492 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:15:50.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:50.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:15:50.493 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:15:50.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:50.495 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:15:50.495 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:15:50.495 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:50.495 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:15:50.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:15:50.495 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:15:50.495 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:15:50.495 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:15:50.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:15:50.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:15:50.499 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:15:50.499 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:15:50.499 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:15:50.504 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:15:50.986 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:15:51.026 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:15:51.027 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:15:51.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:15:51.028 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:15:51.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:15:51.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:15:51.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:15:51.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:51.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:51.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:51.050 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:15:51.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:15:51.463 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:15:51.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:51.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:51.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:51.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:51.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:15:52.415 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:15:52.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:52.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:52.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:52.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:52.892 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:15:53.369 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:15:53.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:53.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:53.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:53.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:53.846 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:15:54.321 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:15:54.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:54.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:54.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:54.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:54.798 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:15:55.275 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:15:55.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:15:55.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:15:55.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:15:55.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:15:55.752 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:15:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:15:55.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:15:55.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:15:55.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:55.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:15:56.230 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:15:56.704 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:15:57.173 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:15:57.645 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:15:58.114 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:15:58.590 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:15:59.062 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:15:59.534 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:16:00.004 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:16:00.478 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:16:00.956 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:16:01.430 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:16:01.899 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:16:02.370 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:16:02.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:02.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:02.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:02.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:02.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:02.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:02.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:02.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:02.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:02.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:02.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:02.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:02.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:02.548 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:16:02.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:02.548 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:02.548 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:02.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:02.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:02.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:02.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:02.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2590 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:07.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:07.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:07.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:07.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:07.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:07.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:07.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:07.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:07.560 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:07.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:07.561 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:16:07.565 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:16:07.565 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:16:07.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:07.566 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:07.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:07.567 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:16:07.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:07.568 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:16:07.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:07.569 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:16:07.569 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:16:07.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:07.569 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:07.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:07.570 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:16:07.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:07.571 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:16:07.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:07.572 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:16:07.572 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:16:07.572 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:07.572 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:07.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:07.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:16:07.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:07.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:16:07.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:07.576 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:16:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:16:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:16:07.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:16:07.576 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.577 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:16:07.577 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:16:07.577 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:16:07.578 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:07.582 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:16:08.066 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:16:08.115 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:16:08.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:16:08.119 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:16:08.121 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:16:08.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:08.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:08.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:16:08.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:08.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:16:08.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:16:08.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:16:08.152 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:16:08.543 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:16:08.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:08.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:08.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:08.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:09.021 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:16:09.498 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:16:09.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:09.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:09.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:09.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:09.976 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:16:10.453 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:16:10.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:10.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:10.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:10.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:10.930 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:16:11.408 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:16:11.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:11.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:11.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:11.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:11.886 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:16:12.364 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:16:12.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:12.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:12.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:12.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:12.841 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:16:12.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:12.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:16:12.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:16:12.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:12.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:13.319 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:16:13.799 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:16:14.278 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:16:14.756 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:16:15.235 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:16:15.713 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:16:16.192 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:16:16.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:16.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:16.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:16.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:16.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:16.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:16.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:16.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:16.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:16.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:16.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:16.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:16.304 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:16:16.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:16.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:16.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:21.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:21.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:21.305 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:21.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:21.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:21.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:21.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:21.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:21.320 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:21.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:21.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:16:21.324 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:16:21.325 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:16:21.325 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:21.325 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:21.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:21.326 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:16:21.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:21.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:16:21.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:21.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:16:21.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:16:21.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:21.328 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:21.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:21.328 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:16:21.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:21.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:16:21.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:21.330 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:16:21.330 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:16:21.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:21.331 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:21.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:21.331 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:16:21.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:21.331 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:16:21.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.334 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:16:21.334 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:16:21.334 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:16:21.335 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:21.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:21.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:21.339 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:16:21.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:16:21.859 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:16:21.861 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:16:21.862 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:16:21.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:16:21.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:21.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:21.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:16:21.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:21.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:16:21.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:16:21.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:16:21.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:16:22.297 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:16:22.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:22.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:22.339 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:22.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:22.783 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:16:23.259 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:16:23.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:23.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:23.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:23.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:23.737 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:16:24.215 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:16:24.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:24.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:24.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:24.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:24.693 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:16:25.170 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:16:25.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:25.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:25.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:25.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:25.648 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:16:26.126 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:16:26.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:26.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:26.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:26.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:26.604 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:16:26.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:26.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:16:26.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:16:26.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:26.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:27.082 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:16:27.560 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:16:28.038 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:16:28.513 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:16:28.982 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:16:29.452 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:16:29.930 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:16:30.408 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:16:30.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:30.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:30.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:30.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:30.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:30.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:30.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:30.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:30.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:30.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:30.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:30.530 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:30.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:30.530 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:16:30.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1965 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:30.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1966 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:35.529 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:35.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:35.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:35.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:35.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:35.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:35.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:35.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:35.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:35.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:35.541 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:16:35.543 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:16:35.543 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:16:35.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:35.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:35.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:35.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:16:35.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:35.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:16:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:35.546 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:35.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:16:35.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:35.548 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:16:35.548 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:16:35.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:35.548 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:35.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:35.548 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:16:35.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:35.548 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:16:35.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:16:35.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:16:35.552 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:16:35.552 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:16:35.552 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:35.557 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:16:36.039 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:16:36.079 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:16:36.080 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:16:36.081 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:16:36.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:16:36.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:36.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:36.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:16:36.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:36.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:16:36.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:16:36.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:16:36.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:16:36.517 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:16:36.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:36.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:36.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:36.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:36.994 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:16:37.471 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:16:37.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:37.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:37.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:37.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:37.949 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:16:38.426 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:16:38.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:38.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:38.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:38.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:38.904 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:16:39.381 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:16:39.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:39.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:39.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:39.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:39.859 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:16:40.337 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:16:40.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:40.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:40.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:40.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:40.815 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:16:40.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:40.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:16:40.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:16:40.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:40.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:41.293 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:16:41.771 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:16:42.250 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:16:42.728 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:16:43.206 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:16:43.684 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:16:44.162 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:16:44.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:16:44.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:16:44.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:16:44.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:16:44.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:44.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:44.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:44.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:44.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:44.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:44.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:44.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:44.275 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:44.275 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:44.275 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:44.275 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:49.279 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:49.279 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:49.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:49.279 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:49.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:49.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:49.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:49.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:49.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:49.288 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:16:49.288 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:16:49.291 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:16:49.291 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:16:49.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:49.292 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:49.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:49.293 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:16:49.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:16:49.293 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:16:49.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:49.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:16:49.294 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:16:49.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:49.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:49.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:49.295 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:16:49.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:16:49.295 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:16:49.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:49.297 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:16:49.297 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:16:49.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:49.300 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:16:49.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:16:49.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:16:49.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:16:49.300 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:16:49.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:16:49.301 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:16:49.301 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:16:49.301 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:16:49.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:16:49.306 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:16:49.790 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:16:49.823 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:16:49.824 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:16:49.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:16:49.825 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:16:50.259 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:16:50.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:50.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:50.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:50.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:50.728 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:16:51.210 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:16:51.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:51.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:51.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:51.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:51.691 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:16:52.173 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:16:52.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:52.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:52.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:52.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:52.651 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:16:53.129 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:16:53.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:53.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:53.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:53.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:53.606 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:16:54.084 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:16:54.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:54.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:54.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:54.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:54.564 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:16:55.042 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:16:55.520 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:16:56.002 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:16:56.482 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:16:56.963 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:16:57.443 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:16:57.924 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:16:58.397 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:16:58.867 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:16:59.346 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:16:59.824 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:16:59.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:16:59.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:16:59.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:16:59.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:16:59.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:16:59.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:16:59.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:16:59.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:16:59.837 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:16:59.837 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:16:59.837 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:16:59.837 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:59.837 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:59.837 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:59.837 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:59.837 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:59.838 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:16:59.838 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:04.839 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:04.839 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:04.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:04.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:04.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:04.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:04.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:04.854 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:04.854 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:04.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:04.855 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:17:04.857 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:17:04.857 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:17:04.858 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:04.858 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:04.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:04.859 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:17:04.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:04.860 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:17:04.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:04.861 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:04.861 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:17:04.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:04.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:04.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:17:04.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:04.868 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.869 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:17:04.869 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:17:04.869 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:17:04.870 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:17:04.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:17:04.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:04.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:04.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:04.872 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:17:09.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:09.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:09.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:09.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:09.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:09.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:09.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:09.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:09.887 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:09.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:09.887 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:17:09.890 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:17:09.890 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:17:09.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:09.891 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:09.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:09.891 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:17:09.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:09.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:17:09.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:09.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:09.893 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:17:09.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:09.897 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:17:09.897 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:17:09.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:09.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:09.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:17:09.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:09.897 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:17:09.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:09.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:17:09.906 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:17:09.906 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:17:09.906 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:09.911 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:17:10.394 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:17:10.440 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:17:10.441 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:17:10.443 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:17:10.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:17:10.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:17:10.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:17:10.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:17:10.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:17:10.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:17:10.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:17:10.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:17:10.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:17:10.871 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:17:10.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:10.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:10.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:10.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:11.349 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:17:11.826 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:17:11.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:11.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:11.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:11.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:12.304 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:17:12.781 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:17:12.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:12.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:12.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:12.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:13.259 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:17:13.736 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:17:13.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:13.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:13.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:13.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:14.213 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:17:14.691 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:17:14.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:14.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:14.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:14.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:15.169 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:17:15.646 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:17:16.124 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:17:16.601 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:17:17.080 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:17:17.557 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:17:18.035 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:17:18.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:17:18.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:17:18.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:18.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:18.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:18.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:18.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:18.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:18.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:18.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:18.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:18.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:18.496 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:17:23.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:23.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:23.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:23.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:23.503 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:23.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:23.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:23.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:23.521 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:23.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:23.522 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:17:23.526 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:17:23.526 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:17:23.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:23.527 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:23.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:23.527 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:17:23.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:23.527 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:17:23.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:23.529 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:17:23.529 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:17:23.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:23.530 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:23.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:23.530 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:17:23.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:23.530 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:17:23.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:23.532 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:23.532 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:17:23.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:17:23.535 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:17:23.535 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:17:23.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:17:23.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:17:23.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:23.537 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:23.537 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:23.537 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:17:28.540 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:28.541 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:28.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:28.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:28.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:28.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:28.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:28.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:28.552 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:28.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:28.552 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:17:28.553 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:17:28.553 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:17:28.554 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:28.554 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:28.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:28.554 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:17:28.555 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:28.555 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:17:28.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:28.557 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:17:28.557 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:17:28.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:28.557 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:28.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:28.558 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:17:28.558 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:28.558 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:17:28.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:28.561 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:17:28.561 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:17:28.561 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:28.561 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:28.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:28.561 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:17:28.562 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:28.562 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:17:28.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:17:28.567 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:17:28.567 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:17:28.567 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:28.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:28.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:28.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:28.572 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:17:29.053 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:17:29.106 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:17:29.108 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:17:29.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:17:29.111 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:17:29.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:17:29.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:17:29.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:17:29.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:17:29.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:17:29.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:17:29.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:17:29.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:17:29.530 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:17:29.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:29.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:29.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:29.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:30.008 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:17:30.486 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:17:30.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:30.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:30.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:30.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:30.964 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:17:31.437 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:17:31.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:31.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:31.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:31.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:31.915 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:17:32.393 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:17:32.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:32.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:32.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:32.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:32.870 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:17:33.347 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:17:33.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:33.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:33.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:33.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:33.825 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:17:34.302 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:17:34.779 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:17:35.256 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:17:35.734 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:17:36.212 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:17:36.689 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:17:37.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:17:37.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:17:37.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:37.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:37.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:37.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:37.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:37.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:37.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:37.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:37.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:37.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:37.157 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:17:37.157 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:37.157 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:37.157 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:37.157 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:37.157 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:37.158 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:42.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:42.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:42.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:42.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:42.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:42.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:42.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:42.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:42.162 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:42.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:42.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:17:42.163 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:17:42.163 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:17:42.163 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:42.164 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:42.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:42.164 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:17:42.164 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:42.164 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:17:42.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:42.165 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:17:42.165 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:17:42.165 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:42.166 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:42.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:42.166 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:17:42.166 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:42.166 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:17:42.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:42.167 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:17:42.168 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:17:42.168 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:42.168 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:42.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:42.168 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:17:42.168 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:42.168 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:17:42.168 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:42.170 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:17:42.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:17:42.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:17:42.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:17:42.170 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:17:42.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:17:42.171 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:17:42.171 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:17:42.171 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:17:42.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:42.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:42.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:42.173 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:17:47.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:47.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:47.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:47.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:47.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:47.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:47.189 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:47.191 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:47.191 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:47.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:17:47.192 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:17:47.196 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:17:47.197 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:17:47.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:47.197 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:47.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:47.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:17:47.199 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:17:47.199 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:17:47.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:47.200 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:17:47.201 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:17:47.201 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:47.201 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:47.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:47.201 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:17:47.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:17:47.202 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:17:47.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:47.204 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:17:47.204 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:17:47.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:47.205 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:17:47.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:47.205 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:17:47.205 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:17:47.205 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:17:47.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:17:47.210 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:17:47.210 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:17:47.210 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:17:47.215 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:17:47.695 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:17:47.731 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:17:47.732 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:17:47.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:17:47.733 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:17:47.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:17:47.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:17:47.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:17:47.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:17:47.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:17:47.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:17:47.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:17:47.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:17:48.172 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:17:48.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:48.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:48.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:48.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:48.650 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:17:49.127 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:17:49.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:49.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:49.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:49.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:49.605 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:17:50.083 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:17:50.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:50.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:50.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:50.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:50.561 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:17:51.038 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:17:51.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:51.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:51.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:51.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:51.516 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:17:51.994 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:17:52.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:52.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:52.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:52.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:52.471 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:17:52.949 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:17:53.426 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:17:53.903 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:17:54.381 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:17:54.859 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:17:55.336 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:17:55.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:17:55.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:17:55.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:17:55.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:17:55.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:17:55.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:17:55.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:17:55.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:17:55.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:17:55.750 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:17:55.750 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:17:55.751 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:17:55.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:17:55.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:55.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:55.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:17:55.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:18:00.750 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:00.750 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:00.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:00.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:00.754 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:00.754 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:00.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:00.762 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:00.762 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:00.762 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:00.762 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:18:00.764 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:18:00.765 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:18:00.765 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:00.765 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:00.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:00.766 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:18:00.766 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:00.766 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:18:00.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:00.767 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:00.767 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:18:00.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:00.769 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:18:00.769 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:18:00.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:00.769 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:00.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:00.769 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:18:00.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:00.770 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:18:00.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:18:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:18:00.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:18:00.773 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:18:00.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:18:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:00.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:00.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:00.775 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:18:05.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:05.778 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:05.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:05.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:05.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:05.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:05.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:05.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:05.789 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:05.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:05.789 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:18:05.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:18:05.791 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:18:05.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:05.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:05.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:05.793 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:18:05.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:05.793 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:18:05.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:05.794 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:05.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:18:05.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:05.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:05.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:18:05.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:18:05.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:18:05.799 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:18:05.800 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:05.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:18:06.288 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:18:06.327 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:18:06.328 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:18:06.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:18:06.329 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:18:06.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:18:06.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:18:06.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:18:06.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:18:06.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:18:06.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:18:06.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:18:06.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:18:06.765 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:18:06.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:06.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:06.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:06.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:07.243 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:18:07.721 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:18:07.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:07.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:07.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:07.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:08.199 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:18:08.676 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:18:08.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:08.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:08.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:08.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:09.153 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:18:09.632 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:18:09.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:09.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:09.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:09.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:10.109 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:18:10.587 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:18:10.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:10.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:10.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:10.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:11.065 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:18:11.542 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:18:12.020 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:18:12.497 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:18:12.975 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:18:13.453 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:18:13.930 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:18:14.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:18:14.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:18:14.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:14.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:14.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:14.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:14.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:14.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:14.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:14.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:14.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:14.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:14.386 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:18:19.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:19.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:19.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:19.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:19.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:19.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:19.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:19.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:19.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:19.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:19.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:19.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:19.399 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:18:19.399 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:19.399 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:19.400 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:19.400 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:19.400 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:18:19.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:18:19.402 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:18:19.402 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:18:19.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:19.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:19.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:19.403 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:18:24.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:24.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:24.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:24.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:24.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:24.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:24.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:24.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:24.421 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:24.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:24.422 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:18:24.425 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:18:24.426 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:18:24.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:24.426 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:24.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:24.427 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:18:24.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:24.428 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:18:24.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:24.429 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:18:24.429 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:18:24.429 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:24.430 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:24.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:24.430 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:18:24.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:24.430 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:18:24.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:24.432 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:24.432 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:18:24.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:18:24.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:18:24.436 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:18:24.436 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:18:24.436 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:24.441 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:18:24.924 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:18:24.963 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:18:24.964 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:18:24.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:18:24.965 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:18:24.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:18:24.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:18:24.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:18:24.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:18:24.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:18:24.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:18:24.967 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:18:24.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:18:25.401 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:18:25.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:25.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:25.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:25.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:25.879 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:18:26.356 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:18:26.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:26.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:26.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:26.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:26.834 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:18:27.312 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:18:27.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:27.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:27.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:27.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:27.789 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:18:28.267 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:18:28.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:28.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:28.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:28.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:28.744 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:18:29.221 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:18:29.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:29.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:29.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:29.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:29.699 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:18:30.177 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:18:30.655 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:18:31.132 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:18:31.610 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:18:32.088 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:18:32.565 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:18:33.043 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:18:33.521 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:18:33.998 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:18:34.476 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:18:34.953 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:18:35.432 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:18:35.909 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:18:36.386 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:18:36.864 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:18:37.341 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:18:37.819 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:18:38.296 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:18:38.773 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:18:39.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:18:39.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:18:39.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:39.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:39.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:39.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:39.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:39.025 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:39.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:39.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:39.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:39.025 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:18:39.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:44.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:44.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:44.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:44.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:44.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:44.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:44.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:44.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:44.041 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:44.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:44.041 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:18:44.045 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:18:44.045 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:18:44.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:44.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:44.046 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:44.046 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:18:44.046 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:44.046 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:18:44.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:44.048 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:18:44.048 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:18:44.049 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:44.049 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:44.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:44.049 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:18:44.049 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:44.049 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:18:44.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:44.051 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:18:44.051 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:18:44.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:44.051 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:44.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:18:44.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:44.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:44.052 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:18:44.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:18:44.055 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:18:44.055 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:18:44.055 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:18:44.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:44.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:44.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:44.056 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:18:49.059 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:49.059 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:49.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:49.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:49.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:49.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:49.067 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:49.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:49.069 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:49.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:18:49.070 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:18:49.073 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:18:49.073 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:18:49.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:49.074 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:49.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:49.075 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:18:49.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:18:49.075 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:18:49.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:49.076 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:18:49.076 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:18:49.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:49.076 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:49.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:49.077 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:18:49.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:18:49.077 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:18:49.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:49.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:18:49.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:18:49.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:18:49.083 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:18:49.083 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:18:49.083 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:18:49.088 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:18:49.572 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:18:49.615 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:18:49.617 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:18:49.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:18:49.619 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:18:49.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:18:49.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:18:49.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:18:49.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:18:49.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:18:49.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:18:49.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:18:49.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:18:50.049 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:18:50.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:50.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:50.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:50.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:50.527 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:18:51.004 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:18:51.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:51.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:51.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:51.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:51.482 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:18:51.960 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:18:52.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:52.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:52.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:52.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:52.437 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:18:52.915 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:18:53.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:53.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:53.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:53.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:53.392 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:18:53.869 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:18:54.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:54.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:54.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:54.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:54.347 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:18:54.824 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:18:55.302 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:18:55.779 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:18:56.257 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:18:56.734 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:18:57.212 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:18:57.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:18:57.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:18:57.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:18:57.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:18:57.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:18:57.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:18:57.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:18:57.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:18:57.673 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:18:57.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:18:57.673 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:18:57.673 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:18:57.673 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:19:02.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:02.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:02.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:02.677 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:02.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:02.677 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:02.682 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:02.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:02.684 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:02.685 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:02.685 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:19:02.688 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:19:02.688 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:19:02.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:02.689 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:02.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:02.689 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:19:02.689 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:02.689 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:19:02.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:02.692 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:02.692 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:19:02.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:02.694 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:19:02.694 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:19:02.694 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:02.695 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:02.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:02.695 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:19:02.695 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:02.695 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:19:02.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.698 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:19:02.699 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:19:02.699 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:19:02.699 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:02.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:02.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:02.701 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:19:07.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:07.705 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:07.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:07.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:07.708 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:07.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:07.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:07.718 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:07.718 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:07.719 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:07.719 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:19:07.722 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:19:07.723 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:19:07.723 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:07.723 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:07.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:07.724 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:19:07.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:07.724 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:19:07.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:07.725 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:19:07.725 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:19:07.725 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:07.725 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:07.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:07.726 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:19:07.726 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:07.726 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:19:07.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:07.727 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:19:07.727 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:19:07.728 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:07.728 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:07.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:07.728 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:19:07.728 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:07.728 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:19:07.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:07.730 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:19:07.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:19:07.731 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:19:07.731 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:19:07.731 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:07.736 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:19:08.219 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:19:08.263 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:19:08.265 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:19:08.267 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:19:08.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:19:08.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:19:08.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:19:08.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:19:08.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:19:08.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:19:08.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:19:08.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:19:08.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:19:08.696 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:19:08.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:08.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:08.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:08.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:09.173 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:19:09.650 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:19:09.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:09.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:09.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:09.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:10.128 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:19:10.605 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:19:10.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:10.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:10.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:10.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:11.083 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:19:11.561 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:19:11.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:11.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:11.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:11.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:12.038 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:19:12.515 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:19:12.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:12.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:12.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:12.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:12.993 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:19:13.470 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:19:13.948 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:19:14.426 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:19:14.904 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:19:15.381 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:19:15.859 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:19:16.337 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:19:16.815 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:19:17.292 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:19:17.770 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:19:18.247 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:19:18.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:19:18.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:19:18.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:18.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:18.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:18.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:18.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:18.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:18.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:18.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:18.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:18.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:18.324 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:18.325 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2262 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:23.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:23.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:23.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:23.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:23.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:23.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:23.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:23.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:23.352 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:23.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:23.352 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:19:23.353 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:19:23.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:19:23.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:23.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:23.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:23.354 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:23.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:23.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:23.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:23.355 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:19:23.355 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:19:23.355 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:23.355 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:23.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:23.355 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:19:23.355 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:23.355 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:19:23.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.357 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:19:23.357 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:19:23.357 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:19:23.358 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:23.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:23.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:23.359 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:19:28.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:28.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:28.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:28.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:28.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:28.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:28.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:28.376 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:28.376 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:28.377 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:28.377 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:28.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:28.379 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:19:28.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:28.381 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:19:28.381 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:19:28.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:28.381 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:28.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:28.382 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:19:28.382 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:28.382 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:19:28.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:28.383 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:19:28.383 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:19:28.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:28.384 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:28.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:28.384 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:19:28.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:28.384 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:19:28.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:28.386 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:19:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:19:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:19:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:19:28.386 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:19:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:19:28.387 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:19:28.387 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:19:28.387 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:28.392 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:19:28.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:19:28.910 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:19:28.911 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:19:28.912 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:19:28.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:19:28.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:19:28.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:19:28.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:19:28.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:19:28.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:19:28.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:19:28.914 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:19:28.914 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:19:29.352 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:19:29.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:29.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:29.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:29.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:29.829 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:19:30.307 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:19:30.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:30.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:30.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:30.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:30.785 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:19:31.263 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:19:31.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:31.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:31.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:31.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:31.741 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:19:32.218 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:19:32.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:32.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:32.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:32.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:32.696 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:19:33.173 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:19:33.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:33.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:33.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:33.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:33.651 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:19:34.129 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:19:34.606 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:19:35.084 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:19:35.562 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:19:36.040 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:19:36.518 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:19:36.995 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:19:37.473 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:19:37.950 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:19:38.428 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:19:38.906 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:19:39.383 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:19:39.861 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:19:39.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:19:39.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:19:39.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:39.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:39.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:39.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:39.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:39.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:39.930 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:39.930 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:39.930 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:39.930 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:19:39.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:39.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:39.931 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2465 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:19:44.929 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:44.929 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:44.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:44.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:44.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:44.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:44.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:44.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:44.936 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:44.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:44.936 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:44.937 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:44.937 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:44.937 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:44.937 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:44.938 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:44.938 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:44.938 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:19:44.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:19:44.940 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:19:44.940 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:19:44.940 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:44.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:44.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:44.941 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:19:49.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:19:49.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:19:49.946 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:49.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:49.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:49.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:49.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:19:49.956 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:49.957 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:49.957 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:19:49.957 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:19:49.961 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:19:49.962 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:19:49.962 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:49.962 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:49.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:19:49.963 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:19:49.963 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:19:49.963 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:19:49.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:49.965 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:19:49.965 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:19:49.965 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:49.965 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:49.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:19:49.965 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:19:49.966 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:19:49.966 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:19:49.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:49.968 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:19:49.968 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:19:49.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:49.971 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:19:49.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:19:49.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:19:49.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:19:49.971 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:19:49.972 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:19:49.972 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:19:49.972 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:19:49.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:19:49.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:19:49.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:19:49.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:19:49.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:19:50.461 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:19:50.514 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:19:50.517 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:19:50.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:19:50.520 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:19:50.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:19:50.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:19:50.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:19:50.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:19:50.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:19:50.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:19:50.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:19:50.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:19:50.939 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:19:50.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:50.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:50.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:50.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:51.416 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:19:51.894 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:19:51.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:51.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:51.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:51.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:52.372 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:19:52.849 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:19:52.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:52.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:52.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:52.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:53.327 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:19:53.804 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:19:53.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:53.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:53.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:53.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:54.282 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:19:54.759 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:19:54.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:19:54.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:19:54.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:19:54.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:19:55.236 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:19:55.714 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:19:56.192 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:19:56.670 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:19:57.147 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:19:57.625 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:19:58.103 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:19:58.580 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:19:59.057 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:19:59.534 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:20:00.011 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:20:00.487 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:20:00.965 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:20:01.442 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:20:01.919 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:20:02.394 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:20:02.871 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:20:03.348 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:20:03.826 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:20:04.304 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:20:04.782 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:20:05.259 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:20:05.736 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:20:06.214 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:20:06.691 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:20:07.169 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:20:07.647 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:20:08.125 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:20:08.602 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:20:09.080 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:20:09.557 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:20:10.035 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:20:10.512 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:20:10.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:20:10.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:20:10.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:10.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:10.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:10.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:10.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:10.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:10.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:10.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:10.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:10.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:10.568 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:10.568 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:15.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:15.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:15.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:15.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:15.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:15.575 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:15.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:15.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:15.583 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:15.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:15.583 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:20:15.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:20:15.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:20:15.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:15.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:15.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:15.586 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:20:15.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:15.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:20:15.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:15.587 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:15.587 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:20:15.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:15.588 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:20:15.589 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:20:15.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:15.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:15.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:15.589 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:20:15.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:15.589 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:20:15.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.591 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:20:15.591 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:20:15.591 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:20:15.592 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:20:15.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:20:15.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:15.593 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:15.593 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:15.593 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:20:20.596 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:20.596 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:20.598 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:20.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:20.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:20.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:20.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:20.610 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:20.610 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:20.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:20.611 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:20:20.614 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:20:20.614 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:20:20.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:20.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:20.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:20.616 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:20:20.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:20.616 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:20:20.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:20.617 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:20:20.617 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:20:20.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:20.618 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:20.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:20.618 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:20:20.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:20.618 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:20:20.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:20.620 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:20.620 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:20:20.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.623 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:20:20.624 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:20:20.624 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:20:20.624 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:20.629 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:20:21.111 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:20:21.152 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:20:21.155 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:20:21.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:20:21.157 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:20:21.592 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:20:21.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:21.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:21.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:21.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:22.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:20:22.551 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:20:22.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:22.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:22.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:22.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:23.032 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:20:23.508 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:20:23.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:23.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:23.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:23.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:23.976 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:20:24.447 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:20:24.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:24.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:24.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:24.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:24.927 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:20:25.401 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:20:25.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:25.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:25.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:25.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:25.869 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:20:26.344 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:20:26.822 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:20:27.301 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:20:27.782 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:20:28.264 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:20:28.745 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:20:29.227 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:20:29.706 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:20:30.184 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:20:30.662 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:20:31.140 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:20:31.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:31.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:31.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:31.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:31.170 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:31.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:31.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:31.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:31.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:31.170 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:31.170 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2251 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:31.171 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2252 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:36.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:36.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:36.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:36.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:36.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:36.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:36.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:36.183 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:36.183 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:36.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:36.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:20:36.187 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:20:36.187 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:20:36.188 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:36.188 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:36.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:36.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:20:36.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:36.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:20:36.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:36.190 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:20:36.191 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:20:36.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:36.191 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:36.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:36.192 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:20:36.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:36.192 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:20:36.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:36.193 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:20:36.193 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:20:36.193 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:36.193 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:36.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:36.193 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:20:36.193 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:36.193 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:20:36.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:36.196 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:20:36.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:20:36.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:20:36.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:20:36.196 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:20:36.197 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:20:36.197 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:20:36.197 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:20:36.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:36.199 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:36.199 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:36.199 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:20:41.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:41.202 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:41.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:41.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:41.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:41.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:41.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:41.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:41.215 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:41.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:41.215 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:20:41.219 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:20:41.220 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:20:41.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:41.220 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:41.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:41.221 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:20:41.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:41.222 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:20:41.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:41.222 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:20:41.223 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:20:41.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:41.223 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:41.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:41.223 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:20:41.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:41.223 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:20:41.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:41.225 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:20:41.225 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:20:41.225 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:41.225 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:41.225 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:41.225 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:20:41.225 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:41.225 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:20:41.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:20:41.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:20:41.229 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:20:41.229 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:20:41.229 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:41.234 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:20:41.716 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:20:41.748 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:20:41.749 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:20:41.750 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:20:41.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:20:42.185 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:20:42.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:42.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:42.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:42.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:42.654 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:20:43.132 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:20:43.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:43.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:43.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:43.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:43.613 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:20:44.094 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:20:44.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:44.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:44.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:44.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:44.572 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:20:45.050 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:20:45.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:45.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:45.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:45.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:45.531 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:20:46.011 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:20:46.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:46.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:46.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:46.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:46.490 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:20:46.970 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:20:47.452 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:20:47.933 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:20:48.412 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:20:48.885 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:20:49.363 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:20:49.841 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:20:50.319 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:20:50.799 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:20:51.281 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:20:51.762 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:20:52.243 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:20:52.724 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:20:53.205 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:20:53.677 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:20:53.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:53.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:53.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:53.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:53.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:53.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:53.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:53.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:53.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:53.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:53.765 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2672 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:53.765 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2673 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:20:58.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:58.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:58.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:58.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:58.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:58.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:58.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:58.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:58.776 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:58.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:20:58.776 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:20:58.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:20:58.779 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:20:58.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:58.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:58.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:58.780 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:20:58.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:20:58.780 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:20:58.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:58.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:20:58.781 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:20:58.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:58.783 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:20:58.783 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:20:58.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.786 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:20:58.786 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:20:58.786 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:20:58.786 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:20:58.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:20:58.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:20:58.788 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:20:58.788 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:20:58.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:03.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:03.791 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:03.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:03.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:03.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:03.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:03.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:03.804 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:03.804 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:03.804 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:03.804 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:03.807 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:03.807 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:03.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:03.808 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:03.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:03.808 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:03.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:03.808 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:03.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:03.811 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:03.812 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:03.812 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:03.812 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:03.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:03.812 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:03.812 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:03.812 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:03.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:03.815 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:03.815 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:03.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:03.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:03.818 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:03.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:03.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:03.823 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:21:04.296 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:21:04.348 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:21:04.350 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:21:04.352 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:21:04.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:21:04.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:21:04.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:21:04.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:21:04.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:04.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:21:04.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:21:04.357 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:21:04.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:21:04.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:21:04.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:21:04.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:04.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:04.773 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:21:04.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:04.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:04.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:04.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:05.251 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:21:05.729 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:21:05.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:05.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:05.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:05.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:06.206 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:21:06.684 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:21:06.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:06.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:06.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:06.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:07.162 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:21:07.639 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:21:07.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:07.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:07.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:07.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:08.117 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:21:08.594 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:21:08.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:08.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:08.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:08.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:09.072 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:21:09.549 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:21:10.028 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:21:10.505 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:21:10.983 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:21:11.461 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:21:11.938 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:21:12.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:21:12.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:21:12.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:12.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:12.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:12.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:12.393 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:12.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:12.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:12.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:12.393 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:12.393 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:12.393 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:21:12.393 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:12.393 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:12.393 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:12.393 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:17.396 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:17.396 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:17.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:17.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:17.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:17.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:17.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:17.408 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:17.408 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:17.408 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:17.408 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:17.411 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:17.411 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:17.411 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:17.411 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:17.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:17.412 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:17.412 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:17.412 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:17.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:17.414 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:17.414 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:17.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:17.415 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:17.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:17.415 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:17.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:17.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:17.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:17.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:17.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:17.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:17.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:17.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:17.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:17.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:17.418 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:17.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.421 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:17.421 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:17.421 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:17.422 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:17.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:17.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:17.424 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:17.424 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:17.424 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:21:22.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:22.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:22.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:22.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:22.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:22.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:22.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:22.437 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:22.437 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:22.438 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:22.438 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:22.440 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:22.441 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:22.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:22.441 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:22.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:22.442 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:22.443 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:22.443 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:22.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:22.444 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:22.444 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:22.444 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:22.444 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:22.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:22.445 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:22.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:22.445 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:22.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:22.447 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:22.448 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:22.448 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:22.448 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:22.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:22.448 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:22.448 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:22.448 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:22.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:22.452 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:22.452 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:22.452 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:22.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:22.456 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:21:22.940 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:21:22.977 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:21:22.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:21:22.979 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:21:22.980 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:21:22.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:21:22.982 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:21:22.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:21:22.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:22.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:21:22.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:21:22.982 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:21:22.982 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:21:23.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:21:23.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:21:23.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:23.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:23.417 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:21:23.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:23.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:23.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:23.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:23.894 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:21:24.372 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:21:24.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:24.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:24.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:24.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:24.849 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:21:25.327 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:21:25.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:25.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:25.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:25.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:25.805 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:21:26.283 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:21:26.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:26.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:26.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:26.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:26.761 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:21:27.235 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:21:27.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:27.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:27.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:27.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:27.706 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:21:28.184 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:21:28.661 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:21:29.157 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:21:29.635 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:21:30.113 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:21:30.590 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:21:31.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:21:31.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:21:31.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:31.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:31.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:31.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:31.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:31.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:31.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:31.041 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:31.041 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:31.041 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:31.041 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:21:31.041 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:31.041 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:31.041 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:31.041 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:31.041 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:31.041 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:36.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:36.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:36.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:36.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:36.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:36.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:36.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:36.051 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:36.051 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:36.051 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:36.051 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:36.053 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:36.053 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:36.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:36.053 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:36.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:36.054 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:36.054 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:36.054 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:36.055 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:36.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:36.055 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:36.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:36.057 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:36.057 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:36.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:36.061 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:36.061 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:36.061 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:36.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:36.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:36.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:36.063 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:36.063 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:36.063 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:21:41.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:41.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:41.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:41.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:41.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:41.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:41.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:41.078 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:41.078 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:41.079 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:41.079 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:41.081 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:41.081 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:41.081 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:41.081 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:41.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:41.082 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:41.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:41.082 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:41.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:41.083 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:41.083 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:41.083 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:41.083 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:41.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:41.084 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:41.084 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:41.084 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:41.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:41.085 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:41.085 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:41.085 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:41.085 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:41.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:41.086 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:41.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:41.086 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:41.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:41.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:41.089 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:41.089 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:41.089 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:41.094 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:21:41.577 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:21:41.621 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:21:41.623 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:21:41.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:21:41.626 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:21:41.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:21:41.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:21:41.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:21:41.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:41.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:21:41.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:21:41.632 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:21:41.632 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:21:41.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:21:41.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:21:41.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:41.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:21:42.054 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:21:42.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:42.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:42.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:42.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:42.532 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:21:43.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:21:43.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:43.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:43.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:43.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:43.488 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:21:43.965 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:21:44.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:44.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:44.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:44.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:44.443 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:21:44.921 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:21:45.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:45.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:45.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:45.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:45.399 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:21:45.877 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:21:46.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:46.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:46.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:46.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:46.355 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:21:46.833 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:21:47.311 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:21:47.788 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:21:48.266 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:21:48.743 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:21:49.221 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:21:49.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:21:49.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:21:49.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:49.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:49.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:49.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:49.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:49.680 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:49.680 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:49.680 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:49.680 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:49.680 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:49.680 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:49.680 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:21:54.680 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:54.680 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:54.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:54.684 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:54.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:54.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:54.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:54.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:54.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:54.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:54.692 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:54.694 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:54.695 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:54.695 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:54.695 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:54.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:54.696 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:54.696 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:54.696 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:54.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:54.697 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:54.697 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:54.697 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:54.697 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:54.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:54.698 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:54.698 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:54.698 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:54.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:54.700 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:54.700 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:54.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:54.703 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:54.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:54.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:54.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:54.703 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:54.704 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:54.704 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:54.704 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:54.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:54.706 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:54.706 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:54.706 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:21:59.709 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:21:59.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:21:59.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:59.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:59.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:59.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:59.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:21:59.723 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:59.723 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:59.724 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:21:59.724 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:21:59.727 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:21:59.727 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:21:59.728 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:59.728 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:59.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:21:59.729 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:21:59.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:21:59.729 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:21:59.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:21:59.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:21:59.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:21:59.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:59.730 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:59.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:21:59.731 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:21:59.731 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:21:59.731 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:21:59.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:21:59.732 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:21:59.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:21:59.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:59.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:21:59.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:21:59.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:21:59.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:21:59.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:21:59.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.736 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:21:59.736 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:21:59.736 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:21:59.737 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:21:59.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:21:59.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:21:59.741 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:22:00.226 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:22:00.259 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:22:00.260 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:22:00.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:22:00.261 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:22:00.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:22:00.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:22:00.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:22:00.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:00.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:22:00.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:22:00.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:22:00.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:22:00.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:22:00.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:22:00.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:00.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:00.703 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:22:00.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:00.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:00.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:00.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:01.181 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:22:01.658 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:22:01.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:01.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:01.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:01.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:02.136 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:22:02.614 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:22:02.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:02.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:02.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:02.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:03.091 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:22:03.570 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:22:03.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:03.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:03.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:03.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:04.047 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:22:04.525 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:22:04.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:04.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:04.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:04.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:05.002 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:22:05.479 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:22:05.957 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:22:06.435 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:22:06.912 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:22:07.390 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:22:07.868 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:22:08.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:22:08.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:22:08.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:08.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:08.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:08.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:08.282 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:08.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:08.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:08.282 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:08.282 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:08.282 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:08.282 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:22:13.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:13.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:13.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:13.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:13.286 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:13.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:13.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:13.298 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:13.298 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:13.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:13.299 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:22:13.301 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:22:13.301 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:22:13.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:13.302 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:13.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:13.303 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:22:13.303 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:13.303 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:22:13.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:13.304 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:22:13.304 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:22:13.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:13.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:13.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:13.304 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:22:13.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:13.305 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:22:13.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:13.306 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:22:13.307 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:22:13.307 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:13.307 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:13.307 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:13.307 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:22:13.307 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:13.307 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:22:13.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.310 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:22:13.310 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:22:13.310 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:22:13.311 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:13.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:13.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:13.312 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:22:18.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:18.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:18.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:18.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:18.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:18.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:18.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:18.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:18.329 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:18.329 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:18.329 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:22:18.332 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:22:18.332 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:22:18.333 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:18.333 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:18.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:18.334 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:22:18.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:18.334 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:22:18.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:18.335 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:22:18.335 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:22:18.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:18.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:18.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:18.335 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:22:18.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:18.336 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:22:18.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:18.337 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:22:18.337 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:22:18.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:18.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:18.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:18.338 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:22:18.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:18.338 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:22:18.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:18.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:22:18.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:22:18.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:22:18.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:22:18.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:22:18.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:22:18.341 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:22:18.341 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:22:18.341 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:18.346 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:22:18.830 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:22:18.870 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:22:18.871 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:22:18.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:22:18.873 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:22:18.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:22:18.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:22:18.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:22:18.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:18.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:22:18.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:22:18.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:22:18.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:22:18.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:22:18.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:22:18.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:18.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:19.307 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:22:19.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:19.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:19.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:19.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:19.784 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:22:20.262 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:22:20.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:20.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:20.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:20.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:20.740 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:22:21.218 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:22:21.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:21.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:21.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:21.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:21.696 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:22:22.173 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:22:22.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:22.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:22.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:22.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:22.650 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:22:23.128 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:22:23.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:23.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:23.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:23.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:23.605 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:22:24.082 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:22:24.560 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:22:25.037 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:22:25.515 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:22:25.992 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:22:26.470 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:22:26.947 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:22:27.425 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:22:27.903 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:22:28.380 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:22:28.858 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:22:29.336 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:22:29.814 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:22:30.292 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:22:30.770 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:22:31.248 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:22:31.726 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:22:32.203 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:22:32.681 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:22:32.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:22:32.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:32.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:32.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:32.929 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:22:37.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:37.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:37.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:37.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:37.936 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:37.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:37.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:37.954 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:37.954 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:37.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:37.955 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:22:37.960 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:22:37.960 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:22:37.960 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:37.961 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:37.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:37.961 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:22:37.962 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:37.962 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:22:37.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:37.962 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:22:37.963 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:22:37.963 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:37.963 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:37.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:37.963 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:22:37.963 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:37.963 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:22:37.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:37.965 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:37.965 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:22:37.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:37.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:22:37.969 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:22:37.969 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:22:37.969 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:37.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:37.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:37.970 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:22:42.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:42.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:42.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:42.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:42.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:42.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:42.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:42.987 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:42.987 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:42.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:42.988 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:22:42.992 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:22:42.992 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:22:42.993 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:42.993 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:42.993 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:42.993 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:22:42.993 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:42.993 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:22:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:42.996 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:42.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:22:42.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:42.998 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:22:42.999 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:22:42.999 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:42.999 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:42.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:42.999 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:22:42.999 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:42.999 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:22:42.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:22:43.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:22:43.003 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:22:43.003 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:22:43.003 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:43.008 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:22:43.491 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:22:43.540 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:22:43.542 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:22:43.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:22:43.544 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:22:43.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:22:43.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:22:43.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:22:43.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:43.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:22:43.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:22:43.549 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:22:43.549 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:22:43.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:22:43.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:22:43.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:43.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:22:43.968 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:22:44.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:44.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:44.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:44.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:44.446 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:22:44.924 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:22:45.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:45.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:45.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:45.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:45.402 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:22:45.880 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:22:46.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:46.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:46.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:46.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:46.358 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:22:46.835 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:22:47.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:47.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:47.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:47.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:47.313 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:22:47.791 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:22:48.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:48.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:48.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:48.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:48.269 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:22:48.746 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:22:49.225 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:22:49.702 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:22:50.180 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:22:50.657 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:22:51.135 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:22:51.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:22:51.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:22:51.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:51.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:51.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:51.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:51.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:51.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:51.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:51.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:51.595 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:51.595 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:51.596 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:22:51.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:51.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:22:56.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:56.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:56.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:56.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:56.597 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:56.597 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:56.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:56.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:56.607 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:56.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:22:56.608 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:22:56.611 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:22:56.611 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:22:56.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:56.612 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:56.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:56.613 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:22:56.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:22:56.613 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:22:56.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:22:56.614 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:22:56.614 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:22:56.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:56.614 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:56.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:56.615 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:22:56.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:22:56.615 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:22:56.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:22:56.616 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:22:56.616 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:22:56.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:56.616 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:22:56.617 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:56.617 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:22:56.617 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:22:56.617 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:22:56.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:22:56.619 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:22:56.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:22:56.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:22:56.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:22:56.619 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:22:56.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:22:56.620 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:22:56.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:22:56.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:22:56.622 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:22:56.622 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:22:56.622 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:23:01.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:01.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:01.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:01.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:01.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:01.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:01.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:01.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:01.638 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:01.639 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:01.639 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:23:01.642 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:23:01.643 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:23:01.643 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:01.643 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:01.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:01.644 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:23:01.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:01.645 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:23:01.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:01.645 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:23:01.646 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:23:01.646 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:01.646 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:01.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:01.646 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:23:01.646 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:01.646 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:23:01.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:01.648 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:23:01.648 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:23:01.648 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:01.648 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:01.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:01.648 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:23:01.648 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:01.649 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:23:01.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:01.651 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:23:01.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:23:01.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:23:01.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:23:01.651 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:23:01.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:23:01.652 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:23:01.652 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:23:01.652 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:01.657 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:23:02.140 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:23:02.179 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:23:02.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:23:02.183 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:23:02.185 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:23:02.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:23:02.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:23:02.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:23:02.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:23:02.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:23:02.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:23:02.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:23:02.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:23:02.617 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:23:02.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:02.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:02.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:02.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:03.095 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:23:03.572 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:23:03.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:03.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:03.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:03.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:04.050 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:23:04.527 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:23:04.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:04.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:04.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:04.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:05.005 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:23:05.483 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:23:05.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:05.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:05.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:05.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:05.961 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:23:06.438 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:23:06.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:06.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:06.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:06.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:06.916 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:23:07.393 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:23:07.871 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:23:08.348 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:23:08.825 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:23:09.303 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:23:09.781 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:23:10.258 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:23:10.736 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:23:11.214 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:23:11.691 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:23:12.169 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:23:12.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:23:12.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:23:12.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:12.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:12.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:12.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:12.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:12.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:12.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:12.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:12.242 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:23:12.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:12.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:12.242 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:12.242 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:12.242 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:12.242 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:17.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:17.244 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:17.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:17.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:17.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:17.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:17.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:17.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:17.259 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:17.260 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:17.260 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:23:17.264 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:23:17.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:23:17.265 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:17.265 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:17.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:17.266 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:23:17.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:17.266 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:23:17.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:17.267 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:23:17.267 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:23:17.267 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:17.267 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:17.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:17.268 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:23:17.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:17.268 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:23:17.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:17.270 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:23:17.270 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:23:17.270 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:17.270 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:17.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:17.271 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:23:17.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:17.271 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:23:17.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:23:17.275 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:23:17.275 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:23:17.275 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:17.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:17.277 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:17.278 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:23:22.281 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:22.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:22.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:22.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:22.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:22.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:22.294 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:22.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:22.296 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:22.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:22.296 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:23:22.301 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:23:22.301 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:23:22.301 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:22.302 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:22.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:22.302 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:23:22.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:22.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:23:22.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:22.305 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:23:22.306 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:23:22.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:22.306 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:22.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:22.306 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:23:22.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:22.306 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:23:22.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:22.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:23:22.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:23:22.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:22.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:22.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:22.310 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:23:22.310 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:22.310 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:23:22.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:23:22.315 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:23:22.315 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:23:22.315 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:22.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:22.320 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:23:22.804 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:23:22.854 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:23:22.856 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:23:22.858 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:23:22.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:23:22.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:23:22.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:23:22.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:23:22.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:23:22.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:23:22.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:23:22.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:23:22.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:23:22.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:23:22.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:23:22.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:23:22.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:23:23.282 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:23:23.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:23.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:23.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:23.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:23.759 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:23:24.237 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:23:24.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:24.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:24.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:24.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:24.715 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:23:25.193 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:23:25.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:25.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:25.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:25.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:25.671 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:23:26.148 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:23:26.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:26.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:26.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:26.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:26.626 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:23:27.104 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:23:27.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:27.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:27.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:27.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:27.582 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:23:28.060 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:23:28.538 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:23:29.016 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:23:29.494 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:23:29.972 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:23:30.450 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:23:30.924 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:23:31.393 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:23:31.870 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:23:32.348 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:23:32.826 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:23:33.304 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:23:33.781 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:23:33.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:23:33.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:23:33.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:33.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:33.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:33.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:33.908 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:33.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:33.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:33.909 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:33.909 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:33.909 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:23:33.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:33.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:33.910 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2477 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:38.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:38.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:38.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:38.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:38.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:38.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:38.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:38.923 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:38.924 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:38.924 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:38.924 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:23:38.928 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:23:38.928 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:23:38.928 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:38.929 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:38.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:38.929 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:23:38.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:38.929 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:23:38.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:38.931 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:23:38.931 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:23:38.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:38.931 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:38.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:38.932 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:23:38.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:38.932 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:23:38.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:38.934 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:38.934 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:23:38.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:38.937 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:23:38.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:23:38.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:23:38.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:23:38.937 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:23:38.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:23:38.938 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:23:38.938 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:23:38.938 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:23:38.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:38.940 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:38.940 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:23:38.940 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:43.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:43.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:43.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:43.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:43.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:43.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:43.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:43.954 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:43.955 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:43.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:43.955 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:23:43.958 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:23:43.958 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:23:43.959 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:43.959 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:43.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:43.960 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:23:43.960 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:43.960 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:23:43.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:43.961 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:23:43.961 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:23:43.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:43.962 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:43.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:43.962 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:23:43.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:43.962 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:23:43.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:43.964 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:23:43.964 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:23:43.964 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:43.964 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:43.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:43.965 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:23:43.965 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:43.965 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:23:43.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.968 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:23:43.968 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:23:43.968 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:23:43.969 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:43.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:43.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:43.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:43.973 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:23:44.456 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:23:44.505 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:23:44.507 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:23:44.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:23:44.509 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:23:44.933 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:23:44.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:44.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:44.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:44.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:45.414 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:23:45.896 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:23:45.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:45.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:45.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:45.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:46.377 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:23:46.859 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:23:46.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:46.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:46.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:46.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:47.337 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:23:47.815 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:23:47.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:47.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:47.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:47.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:48.296 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:23:48.778 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:23:48.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:48.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:48.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:48.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:49.259 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:23:49.742 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:23:50.221 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:23:50.702 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:23:51.183 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:23:51.665 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:23:52.144 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:23:52.624 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:23:53.097 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:23:53.565 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:23:54.034 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:23:54.504 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:23:54.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:54.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:54.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:54.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:54.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:54.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:54.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:54.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:54.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:54.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:54.522 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:54.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2250 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:23:59.524 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:59.524 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:59.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:59.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:59.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:59.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:59.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:59.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:59.543 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:59.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:23:59.544 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:23:59.548 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:23:59.548 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:23:59.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:59.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:59.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:59.549 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:23:59.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:23:59.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:23:59.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:23:59.551 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:23:59.551 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:23:59.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:59.551 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:59.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:59.551 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:23:59.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:23:59.551 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:23:59.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:23:59.553 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:23:59.553 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:23:59.553 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:59.553 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:23:59.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:59.553 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:23:59.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:23:59.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:23:59.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:23:59.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:23:59.557 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:23:59.557 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:23:59.557 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:23:59.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:23:59.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:23:59.559 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:24:04.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:04.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:04.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:04.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:04.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:04.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:04.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:04.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:04.573 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:04.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:04.573 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:24:04.576 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:24:04.576 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:24:04.576 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:04.577 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:04.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:04.577 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:24:04.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:04.578 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:24:04.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:04.579 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:24:04.579 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:24:04.579 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:04.580 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:04.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:04.580 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:24:04.580 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:04.580 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:24:04.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:04.582 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:04.582 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:24:04.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:24:04.586 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:24:04.586 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:24:04.586 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:04.591 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:24:05.075 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:24:05.115 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:24:05.117 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:24:05.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:24:05.120 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:24:05.544 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:24:05.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:05.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:05.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:05.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:06.013 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:24:06.487 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:24:06.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:06.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:06.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:06.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:06.965 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:24:07.445 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:24:07.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:07.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:07.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:07.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:07.923 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:24:08.400 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:24:08.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:08.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:08.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:08.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:08.880 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:24:09.358 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:24:09.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:09.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:09.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:09.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:09.837 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:24:10.318 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:24:10.800 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:24:11.281 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:24:11.762 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:24:12.243 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:24:12.722 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:24:13.203 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:24:13.684 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:24:14.164 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:24:14.642 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:24:15.123 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:24:15.604 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:24:16.085 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:24:16.561 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:24:17.030 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:17.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:17.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:17.135 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:24:17.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:22.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:22.142 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:22.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:22.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:22.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:22.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:22.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:22.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:22.153 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:22.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:22.154 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:24:22.158 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:24:22.158 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:24:22.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:22.159 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:22.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:22.160 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:24:22.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:22.160 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:24:22.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:22.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:24:22.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:24:22.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:22.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:22.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:22.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:24:22.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:22.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:24:22.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:22.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:24:22.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:24:22.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:22.165 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:22.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:22.165 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:24:22.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:22.165 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:24:22.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:24:22.169 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:24:22.169 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:24:22.169 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:22.174 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:24:22.656 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:24:22.702 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:24:22.703 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:24:22.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:24:22.703 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:24:22.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:24:22.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:24:22.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:24:22.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:24:22.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:24:22.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:24:22.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:24:22.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:24:23.133 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:24:23.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:23.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:23.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:23.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:23.611 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:24:24.088 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:24:24.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:24.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:24.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:24.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:24.566 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:24:25.044 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:24:25.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:25.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:25.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:25.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:25.521 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:24:25.999 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:24:26.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:26.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:26.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:26.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:26.477 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:24:26.954 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:24:27.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:27.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:27.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:27.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:27.432 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:24:27.910 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:24:28.388 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:24:28.866 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:24:29.343 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:24:29.821 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:24:30.299 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:24:30.776 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:24:31.254 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:24:31.732 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:24:32.209 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:24:32.687 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:24:33.165 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:24:33.643 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:24:33.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:24:33.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:24:33.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:33.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:33.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:33.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:33.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:33.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:33.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:33.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:33.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:33.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:33.756 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:24:38.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:38.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:38.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:38.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:38.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:38.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:38.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:38.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:38.770 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:38.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:38.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:38.771 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:38.771 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:24:38.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:38.772 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:38.772 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:24:38.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:38.773 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:38.773 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:24:38.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:24:38.775 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:24:38.775 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:24:38.775 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:38.779 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:24:39.263 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:24:39.301 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:24:39.303 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:24:39.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:24:39.305 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:24:39.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:24:39.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:24:39.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:24:39.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:24:39.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:24:39.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:24:39.310 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:24:39.310 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:24:39.740 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:24:39.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:39.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:39.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:39.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:40.218 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:24:40.695 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:24:40.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:40.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:40.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:40.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:41.173 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:24:41.651 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:24:41.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:41.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:41.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:41.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:42.129 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:24:42.606 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:24:42.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:42.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:42.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:42.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:43.081 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:24:43.550 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:24:43.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:43.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:43.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:43.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:44.027 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:24:44.504 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:24:44.982 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:24:45.460 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:24:45.938 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:24:46.415 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:24:46.893 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:24:47.371 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:24:47.849 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:24:48.327 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:24:48.804 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:24:49.282 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:24:49.760 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:24:50.238 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:24:50.716 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:24:51.193 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:24:51.671 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:24:52.149 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:24:52.627 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:24:53.105 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:24:53.579 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:24:54.056 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:24:54.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:24:54.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:24:54.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:54.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:54.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:54.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:54.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:54.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:54.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:54.366 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:54.366 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:54.366 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:54.366 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3332 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:54.366 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3333 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:59.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:59.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:59.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:59.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:59.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:59.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:59.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:59.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:59.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:24:59.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:24:59.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:24:59.382 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:24:59.382 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:59.382 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:59.382 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:59.382 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:24:59.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:24:59.383 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:24:59.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:59.385 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:24:59.385 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:24:59.385 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:59.385 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:59.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:59.386 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:24:59.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:24:59.386 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:24:59.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:59.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:24:59.388 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:24:59.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:59.391 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:24:59.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:24:59.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:24:59.391 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.392 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:24:59.392 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:24:59.392 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:24:59.392 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:24:59.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:24:59.397 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:24:59.879 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:24:59.924 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:24:59.926 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:24:59.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:24:59.928 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:24:59.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:24:59.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:24:59.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:24:59.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:24:59.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:24:59.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:24:59.937 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:24:59.937 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:24:59.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:24:59.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:24:59.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:24:59.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:24:59.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:24:59.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:24:59.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:24:59.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:24:59.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:24:59.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:24:59.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:24:59.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:24:59.983 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:24:59.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:04.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:25:04.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:25:04.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:04.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:04.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:04.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:04.990 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:04.991 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:25:04.991 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:04.991 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:25:04.991 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:25:04.994 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:25:04.994 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:25:04.994 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:25:04.994 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:04.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:04.995 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:25:04.995 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:25:04.995 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:25:04.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:04.997 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:25:04.997 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:25:04.997 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:25:04.997 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:04.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:04.997 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:25:04.997 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:25:04.997 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:25:04.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:04.999 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:25:04.999 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:25:04.999 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:25:05.000 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:05.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:05.000 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:25:05.000 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:25:05.000 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:25:05.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:05.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:25:05.003 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:25:05.003 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:25:05.003 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:25:05.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:05.008 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:25:05.491 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:25:05.535 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:25:05.537 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:25:05.538 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:25:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:05.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:05.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:05.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:05.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:05.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:05.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:05.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:05.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:05.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:05.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:05.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:05.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:05.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:05.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:05.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:05.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:05.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:05.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:05.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:05.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:05.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:05.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:05.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:05.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:05.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:05.787 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:05.787 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:05.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:05.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:05.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:05.964 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:25:06.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:06.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:06.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:06.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:06.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:06.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:06.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:06.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:06.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:06.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:06.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:06.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:06.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:06.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:06.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:06.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:06.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:06.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:06.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:06.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:06.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:06.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:06.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:06.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:06.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.437 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:25:06.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:06.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:06.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:06.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:06.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:06.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:06.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:06.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:06.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:06.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:06.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:06.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:25:06.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:25:06.770 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:25:06.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:06.770 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.770 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=381 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:06.771 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:11.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:25:11.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:25:11.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:11.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:11.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:11.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:11.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:11.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:25:11.785 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:11.786 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:25:11.786 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:25:11.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:25:11.792 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:25:11.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:25:11.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:11.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:11.793 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:25:11.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:25:11.794 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:25:11.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:11.795 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:25:11.796 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:25:11.796 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:25:11.796 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:11.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:11.796 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:25:11.796 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:25:11.796 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:25:11.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:25:11.799 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:25:11.799 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:25:11.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:11.802 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:25:11.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.803 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:25:11.803 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:25:11.803 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:25:11.804 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:11.808 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:25:12.291 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:25:12.336 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:25:12.338 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:25:12.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:12.340 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:25:12.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:12.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:12.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:12.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:12.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:12.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:12.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:12.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:12.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:12.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:12.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:12.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:12.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:12.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:12.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:12.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:12.767 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:25:12.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:12.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:12.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:12.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:13.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:25:13.723 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:25:13.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:13.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:13.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:13.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:14.200 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:25:14.679 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:25:14.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:14.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:14.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:14.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:15.157 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:25:15.635 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:25:15.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:15.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:15.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:15.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:16.113 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:25:16.590 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:25:16.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:16.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:16.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:16.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:17.068 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:25:17.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:17.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:17.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:17.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:17.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:17.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:17.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:17.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:17.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:17.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:17.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:17.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:17.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:17.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:17.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:17.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:17.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:17.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:17.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:17.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:17.545 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:25:18.022 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:25:18.500 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:25:18.978 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:25:19.455 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:25:19.933 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:25:20.411 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:25:20.889 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:25:21.368 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:25:21.846 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:25:22.323 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:25:22.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:22.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:22.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:22.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:22.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:22.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:22.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:22.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:22.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:22.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:22.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:22.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:22.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:22.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:22.522 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:22.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:22.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:22.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:22.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:22.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:22.799 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:25:23.277 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:25:23.752 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:25:24.230 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:25:24.707 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:25:25.185 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:25:25.663 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:25:26.140 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:25:26.619 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:25:27.096 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:25:27.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:27.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:27.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:27.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:27.574 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:25:27.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:27.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:27.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:27.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:27.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:27.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:27.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:27.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:27.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:27.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:27.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:27.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:27.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:27.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:27.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:27.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:28.051 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:25:28.530 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:25:29.008 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:25:29.487 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:25:29.964 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:25:30.442 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:25:30.919 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:25:31.395 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:25:31.872 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:25:32.350 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:25:32.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:32.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:32.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:32.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:32.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:25:32.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:25:32.637 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:25:32.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4450 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:32.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4450 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:32.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4450 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:32.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4450 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:32.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4450 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:32.637 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4450 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:25:37.644 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:25:37.644 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:25:37.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:37.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:37.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:37.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:37.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:37.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:25:37.652 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:37.653 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:25:37.653 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:25:37.656 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:25:37.657 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:25:37.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:25:37.657 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:37.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:37.658 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:25:37.659 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:25:37.659 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:25:37.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:37.660 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:25:37.660 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:25:37.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:25:37.661 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:37.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:37.661 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:25:37.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:25:37.661 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:25:37.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:37.663 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:25:37.663 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:25:37.663 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:25:37.663 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:25:37.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:37.664 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:25:37.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:25:37.664 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:25:37.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.667 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:25:37.668 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:25:37.668 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:25:37.668 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:25:37.673 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:25:38.157 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:25:38.196 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:25:38.198 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:25:38.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:38.201 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:25:38.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:38.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:38.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:38.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:38.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:38.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:38.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:38.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:38.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:38.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:38.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:38.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:38.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:38.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:38.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:38.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:38.633 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:25:38.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:38.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:38.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:38.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:39.112 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:25:39.590 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:25:39.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:39.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:39.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:39.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:40.068 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:25:40.546 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:25:40.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:40.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:40.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:40.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:41.024 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:25:41.502 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:25:41.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:41.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:41.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:41.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:41.980 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:25:42.458 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:25:42.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:42.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:42.676 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:42.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:42.935 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:25:43.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:43.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:43.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:43.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:43.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:43.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:43.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:43.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:43.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:43.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:43.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:43.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:43.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:43.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:43.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:43.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:43.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:43.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:43.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:43.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:43.412 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:25:43.890 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:25:44.368 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:25:44.847 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:25:45.325 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:25:45.802 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:25:46.280 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:25:46.758 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:25:47.236 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:25:47.715 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:25:48.193 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:25:48.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:48.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:48.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:48.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:48.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:48.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:48.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:48.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:48.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:48.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:48.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:48.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:48.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:48.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:48.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:48.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:48.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:48.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:48.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:48.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:48.669 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:25:49.146 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:25:49.624 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:25:50.102 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:25:50.580 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:25:51.057 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:25:51.535 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:25:52.012 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:25:52.490 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:25:52.968 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:25:53.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:53.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:53.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:53.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:53.445 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:25:53.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:53.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:53.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:53.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:53.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:53.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:25:53.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:53.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:53.456 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:53.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:53.456 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:25:53.456 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:25:53.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:25:53.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:25:53.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:53.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:53.921 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:25:54.399 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:25:54.877 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:25:55.352 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:25:55.829 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:25:56.307 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:25:56.785 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:25:57.263 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:25:57.741 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:25:58.220 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:25:58.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:25:58.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:25:58.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:25:58.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:25:58.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:25:58.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:25:58.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:25:58.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:25:58.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:25:58.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:25:58.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:25:58.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:25:58.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:25:58.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:25:58.509 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:26:03.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:26:03.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:26:03.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:03.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:03.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:03.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:03.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:03.528 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:26:03.528 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:03.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:26:03.529 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:26:03.531 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:26:03.531 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:26:03.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:26:03.531 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:03.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:03.531 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:26:03.532 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:26:03.532 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:26:03.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:03.533 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:26:03.534 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:26:03.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:26:03.534 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:03.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:03.534 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:26:03.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:26:03.534 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:26:03.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:03.535 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:26:03.535 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:26:03.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:26:03.535 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:03.535 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:26:03.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:03.536 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:26:03.536 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:26:03.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:03.537 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:26:03.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:26:03.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:26:03.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:26:03.537 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:26:03.538 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:26:03.538 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:26:03.538 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:03.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:03.543 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:26:04.023 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:26:04.063 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:26:04.065 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:26:04.067 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:26:04.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:04.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:04.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:04.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:04.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:04.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:04.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:04.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:04.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:04.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:04.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:04.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:04.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:04.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:04.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:04.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:04.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:04.499 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:26:04.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:04.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:04.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:04.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:04.977 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:26:05.455 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:26:05.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:05.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:05.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:05.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:05.933 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:26:06.410 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:26:06.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:06.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:06.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:06.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:06.888 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:26:07.366 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:26:07.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:07.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:07.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:07.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:07.844 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:26:08.322 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:26:08.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:08.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:08.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:08.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:08.799 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:26:09.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:09.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:09.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:09.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:09.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:09.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:09.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:09.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:09.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:09.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:09.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:09.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:09.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:09.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:09.196 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:09.196 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:09.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:09.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:09.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:09.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:09.276 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:26:09.755 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:26:10.233 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:26:10.711 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:26:11.189 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:26:11.667 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:26:12.145 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:26:12.623 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:26:13.100 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:26:13.573 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:26:14.044 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:26:14.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:14.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:14.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:14.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:14.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:14.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:14.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:14.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:14.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:14.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:14.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:14.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:14.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:14.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:14.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:14.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:14.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:14.276 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:14.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:14.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:14.518 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:26:14.995 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:26:15.473 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:26:15.951 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:26:16.429 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:26:16.907 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:26:17.384 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:26:17.862 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:26:18.340 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:26:18.817 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:26:19.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:19.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:19.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:19.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:19.294 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:26:19.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:19.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:19.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:19.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:19.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:19.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:19.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:19.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:19.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:19.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:19.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:19.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:19.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:19.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:19.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:19.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:19.769 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:26:20.247 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:26:20.725 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:26:21.204 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:26:21.681 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:26:22.159 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:26:22.637 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:26:23.115 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:26:23.592 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:26:24.070 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:26:24.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:24.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:24.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:24.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:24.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:24.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:24.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:24.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:24.364 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:24.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:24.364 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:26:24.364 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:26:24.364 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:26:24.364 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:24.364 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:24.364 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:24.364 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:24.364 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:24.364 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:24.364 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:24.364 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:24.365 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4451 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:29.364 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:26:29.364 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:26:29.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:29.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:29.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:29.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:29.377 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:29.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:26:29.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:29.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:26:29.380 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:26:29.383 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:26:29.384 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:26:29.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:26:29.384 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:29.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:29.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:26:29.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:26:29.386 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:26:29.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:29.387 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:26:29.387 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:26:29.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:26:29.387 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:29.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:29.387 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:26:29.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:26:29.388 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:26:29.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:29.390 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:26:29.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:26:29.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:26:29.390 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:29.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:29.390 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:26:29.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:26:29.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:26:29.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:29.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:26:29.395 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:26:29.395 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:26:29.395 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:29.400 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:26:29.882 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:26:29.921 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:26:29.922 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:26:29.922 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:26:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:29.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:29.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:29.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:29.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:29.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:29.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:29.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:29.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:29.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:29.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:29.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:29.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:29.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:29.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:29.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:29.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:30.360 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:26:30.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:30.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:30.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:30.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:30.838 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:26:31.316 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:26:31.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:31.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:31.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:31.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:31.793 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:26:32.271 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:26:32.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:32.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:32.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:32.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:32.749 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:26:33.227 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:26:33.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:33.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:33.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:33.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:33.705 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:26:34.183 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:26:34.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:34.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:34.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:34.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:34.660 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:26:34.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:34.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:34.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:34.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:35.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:35.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:35.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:35.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:35.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:35.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:35.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:35.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:35.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:35.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:35.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:35.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:35.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:35.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:35.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:35.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:35.138 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:26:35.616 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:26:36.094 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:26:36.572 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:26:37.050 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:26:37.528 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:26:38.006 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:26:38.484 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:26:38.962 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:26:39.440 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:26:39.918 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:26:40.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:40.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:40.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:40.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:40.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:40.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:40.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:40.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:40.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:40.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:40.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:40.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:40.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:40.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:40.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:40.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:40.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:40.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:40.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:40.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:40.394 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:26:40.872 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:26:41.349 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:26:41.827 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:26:42.305 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:26:42.783 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:26:43.261 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:26:43.739 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:26:44.216 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:26:44.694 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:26:45.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:45.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:45.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:45.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:45.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:45.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:45.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:45.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:45.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:45.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:45.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:45.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:45.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:45.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:45.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:45.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:45.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:45.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:45.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:45.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:45.171 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:26:45.649 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:26:46.126 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:26:46.604 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:26:47.083 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:26:47.560 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:26:48.038 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:26:48.516 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:26:48.993 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:26:49.471 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:26:49.949 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:26:50.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:50.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:50.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:50.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:50.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:50.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:50.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:50.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:50.189 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:50.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:50.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:50.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:50.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:26:50.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:26:50.190 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:26:50.190 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.190 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:50.191 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4439 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:55.189 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:26:55.189 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:26:55.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:55.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:55.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:55.193 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:55.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:55.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:26:55.197 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:55.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:26:55.198 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:26:55.199 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:26:55.200 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:26:55.200 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:26:55.200 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:55.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:55.201 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:26:55.201 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:26:55.201 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:26:55.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:26:55.202 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:26:55.202 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:26:55.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:26:55.204 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:26:55.204 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:26:55.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.207 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:26:55.207 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:26:55.207 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:26:55.208 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:26:55.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:26:55.212 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:26:55.695 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:26:55.741 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:26:55.744 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:26:55.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:55.746 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:26:55.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:55.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:55.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:55.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:55.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:55.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:55.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:55.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:55.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:55.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:55.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:55.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:55.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:55.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:55.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:55.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:56.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:56.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:56.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:56.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:56.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:56.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:56.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:56.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:56.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:56.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:56.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:56.103 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:56.103 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:56.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:56.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:56.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.172 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:26:56.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:56.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:56.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:56.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:56.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:56.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:56.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:56.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:56.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:56.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:56.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:56.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:56.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:56.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:56.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:56.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:56.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:56.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:56.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:56.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:56.648 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:26:57.126 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:26:57.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:57.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:57.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:57.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:57.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:57.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:57.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:57.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:57.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:57.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:57.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:57.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:57.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:57.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:26:57.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:57.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:57.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:57.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:57.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:26:57.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:26:57.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:26:57.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:26:57.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:57.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:57.601 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:26:58.079 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:26:58.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:26:58.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:26:58.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:26:58.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:26:58.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:26:58.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:26:58.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:26:58.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:26:58.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:26:58.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:26:58.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:26:58.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:26:58.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:26:58.181 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:26:58.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:26:58.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=635 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:26:58.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=636 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:27:03.180 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:27:03.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:27:03.182 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:27:03.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:27:03.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:27:03.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:27:03.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:27:03.195 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:27:03.195 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:27:03.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:27:03.196 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:27:03.198 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:27:03.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:27:03.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:27:03.201 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:27:03.201 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:27:03.201 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:27:03.201 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:27:03.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:27:03.202 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:27:03.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:27:03.202 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:27:03.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:27:03.203 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:27:03.203 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:27:03.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:27:03.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:27:03.206 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:27:03.206 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:27:03.206 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:27:03.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:27:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:27:03.210 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:27:03.693 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:27:03.731 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:27:03.733 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:27:03.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:27:03.736 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:27:03.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:03.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:03.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:27:03.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:03.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:03.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:27:03.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:27:03.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:03.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:27:03.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:27:03.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:27:03.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:27:03.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:27:03.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:27:03.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:03.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:04.169 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:27:04.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:27:04.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:27:04.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:27:04.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:27:04.642 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:27:05.120 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:27:05.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:27:05.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:27:05.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:27:05.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:27:05.598 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:27:06.076 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:27:06.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:27:06.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:27:06.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:27:06.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:27:06.554 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:27:07.032 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:27:07.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:27:07.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:27:07.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:27:07.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:27:07.510 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:27:07.988 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:27:08.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:27:08.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:27:08.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:27:08.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:27:08.465 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:27:08.943 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:27:09.420 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:27:09.898 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:27:10.375 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:27:10.853 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:27:11.331 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:27:11.809 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:27:12.287 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:27:12.765 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:27:13.243 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:27:13.721 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:27:14.199 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:27:14.677 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:27:15.155 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:27:15.633 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:27:16.111 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:27:16.589 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:27:17.067 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:27:17.545 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:27:18.023 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:27:18.501 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:27:18.978 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:27:19.456 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:27:19.934 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:27:20.411 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:27:20.889 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:27:21.367 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:27:21.845 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:27:22.323 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:27:22.801 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:27:23.279 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:27:23.755 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:27:23.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:23.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:27:23.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:23.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:23.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:23.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:23.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:27:23.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:23.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:23.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:27:23.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:27:23.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:23.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:27:23.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:27:23.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:27:23.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:27:23.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:27:23.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:27:23.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:23.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:24.230 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:27:24.708 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:27:25.187 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:27:25.665 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:27:26.143 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:27:26.620 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:27:27.098 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:27:27.577 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:27:28.054 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:27:28.533 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:27:29.011 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:27:29.489 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:27:29.968 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:27:30.446 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:27:30.924 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:27:31.402 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:27:31.879 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:27:32.356 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:27:32.834 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:27:33.312 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:27:33.790 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:27:34.268 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:27:34.746 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:27:35.224 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:27:35.702 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:27:36.181 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:27:36.659 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:27:37.138 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:27:37.616 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:27:38.094 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:27:38.571 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:27:39.049 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:27:39.528 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:27:40.005 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:27:40.483 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:27:40.961 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:27:41.439 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:27:41.917 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:27:42.395 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:27:42.873 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:27:43.351 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:27:43.829 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:27:43.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:43.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:27:43.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:43.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:43.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:43.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:43.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:27:43.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:27:43.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:27:43.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:27:43.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:27:43.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:43.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:27:43.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:27:43.928 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:27:43.928 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:27:43.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:27:43.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:27:43.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:43.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:27:44.306 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:27:44.783 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:27:45.260 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:27:45.738 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:27:46.216 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:27:46.694 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:27:47.171 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:27:47.649 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:27:48.127 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:27:48.604 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:27:49.082 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:27:49.560 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:27:50.038 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:27:50.515 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:27:50.993 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:27:51.471 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 02:27:51.949 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 02:27:52.426 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 02:27:52.904 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 02:27:53.382 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 02:27:53.859 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 02:27:54.337 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 02:27:54.814 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 02:27:55.292 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 02:27:55.769 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 02:27:56.247 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 02:27:56.725 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 02:27:57.202 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 02:27:57.680 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 02:27:58.155 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 02:27:58.633 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 02:27:59.111 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 02:27:59.588 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 02:28:00.066 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 02:28:00.544 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 02:28:01.022 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 02:28:01.500 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 02:28:01.978 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 02:28:02.450 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 02:28:02.920 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 02:28:03.392 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 02:28:03.863 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 02:28:03.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:03.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:03.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:03.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:03.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:03.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:03.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:03.982 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:03.982 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:03.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:03.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:03.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:03.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:03.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:03.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:03.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:03.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:03.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:03.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:03.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:04.334 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 02:28:04.806 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 02:28:05.284 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 02:28:05.762 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 02:28:06.237 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 02:28:06.712 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 02:28:07.186 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 02:28:07.664 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 02:28:08.141 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 02:28:08.618 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 02:28:09.096 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 02:28:09.573 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 02:28:10.051 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 02:28:10.528 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 02:28:11.006 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 02:28:11.484 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 02:28:11.962 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 02:28:12.440 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 02:28:12.917 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 02:28:13.396 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 02:28:13.874 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 02:28:14.352 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 02:28:14.830 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 02:28:15.308 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 02:28:15.785 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 02:28:16.263 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 02:28:16.742 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 02:28:17.219 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 02:28:17.696 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 02:28:18.174 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 02:28:18.652 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 02:28:19.131 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 02:28:19.608 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 02:28:20.085 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 02:28:20.564 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 02:28:21.042 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 02:28:21.520 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 02:28:21.998 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 02:28:22.475 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 02:28:22.953 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 02:28:23.430 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 02:28:23.908 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 02:28:23.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:23.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:24.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:24.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:24.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:24.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:24.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:24.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:24.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:24.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:24.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:24.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:24.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:28:24.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:28:24.019 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:24.019 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17264 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:29.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:28:29.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:28:29.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:29.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:29.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:29.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:29.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:29.029 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:28:29.029 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:29.030 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:28:29.030 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:28:29.032 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:28:29.032 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:28:29.033 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:28:29.033 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:29.033 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:29.034 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:28:29.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:28:29.034 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:28:29.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:28:29.035 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:28:29.035 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:28:29.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:29.037 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:28:29.037 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:28:29.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:28:29.037 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:29.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:29.037 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:28:29.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:28:29.037 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:28:29.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:28:29.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:28:29.041 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:28:29.041 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:29.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:28:29.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:28:29.043 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:28:34.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:28:34.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:28:34.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:34.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:34.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:34.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:34.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:34.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:28:34.060 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:34.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:28:34.061 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:28:34.065 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:28:34.065 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:28:34.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:28:34.066 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:34.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:34.067 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:28:34.067 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:28:34.067 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:28:34.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:34.068 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:28:34.069 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:28:34.069 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:28:34.069 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:34.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:34.069 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:28:34.069 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:28:34.069 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:28:34.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:28:34.072 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:28:34.072 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:28:34.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:28:34.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:28:34.076 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:28:34.076 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:28:34.076 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:34.081 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:28:34.563 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:28:34.610 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:28:34.612 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:28:34.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:34.615 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:28:34.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:34.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:34.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:34.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:34.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:34.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:34.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:34.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:34.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:34.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:34.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:34.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:34.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:34.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:34.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:34.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:34.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:34.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:34.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:34.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:34.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:34.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:34.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:34.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:34.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:34.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:34.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:34.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:34.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:34.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:34.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:34.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:34.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.040 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:28:35.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:35.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:35.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:35.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:35.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:35.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:35.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:35.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:35.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:35.167 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:35.167 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:35.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:35.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:35.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:35.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:35.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:35.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:35.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:35.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:35.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:35.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:35.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:35.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:35.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.513 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:28:35.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:35.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:35.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:35.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:35.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:35.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:35.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:35.787 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:35.787 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:35.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:35.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:35.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:35.990 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:28:36.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:36.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:36.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:36.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:36.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:36.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:36.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:36.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:36.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:36.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:36.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:36.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:36.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:36.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:36.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:36.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:36.124 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:36.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:36.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:36.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:36.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:36.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:36.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:36.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:36.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:36.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:36.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:36.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:36.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:36.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:36.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:36.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:36.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:36.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:36.464 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:28:36.941 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:28:37.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:37.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:37.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:37.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:37.419 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:28:37.896 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:28:38.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:38.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:38.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:38.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:38.374 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:28:38.851 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:28:39.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:39.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:39.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:39.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:39.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:39.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:39.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:39.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:39.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:39.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:39.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:39.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:39.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:39.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:39.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:39.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:39.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:39.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:39.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:39.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:39.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:39.328 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:28:39.806 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:28:40.284 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:28:40.761 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:28:41.239 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:28:41.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:41.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:41.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:41.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:41.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:41.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:41.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:41.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:41.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:41.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:41.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:41.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:41.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:41.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:41.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:41.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:41.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:41.717 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:28:42.195 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:28:42.673 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:28:43.150 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:28:43.628 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:28:44.106 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:28:44.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:44.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:44.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:44.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:44.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:44.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:44.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:44.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:44.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:44.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:44.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:44.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:44.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:44.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:44.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:44.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:44.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:44.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:44.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:44.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:44.583 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:28:45.061 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:28:45.539 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:28:46.017 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:28:46.495 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:28:46.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:46.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:46.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:46.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:46.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:46.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:46.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:46.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:46.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:46.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:46.839 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:46.839 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:46.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:46.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:46.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:46.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:46.973 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:28:47.451 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:28:47.929 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:28:48.406 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:28:48.885 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:28:49.363 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:28:49.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:49.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:49.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:49.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:49.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:49.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:49.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:49.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:49.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:49.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:49.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:49.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:49.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:49.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:49.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:49.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:49.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:49.838 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:28:50.316 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:28:50.793 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:28:51.272 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:28:51.749 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:28:52.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:52.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:52.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:52.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:52.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:52.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:52.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:52.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:52.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:52.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:52.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:52.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:52.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:28:52.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:28:52.085 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:52.085 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3848 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:28:57.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:28:57.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:28:57.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:57.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:57.089 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:57.089 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:57.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:28:57.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:28:57.099 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:57.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:28:57.100 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:28:57.102 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:28:57.102 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:28:57.103 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:28:57.103 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:57.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:28:57.104 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:28:57.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:28:57.104 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:28:57.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:57.106 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:28:57.106 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:28:57.106 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:28:57.106 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:57.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:28:57.107 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:28:57.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:28:57.107 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:28:57.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:57.108 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:28:57.108 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:28:57.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:28:57.109 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:28:57.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:28:57.109 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:28:57.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:28:57.109 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:28:57.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.112 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:28:57.112 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:28:57.113 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:28:57.113 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:28:57.117 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:28:57.601 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:28:57.639 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:28:57.640 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:28:57.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:57.643 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:28:57.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:57.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:57.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:57.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:28:57.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:28:57.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:28:57.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:28:57.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:57.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:57.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:57.691 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:28:57.691 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:28:57.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:28:57.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:28:57.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:57.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:28:58.078 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:28:58.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:58.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:58.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:58.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:58.556 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:28:59.034 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:28:59.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:28:59.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:28:59.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:28:59.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:28:59.512 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:28:59.990 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:29:00.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:00.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:00.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:00.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:00.467 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:29:00.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:00.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:00.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:00.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:00.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:00.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:00.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:00.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:00.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:00.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:00.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:00.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:00.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:00.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:00.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:00.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:00.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:00.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:00.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:00.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:00.944 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:29:01.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:01.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:01.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:01.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:01.422 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:29:01.899 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:29:02.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:02.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:02.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:02.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:02.376 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:29:02.854 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:29:03.332 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:29:03.809 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:29:04.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:04.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:04.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:04.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:04.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:04.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:04.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:04.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:04.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:04.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:04.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:04.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:04.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:04.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:04.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:04.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:04.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:04.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:04.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:04.285 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:29:04.762 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:29:05.239 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:29:05.717 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:29:06.192 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:29:06.670 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:29:07.147 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:29:07.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:07.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:07.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:07.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:07.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:07.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:07.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:07.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:07.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:07.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:07.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:07.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:07.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:07.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:07.307 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:07.307 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:07.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:07.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:07.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:07.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:07.624 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:29:08.101 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:29:08.579 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:29:09.057 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:29:09.535 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:29:10.012 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:29:10.490 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:29:10.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:10.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:10.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:10.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:10.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:10.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:10.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:10.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:10.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:10.555 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:10.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:10.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:10.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:10.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:10.556 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:10.556 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2872 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:15.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:15.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:15.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:15.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:15.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:15.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:15.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:15.569 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:15.569 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:15.570 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:15.570 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:29:15.574 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:29:15.574 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:29:15.574 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:15.574 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:15.575 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:15.575 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:29:15.575 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:15.575 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:29:15.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:15.577 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:29:15.578 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:29:15.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:15.578 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:15.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:15.578 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:29:15.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:15.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:29:15.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:15.580 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:29:15.580 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:29:15.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:15.581 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:15.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:15.581 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:29:15.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:15.581 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:29:15.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:29:15.585 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:29:15.585 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:29:15.585 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:15.590 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:29:16.074 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:29:16.113 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:29:16.116 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:29:16.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:16.118 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:29:16.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:16.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:16.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:16.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:16.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:16.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:16.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:16.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:16.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:16.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:16.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:16.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:16.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:16.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:16.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:16.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:16.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:16.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:16.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:16.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:16.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:16.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:16.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:16.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:16.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:16.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:16.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:16.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:16.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:16.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:16.549 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:29:16.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:16.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:16.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:16.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:17.027 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:29:17.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:17.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:17.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:17.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:17.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:17.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:17.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:17.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:17.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:17.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:17.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:17.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:17.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:17.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:17.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:17.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:17.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:17.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:17.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:17.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:17.504 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:29:17.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:17.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:17.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:17.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:17.982 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:29:18.459 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:29:18.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:18.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:18.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:18.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:18.938 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:29:19.415 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:29:19.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:19.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:19.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:19.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:19.893 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:29:20.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:20.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:20.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:20.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:20.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:20.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:20.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:20.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:20.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:20.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:20.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:20.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:20.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:20.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:20.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:20.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:20.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:20.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:20.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:20.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:20.370 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:29:20.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:20.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:20.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:20.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:20.848 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:29:21.326 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:29:21.803 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:29:22.280 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:29:22.759 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:29:23.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:23.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:23.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:23.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:23.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:23.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:23.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:23.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:23.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:23.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:23.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:23.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:23.096 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:23.096 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:23.096 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:29:23.096 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:23.097 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:28.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:28.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:28.096 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:28.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:28.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:28.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:28.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:28.108 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:28.108 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:28.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:28.109 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:29:28.112 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:29:28.112 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:29:28.113 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:28.113 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:28.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:28.114 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:29:28.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:28.114 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:29:28.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:28.115 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:29:28.115 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:29:28.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:28.116 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:28.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:28.116 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:29:28.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:28.116 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:29:28.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:28.118 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:28.118 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:29:28.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:29:28.122 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:29:28.122 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:29:28.122 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:28.127 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:29:28.607 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:29:28.642 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:29:28.643 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:29:28.643 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:29:28.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:28.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:28.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:28.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:28.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:28.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:28.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:28.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:28.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:28.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:28.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:28.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:28.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:28.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:28.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:28.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:28.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:29.083 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:29:29.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:29.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:29.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:29.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:29.562 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:29:29.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:29.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:29.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:29.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:30.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:30.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:30.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:30.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:30.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:30.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:30.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:30.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:30.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:30.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:30.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:30.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:30.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:30.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:30.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:30.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:30.039 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:29:30.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:30.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:30.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:30.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:30.516 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:29:30.994 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:29:31.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:31.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:31.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:31.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:31.472 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:29:31.949 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:29:32.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:32.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:32.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:32.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:32.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:32.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:32.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:32.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:32.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:32.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:32.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:32.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:32.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:32.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:32.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:32.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:32.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:32.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:32.222 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:32.222 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:32.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:32.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:32.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:32.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:32.427 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:29:32.905 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:29:33.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:33.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:33.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:33.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:33.383 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:29:33.861 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:29:34.338 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:29:34.815 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:29:35.294 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:29:35.772 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:29:36.250 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:29:36.727 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:29:37.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:37.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:37.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:37.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:37.205 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:29:37.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:37.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:37.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:37.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:37.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:37.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:37.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:37.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:37.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:37.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:37.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:37.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:37.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:37.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:37.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:37.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:37.681 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:29:38.159 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:29:38.636 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:29:39.114 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:29:39.592 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:29:40.070 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:29:40.548 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:29:41.026 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:29:41.504 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:29:41.982 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:29:42.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:42.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:42.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:42.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:42.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:42.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:42.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:42.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:42.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:42.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:42.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:42.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:42.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:42.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:42.153 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:42.153 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2997 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:29:47.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:47.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:47.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:47.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:47.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:47.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:47.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:47.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:47.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:47.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:47.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:29:47.165 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:29:47.165 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:29:47.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:47.166 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:47.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:47.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:29:47.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:47.167 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:29:47.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:47.168 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:29:47.168 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:29:47.168 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:47.168 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:47.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:47.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:29:47.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:47.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:29:47.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:47.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:47.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:29:47.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:47.174 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:29:47.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:29:47.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:29:47.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:29:47.174 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:29:47.175 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:29:47.175 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:29:47.175 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:47.180 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:29:47.661 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:29:47.698 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:29:47.700 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:29:47.702 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:29:47.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:47.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:47.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:47.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:47.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:47.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:47.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:47.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:47.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:47.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:47.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:47.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:47.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:47.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:47.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:47.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:47.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:48.135 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:29:48.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:48.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:48.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:48.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:48.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:48.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:48.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:48.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:48.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:48.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:48.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:48.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:48.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:48.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:48.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:48.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:48.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:48.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:48.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:48.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:48.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:48.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:48.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:48.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:48.611 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:29:49.090 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:29:49.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:49.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:49.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:49.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:49.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:49.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:49.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:49.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:49.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:49.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:49.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:49.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:49.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:49.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:49.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:49.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:49.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:49.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:49.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:49.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:49.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:49.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:49.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:49.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:49.567 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:29:50.044 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:29:50.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:50.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:50.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:50.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:50.522 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:29:51.000 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:29:51.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:51.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:51.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:51.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:51.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:51.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:51.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:51.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:51.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:51.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:51.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:51.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:51.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:51.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:51.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:51.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:51.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:51.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:51.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:51.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:51.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:51.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:51.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:51.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:51.477 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:29:51.954 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:29:52.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:52.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:52.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:52.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:52.432 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:29:52.910 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:29:53.388 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:29:53.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:53.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:53.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:53.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:53.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:53.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:53.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:53.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:53.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:53.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:53.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:53.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:53.484 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:53.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:53.484 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:29:58.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:29:58.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:29:58.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:58.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:58.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:58.489 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:58.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:29:58.496 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:58.496 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:58.496 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:29:58.497 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:29:58.499 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:29:58.499 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:29:58.499 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:58.499 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:58.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:29:58.500 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:29:58.500 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:29:58.500 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:29:58.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:58.502 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:29:58.502 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:29:58.502 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:58.502 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:58.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:29:58.502 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:29:58.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:29:58.503 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:29:58.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:58.504 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:29:58.504 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:29:58.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:58.504 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:29:58.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:29:58.505 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:29:58.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:29:58.505 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:29:58.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:29:58.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:29:58.509 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:29:58.509 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:29:58.509 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:29:58.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:29:58.514 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:29:58.998 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:29:59.046 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:29:59.048 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:29:59.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:59.050 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:29:59.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:59.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:59.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:59.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:29:59.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:29:59.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:29:59.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:29:59.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:59.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:59.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:59.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:29:59.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:29:59.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:29:59.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:29:59.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:59.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:29:59.475 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:29:59.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:29:59.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:29:59.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:29:59.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:29:59.953 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:30:00.430 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:30:00.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:00.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:00.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:00.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:00.908 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:30:01.386 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:30:01.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:01.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:01.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:01.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:01.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:01.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:01.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:01.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:01.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:01.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:01.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:01.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:01.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:01.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:01.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:01.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:01.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:01.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:01.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:01.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:01.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:01.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:01.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:01.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:01.862 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:30:02.340 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:30:02.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:02.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:02.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:02.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:02.818 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:30:03.296 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:30:03.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:03.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:03.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:03.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:03.774 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:30:04.252 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:30:04.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:04.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:04.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:04.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:04.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:04.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:04.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:04.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:04.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:04.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:04.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:04.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:04.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:04.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:04.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:04.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:04.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:04.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:04.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:04.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:04.727 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:30:05.205 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:30:05.682 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:30:06.159 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:30:06.637 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:30:07.115 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:30:07.592 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:30:07.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:07.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:07.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:07.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:07.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:07.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:07.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:07.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:07.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:07.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:07.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:07.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:07.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:07.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:07.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:07.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:07.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:07.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:07.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:07.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:08.067 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:30:08.541 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:30:09.018 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:30:09.496 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:30:09.969 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:30:10.447 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:30:10.924 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:30:11.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:11.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:11.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:11.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:11.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:11.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:11.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:11.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:11.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:30:11.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:30:11.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:30:11.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:30:11.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:30:11.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:30:11.262 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:30:11.262 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2726 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.262 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2726 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2726 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2726 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2726 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2726 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.263 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:11.264 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2727 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:30:16.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:30:16.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:30:16.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:30:16.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:30:16.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:30:16.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:30:16.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:30:16.272 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:30:16.272 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:16.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:30:16.273 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:30:16.275 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:30:16.275 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:30:16.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:30:16.276 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:16.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:30:16.277 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:30:16.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:30:16.277 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:30:16.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:16.277 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:30:16.278 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:30:16.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:30:16.278 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:16.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:30:16.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:30:16.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:30:16.278 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:30:16.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:30:16.280 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:30:16.280 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:30:16.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:30:16.283 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:30:16.283 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:30:16.283 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:30:16.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:16.288 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:30:16.772 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:30:16.810 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:30:16.810 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:30:16.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:16.813 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:30:16.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:16.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:16.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:16.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:16.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:16.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:16.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:16.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:16.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:16.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:16.871 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:16.871 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:16.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:16.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:16.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:16.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:17.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:17.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:17.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:17.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:17.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:17.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:17.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:17.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:17.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:17.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:17.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:17.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:17.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:17.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:17.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:17.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.247 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:30:17.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:17.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:17.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:17.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:17.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:17.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:17.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:17.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:17.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:17.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:17.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:17.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:17.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:17.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:17.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:17.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:17.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:17.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:17.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:17.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:17.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:17.723 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:30:18.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:18.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:18.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:18.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:18.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:18.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:18.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:18.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:18.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:18.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:18.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:18.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:18.145 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:18.145 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:18.145 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:18.145 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:18.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:18.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:18.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:18.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:18.199 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:30:18.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:18.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:18.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:18.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:18.677 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:30:18.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:18.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:18.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:18.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:18.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:18.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:18.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:18.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:18.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:30:18.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:30:18.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:30:18.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:30:18.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:30:18.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:30:18.773 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:30:23.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:30:23.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:30:23.778 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:30:23.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:30:23.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:30:23.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:30:23.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:30:23.787 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:30:23.787 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:23.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:30:23.788 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:30:23.790 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:30:23.790 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:30:23.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:23.792 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:30:23.792 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:30:23.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:30:23.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:23.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:30:23.793 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:30:23.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:30:23.793 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:30:23.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:30:23.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:30:23.795 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:30:23.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.798 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:30:23.798 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:30:23.798 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:30:23.798 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:30:23.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:30:23.803 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:30:24.287 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:30:24.337 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:30:24.339 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:30:24.341 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:30:24.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:24.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:24.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:24.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:24.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:24.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:24.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:24.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:24.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:24.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:24.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:24.399 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:24.399 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:24.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:24.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:24.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:24.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:24.764 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:30:24.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:24.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:24.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:24.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:25.242 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:30:25.720 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:30:25.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:25.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:25.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:25.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:26.198 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:30:26.676 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:30:26.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:26.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:26.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:26.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:27.154 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:30:27.632 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:30:27.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:27.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:27.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:27.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:28.109 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:30:28.586 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:30:28.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:30:28.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:30:28.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:30:28.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:30:29.064 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:30:29.541 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:30:30.019 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:30:30.497 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:30:30.975 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:30:31.453 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:30:31.931 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:30:32.408 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:30:32.886 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:30:33.364 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:30:33.842 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:30:34.320 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:30:34.798 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:30:35.275 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:30:35.753 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:30:36.231 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:30:36.709 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:30:37.187 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:30:37.665 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:30:38.143 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:30:38.620 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:30:39.098 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:30:39.575 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:30:40.053 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:30:40.531 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:30:41.008 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:30:41.485 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:30:41.963 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:30:42.441 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:30:42.919 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:30:43.397 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:30:43.874 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:30:44.351 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:30:44.829 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:30:45.307 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:30:45.785 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:30:46.264 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:30:46.741 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:30:47.219 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:30:47.697 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:30:48.175 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:30:48.653 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:30:49.131 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:30:49.608 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:30:50.087 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:30:50.564 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:30:51.041 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:30:51.519 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:30:51.997 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:30:52.475 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:30:52.953 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:30:53.431 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:30:53.908 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:30:54.386 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:30:54.863 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:30:55.341 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:30:55.819 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:30:56.297 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:30:56.775 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:30:57.253 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:30:57.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:57.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:57.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:57.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:57.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:57.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:57.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:57.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:30:57.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:30:57.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:30:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:30:57.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:57.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:57.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:57.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:30:57.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:30:57.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:30:57.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:30:57.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:57.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:30:57.729 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:30:58.207 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:30:58.685 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:30:59.164 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:30:59.642 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:31:00.120 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:31:00.598 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:31:01.076 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:31:01.552 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:31:02.030 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:31:02.508 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:31:02.986 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:31:03.464 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:31:03.942 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:31:04.420 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:31:04.898 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:31:05.376 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:31:05.854 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:31:06.332 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:31:06.810 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:31:07.288 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:31:07.766 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:31:08.243 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:31:08.720 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:31:09.199 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:31:09.677 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:31:10.155 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:31:10.634 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:31:11.112 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:31:11.590 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:31:12.068 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 02:31:12.546 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 02:31:13.024 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 02:31:13.501 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 02:31:13.979 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 02:31:14.456 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 02:31:14.935 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 02:31:15.413 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 02:31:15.891 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 02:31:16.369 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 02:31:16.847 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 02:31:17.325 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 02:31:17.803 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 02:31:18.281 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 02:31:18.760 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 02:31:19.237 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 02:31:19.715 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 02:31:20.194 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 02:31:20.672 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 02:31:21.150 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 02:31:21.628 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 02:31:22.106 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 02:31:22.585 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 02:31:23.063 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 02:31:23.541 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 02:31:24.020 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 02:31:24.498 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 02:31:24.976 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 02:31:25.454 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 02:31:25.932 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 02:31:26.410 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 02:31:26.888 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 02:31:27.366 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 02:31:27.844 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 02:31:28.322 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 02:31:28.800 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 02:31:29.278 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 02:31:29.756 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 02:31:30.234 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 02:31:30.712 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 02:31:31.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:31:31.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:31:31.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:31:31.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:31:31.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:31:31.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:31:31.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:31:31.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:31:31.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:31:31.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:31:31.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:31:31.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:31:31.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:31:31.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:31:31.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:31:31.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:31:31.189 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 02:31:31.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:31:31.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:31:31.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:31:31.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:31:31.666 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 02:31:32.143 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 02:31:32.621 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 02:31:33.098 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 02:31:33.576 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 02:31:34.054 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 02:31:34.531 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 02:31:35.009 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 02:31:35.486 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 02:31:35.964 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 02:31:36.442 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 02:31:36.919 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 02:31:37.397 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 02:31:37.874 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 02:31:38.352 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 02:31:38.829 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 02:31:39.307 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 02:31:39.784 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 02:31:40.262 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 02:31:40.740 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 02:31:41.218 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 02:31:41.695 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 02:31:42.173 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 02:31:42.651 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 02:31:43.128 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 02:31:43.606 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 02:31:44.084 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 02:31:44.561 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 02:31:45.039 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 02:31:45.516 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 02:31:45.994 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 02:31:46.471 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 02:31:46.949 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 02:31:47.427 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 02:31:47.904 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 02:31:48.382 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 02:31:48.860 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 02:31:49.338 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 02:31:49.815 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 02:31:50.292 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 02:31:50.770 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-02 02:31:51.248 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-02 02:31:51.726 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-02 02:31:52.203 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-02 02:31:52.681 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-02 02:31:53.158 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-02 02:31:53.635 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-02 02:31:54.113 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-02 02:31:54.591 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-02 02:31:55.069 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-02 02:31:55.547 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-02 02:31:56.025 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-02 02:31:56.502 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-02 02:31:56.980 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-02 02:31:57.457 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-02 02:31:57.935 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-02 02:31:58.413 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-02 02:31:58.891 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-02 02:31:59.368 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-02 02:31:59.846 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-02 02:32:00.324 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-02 02:32:00.801 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-02 02:32:01.279 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-02 02:32:01.756 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-02 02:32:02.234 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-02 02:32:02.711 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-02 02:32:03.188 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-02 02:32:03.666 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-02 02:32:04.144 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-02 02:32:04.622 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-02 02:32:05.100 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-02 02:32:05.578 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-02 02:32:06.056 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-02 02:32:06.533 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-02 02:32:06.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:06.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:06.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:06.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:06.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:06.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:06.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:06.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:06.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:06.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:06.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:06.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:06.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:06.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:06.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:32:06.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:32:06.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:06.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:06.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:06.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:07.009 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-02 02:32:07.487 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-02 02:32:07.964 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-02 02:32:08.442 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-02 02:32:08.920 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-02 02:32:09.398 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-02 02:32:09.875 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-02 02:32:10.353 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-02 02:32:10.831 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-02 02:32:11.309 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-02 02:32:11.786 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-02 02:32:12.264 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-02 02:32:12.742 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-02 02:32:13.220 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-02 02:32:13.698 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-02 02:32:14.176 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-02 02:32:14.653 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-02 02:32:15.132 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-02 02:32:15.609 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-02 02:32:16.086 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-02 02:32:16.564 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-02 02:32:17.042 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-02 02:32:17.519 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-02 02:32:17.996 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-02 02:32:18.474 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-02 02:32:18.951 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-02 02:32:19.429 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-02 02:32:19.906 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-02 02:32:20.385 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-02 02:32:20.863 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-02 02:32:21.340 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-02 02:32:21.818 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-02 02:32:22.296 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-02 02:32:22.774 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-02 02:32:23.252 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-02 02:32:23.730 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-02 02:32:24.208 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-03-02 02:32:24.685 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-03-02 02:32:25.163 [DEBUG] clck_gen.py:113 IND CLOCK 25908
2026-03-02 02:32:25.640 [DEBUG] clck_gen.py:113 IND CLOCK 26010
2026-03-02 02:32:26.118 [DEBUG] clck_gen.py:113 IND CLOCK 26112
2026-03-02 02:32:26.596 [DEBUG] clck_gen.py:113 IND CLOCK 26214
2026-03-02 02:32:27.074 [DEBUG] clck_gen.py:113 IND CLOCK 26316
2026-03-02 02:32:27.552 [DEBUG] clck_gen.py:113 IND CLOCK 26418
2026-03-02 02:32:28.030 [DEBUG] clck_gen.py:113 IND CLOCK 26520
2026-03-02 02:32:28.508 [DEBUG] clck_gen.py:113 IND CLOCK 26622
2026-03-02 02:32:28.986 [DEBUG] clck_gen.py:113 IND CLOCK 26724
2026-03-02 02:32:29.463 [DEBUG] clck_gen.py:113 IND CLOCK 26826
2026-03-02 02:32:29.941 [DEBUG] clck_gen.py:113 IND CLOCK 26928
2026-03-02 02:32:30.419 [DEBUG] clck_gen.py:113 IND CLOCK 27030
2026-03-02 02:32:30.896 [DEBUG] clck_gen.py:113 IND CLOCK 27132
2026-03-02 02:32:31.374 [DEBUG] clck_gen.py:113 IND CLOCK 27234
2026-03-02 02:32:31.851 [DEBUG] clck_gen.py:113 IND CLOCK 27336
2026-03-02 02:32:32.329 [DEBUG] clck_gen.py:113 IND CLOCK 27438
2026-03-02 02:32:32.807 [DEBUG] clck_gen.py:113 IND CLOCK 27540
2026-03-02 02:32:33.286 [DEBUG] clck_gen.py:113 IND CLOCK 27642
2026-03-02 02:32:33.763 [DEBUG] clck_gen.py:113 IND CLOCK 27744
2026-03-02 02:32:34.241 [DEBUG] clck_gen.py:113 IND CLOCK 27846
2026-03-02 02:32:34.718 [DEBUG] clck_gen.py:113 IND CLOCK 27948
2026-03-02 02:32:35.196 [DEBUG] clck_gen.py:113 IND CLOCK 28050
2026-03-02 02:32:35.674 [DEBUG] clck_gen.py:113 IND CLOCK 28152
2026-03-02 02:32:36.152 [DEBUG] clck_gen.py:113 IND CLOCK 28254
2026-03-02 02:32:36.629 [DEBUG] clck_gen.py:113 IND CLOCK 28356
2026-03-02 02:32:37.107 [DEBUG] clck_gen.py:113 IND CLOCK 28458
2026-03-02 02:32:37.585 [DEBUG] clck_gen.py:113 IND CLOCK 28560
2026-03-02 02:32:38.063 [DEBUG] clck_gen.py:113 IND CLOCK 28662
2026-03-02 02:32:38.540 [DEBUG] clck_gen.py:113 IND CLOCK 28764
2026-03-02 02:32:39.018 [DEBUG] clck_gen.py:113 IND CLOCK 28866
2026-03-02 02:32:39.496 [DEBUG] clck_gen.py:113 IND CLOCK 28968
2026-03-02 02:32:39.974 [DEBUG] clck_gen.py:113 IND CLOCK 29070
2026-03-02 02:32:40.452 [DEBUG] clck_gen.py:113 IND CLOCK 29172
2026-03-02 02:32:40.930 [DEBUG] clck_gen.py:113 IND CLOCK 29274
2026-03-02 02:32:41.407 [DEBUG] clck_gen.py:113 IND CLOCK 29376
2026-03-02 02:32:41.885 [DEBUG] clck_gen.py:113 IND CLOCK 29478
2026-03-02 02:32:42.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:42.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:42.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:42.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:42.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:42.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:42.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:42.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:42.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:32:42.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:32:42.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:32:42.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:32:42.234 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:32:42.234 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:32:42.234 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:32:42.234 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:42.234 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:42.234 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:42.234 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:42.234 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:42.234 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:42.235 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=29555 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:32:47.234 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:32:47.234 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:32:47.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:32:47.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:32:47.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:32:47.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:32:47.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:32:47.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:32:47.247 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:47.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:32:47.247 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:32:47.251 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:32:47.252 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:32:47.252 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:32:47.252 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:47.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:32:47.253 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:32:47.253 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:32:47.253 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:32:47.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:47.254 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:32:47.255 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:32:47.255 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:32:47.255 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:47.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:32:47.255 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:32:47.255 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:32:47.255 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:32:47.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:47.257 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:32:47.257 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:32:47.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:32:47.257 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:47.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:32:47.257 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:32:47.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:32:47.257 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:32:47.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:47.260 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:32:47.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:32:47.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:32:47.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:32:47.261 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:32:47.261 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:32:47.261 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:32:47.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:32:47.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:32:47.263 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:32:52.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:32:52.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:32:52.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:32:52.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:32:52.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:32:52.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:32:52.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:32:52.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:32:52.281 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:52.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:32:52.282 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:32:52.286 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:32:52.286 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:32:52.286 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:32:52.286 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:52.286 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:32:52.287 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:32:52.287 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:32:52.287 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:32:52.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:52.289 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:32:52.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:32:52.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:32:52.290 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:52.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:32:52.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:32:52.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:32:52.291 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:32:52.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:52.292 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:32:52.292 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:32:52.292 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:32:52.292 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:32:52.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:32:52.293 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:32:52.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:32:52.293 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:32:52.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:32:52.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:32:52.297 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:32:52.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:32:52.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:32:52.786 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:32:52.821 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:32:52.822 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:32:52.823 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:32:52.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:52.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:52.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:52.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:52.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:52.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:52.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:52.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:52.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:52.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:52.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:52.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:32:52.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:32:52.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:52.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:52.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:52.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:53.262 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:32:53.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:53.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:53.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:53.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:53.739 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:32:54.217 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:32:54.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:54.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:54.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:54.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:54.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:54.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:54.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:54.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:54.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:54.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:54.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:54.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:54.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:54.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:54.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:54.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:54.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:54.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:54.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:32:54.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:32:54.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:54.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:54.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:54.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:54.693 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:32:55.171 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:32:55.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:55.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:55.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:55.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:55.650 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:32:56.128 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:32:56.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:56.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:56.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:56.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:56.606 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:32:56.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:56.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:56.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:56.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:56.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:56.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:56.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:56.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:32:56.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:32:56.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:32:56.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:32:56.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:56.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:56.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:56.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:32:56.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:32:56.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:32:56.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:32:56.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:56.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:32:57.081 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:32:57.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:32:57.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:32:57.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:32:57.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:32:57.559 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:32:58.037 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:32:58.514 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:32:58.992 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:32:59.470 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:32:59.947 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:33:00.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:00.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:00.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:00.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:00.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:00.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:00.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:00.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:00.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:00.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:00.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:00.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:00.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:00.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:00.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:33:00.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:33:00.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:00.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:00.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:00.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:00.423 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:33:00.901 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:33:01.378 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:33:01.855 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:33:02.334 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:33:02.811 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:33:03.289 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:33:03.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:03.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:03.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:03.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:03.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:03.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:03.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:03.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:03.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:33:03.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:33:03.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:33:03.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:33:03.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:33:03.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:33:03.627 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2420 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2420 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2420 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2420 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2420 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2420 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:03.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2421 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:33:08.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:33:08.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:33:08.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:33:08.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:33:08.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:33:08.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:33:08.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:33:08.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:33:08.641 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:33:08.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:33:08.642 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:33:08.645 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:33:08.646 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:33:08.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:33:08.646 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:33:08.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:33:08.647 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:33:08.647 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:33:08.648 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:33:08.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:08.648 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:33:08.648 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:33:08.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:33:08.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:33:08.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:33:08.649 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:33:08.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:33:08.649 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:33:08.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:33:08.651 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:33:08.651 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:33:08.651 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.654 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:33:08.655 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:33:08.655 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:33:08.655 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:33:08.660 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:33:09.145 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:33:09.186 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:33:09.188 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:33:09.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:09.188 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:33:09.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:09.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:09.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:09.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:09.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:09.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:09.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:09.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:09.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:09.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:09.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:33:09.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:33:09.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:09.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:09.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:09.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:09.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:33:09.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:09.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:09.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:09.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:10.100 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:33:10.578 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:33:10.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:10.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:10.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:10.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:11.056 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:33:11.533 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:33:11.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:11.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:11.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:11.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:12.011 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:33:12.489 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:33:12.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:12.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:12.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:12.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:12.967 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:33:13.444 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:33:13.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:33:13.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:33:13.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:33:13.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:33:13.922 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:33:14.400 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:33:14.877 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:33:15.355 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:33:15.833 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:33:16.311 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:33:16.789 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:33:17.267 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:33:17.745 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:33:18.236 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:33:18.714 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:33:19.192 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:33:19.669 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:33:20.147 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:33:20.625 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:33:21.104 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:33:21.582 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:33:22.059 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:33:22.537 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:33:23.015 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:33:23.492 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:33:23.970 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:33:24.448 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:33:24.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:24.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:24.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:24.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:24.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:24.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:24.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:24.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:24.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:24.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:24.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:24.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:24.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:24.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:24.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:33:24.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:33:24.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:24.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:24.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:24.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:24.925 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:33:25.403 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:33:25.881 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:33:26.360 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:33:26.838 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:33:27.316 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:33:27.794 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:33:28.272 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:33:28.750 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:33:29.228 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:33:29.706 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:33:30.184 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:33:30.662 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:33:31.140 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:33:31.618 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:33:32.096 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:33:32.573 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:33:33.051 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:33:33.530 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:33:34.008 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:33:34.486 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:33:34.964 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:33:35.442 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:33:35.920 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:33:36.399 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:33:36.877 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:33:37.355 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:33:37.832 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:33:38.310 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:33:38.788 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:33:39.266 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:33:39.745 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:33:40.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:40.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:40.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:40.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:40.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:40.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:40.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:40.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:40.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:40.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:40.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:40.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:40.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:40.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:40.128 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:33:40.128 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:33:40.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:40.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:40.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:40.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:40.222 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:33:40.700 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:33:41.177 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:33:41.655 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:33:42.133 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:33:42.610 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:33:43.088 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:33:43.565 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:33:44.042 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:33:44.520 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:33:44.997 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:33:45.475 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:33:45.952 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:33:46.430 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:33:46.907 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:33:47.385 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:33:47.863 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:33:48.341 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:33:48.818 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:33:49.296 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:33:49.773 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:33:50.250 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:33:50.728 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:33:51.206 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:33:51.683 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:33:52.161 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:33:52.639 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:33:53.116 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:33:53.594 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:33:54.072 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:33:54.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:54.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:54.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:54.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:54.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:54.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:54.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:54.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:33:54.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:33:54.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:33:54.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:33:54.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:54.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:54.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:54.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:33:54.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:33:54.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:33:54.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:33:54.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:54.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:33:54.548 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:33:55.026 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:33:55.504 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:33:55.982 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:33:56.459 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:33:56.937 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 02:33:57.414 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 02:33:57.892 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 02:33:58.370 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 02:33:58.848 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 02:33:59.326 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 02:33:59.804 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 02:34:00.282 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 02:34:00.759 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 02:34:01.237 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 02:34:01.715 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 02:34:02.192 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 02:34:02.670 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 02:34:03.147 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 02:34:03.625 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 02:34:04.100 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 02:34:04.577 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 02:34:05.055 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 02:34:05.532 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 02:34:06.010 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 02:34:06.487 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 02:34:06.965 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 02:34:07.443 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 02:34:07.921 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 02:34:08.398 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 02:34:08.876 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 02:34:09.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:09.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:09.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:09.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:09.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:09.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:09.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:09.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:09.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:09.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:34:09.294 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:34:09.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:34:09.294 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:34:09.294 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12943 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.295 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.296 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.296 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:09.296 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=12944 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:34:14.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:34:14.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:34:14.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:14.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:14.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:14.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:34:14.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:14.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:34:14.305 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:14.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:34:14.306 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:34:14.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:34:14.309 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:34:14.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:34:14.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:14.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:14.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:34:14.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:34:14.309 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:34:14.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:34:14.311 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:34:14.311 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:34:14.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:14.312 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:34:14.312 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:34:14.312 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:34:14.312 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:14.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:34:14.312 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:34:14.312 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:34:14.312 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:34:14.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:34:14.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:34:14.317 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:34:14.318 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:14.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:14.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:14.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:34:14.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:34:14.320 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:34:19.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:34:19.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:34:19.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:19.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:19.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:34:19.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:19.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:19.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:34:19.337 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:19.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:34:19.338 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:34:19.341 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:34:19.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:34:19.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:34:19.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:19.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:19.343 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:34:19.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:34:19.343 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:34:19.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:19.344 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:34:19.344 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:34:19.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:34:19.345 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:19.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:19.345 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:34:19.345 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:34:19.345 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:34:19.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:34:19.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:34:19.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:34:19.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:34:19.350 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:34:19.351 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:34:19.351 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:34:19.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:34:19.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:34:19.356 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:34:19.840 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:34:19.881 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:34:19.883 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:34:19.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:19.886 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:34:19.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:19.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:19.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:19.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:19.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:19.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:19.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:19.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:19.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:19.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:19.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:34:19.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:34:19.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:19.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:19.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:19.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:20.317 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:34:20.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:20.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:20.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:20.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:20.795 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:34:21.273 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:34:21.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:21.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:21.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:21.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:21.750 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:34:22.227 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:34:22.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:22.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:22.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:22.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:22.705 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:34:23.183 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:34:23.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:23.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:23.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:23.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:23.660 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:34:24.138 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:34:24.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:24.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:24.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:24.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:24.616 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:34:25.094 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:34:25.572 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:34:26.050 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:34:26.528 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:34:27.006 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:34:27.483 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:34:27.960 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:34:28.438 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:34:28.916 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:34:29.394 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:34:29.871 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:34:30.349 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:34:30.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:30.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:30.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:30.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:30.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:30.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:30.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:30.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:30.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:30.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:30.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:30.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:30.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:30.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:30.583 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:34:30.583 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:34:30.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:30.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:30.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:30.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:30.834 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:34:31.313 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:34:31.791 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:34:32.269 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:34:32.747 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:34:33.225 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:34:33.701 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:34:34.179 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:34:34.657 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:34:35.135 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:34:35.613 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:34:36.091 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:34:36.569 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:34:37.045 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:34:37.523 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:34:38.001 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:34:38.478 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:34:38.956 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:34:39.434 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:34:39.912 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:34:40.390 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:34:40.868 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:34:41.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:41.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:41.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:41.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:41.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:41.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:41.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:41.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:41.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:41.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:41.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:41.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:41.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:41.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:41.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:34:41.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:34:41.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:41.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:41.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:41.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:41.344 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:34:41.822 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:34:42.299 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:34:42.777 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:34:43.255 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:34:43.733 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:34:44.211 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:34:44.688 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:34:45.166 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:34:45.643 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:34:46.120 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:34:46.598 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:34:47.076 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:34:47.553 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:34:48.031 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:34:48.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:48.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:48.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:48.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:48.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:48.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:48.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:48.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:48.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:48.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:34:48.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:48.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:48.100 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:48.100 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:48.100 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:34:48.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:34:48.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:34:48.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:34:48.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:48.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:48.508 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:34:48.986 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:34:49.464 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:34:49.941 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:34:50.419 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:34:50.896 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:34:51.373 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:34:51.851 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:34:52.329 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:34:52.807 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:34:53.284 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:34:53.762 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:34:54.239 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:34:54.716 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:34:55.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:34:55.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:34:55.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:34:55.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:34:55.194 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:34:55.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:34:55.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:34:55.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:34:55.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:34:55.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:34:55.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:34:55.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:34:55.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:34:55.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:34:55.201 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:34:55.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:00.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:00.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:00.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:00.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:00.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:00.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:00.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:00.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:00.212 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:00.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:00.212 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:35:00.214 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:35:00.215 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:35:00.215 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:00.215 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:00.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:00.216 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:35:00.216 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:00.216 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:35:00.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:00.217 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:35:00.217 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:35:00.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:00.217 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:00.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:00.218 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:35:00.218 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:00.218 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:35:00.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:00.220 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:35:00.220 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:35:00.220 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:00.220 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:00.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:00.221 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:35:00.221 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:00.221 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:35:00.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:35:00.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:35:00.224 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:35:00.224 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:35:00.224 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:00.229 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:35:00.712 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:35:00.755 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:35:00.757 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:35:00.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:00.759 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:35:00.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:00.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:00.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:00.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:00.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:00.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:00.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:00.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:00.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:00.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:00.819 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:00.819 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:00.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:00.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:00.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:00.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:01.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:01.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:01.189 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:35:01.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:01.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:01.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:01.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:01.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:01.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:01.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:01.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:01.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:01.200 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:01.200 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:01.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:01.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:01.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:01.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:01.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:01.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:01.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.665 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:35:01.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:01.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:01.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:01.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:01.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:01.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:01.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:01.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:01.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:01.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:01.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:01.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:01.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:01.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:01.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:01.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:01.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:01.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:02.142 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:35:02.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:02.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:02.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:02.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:02.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:02.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:02.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:02.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:02.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:02.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:02.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:02.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:02.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:02.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:02.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:02.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:02.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:02.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:02.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:02.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:02.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:02.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:02.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:02.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:02.618 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:35:03.096 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:35:03.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:03.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:03.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:03.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:03.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:03.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:03.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:03.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:03.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:03.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:03.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:03.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:03.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:03.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:03.432 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:03.432 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:03.432 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:03.432 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:35:03.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:03.433 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=686 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:08.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:08.432 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:08.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:08.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:08.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:08.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:08.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:08.439 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:08.439 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:08.439 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:08.439 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:08.441 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:08.441 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:35:08.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:08.443 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:35:08.443 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:35:08.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:08.443 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:08.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:08.444 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:35:08.444 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:08.444 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:35:08.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:08.445 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:35:08.445 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:35:08.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:08.445 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:08.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:08.446 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:35:08.446 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:08.446 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:35:08.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:35:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:35:08.449 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:35:08.449 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:35:08.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:08.454 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:35:08.938 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:35:08.978 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:35:08.980 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:35:08.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:08.982 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:35:09.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:09.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:09.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:09.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:09.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:09.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:09.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:09.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:09.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:09.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:09.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:09.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:09.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:09.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:09.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:09.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:09.414 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:35:09.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:09.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:09.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:09.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:09.892 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:35:10.370 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:35:10.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:10.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:10.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:10.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:10.848 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:35:11.326 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:35:11.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:11.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:11.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:11.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:11.804 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:35:12.281 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:35:12.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:12.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:12.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:12.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:12.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:12.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:12.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:12.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:12.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:12.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:12.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:12.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:12.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:12.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:12.334 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:12.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:12.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:12.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:12.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:12.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:12.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:12.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:12.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:12.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:12.759 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:35:13.237 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:35:13.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:13.715 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:35:14.193 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:35:14.671 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:35:15.149 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:35:15.627 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:35:15.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:15.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:15.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:15.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:15.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:15.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:15.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:15.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:15.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:15.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:15.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:15.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:15.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:15.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:15.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:15.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:15.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:15.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:15.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:15.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:16.104 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:35:16.582 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:35:17.059 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:35:17.536 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:35:18.014 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:35:18.492 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:35:18.969 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:35:19.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:19.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:19.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:19.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:19.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:19.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:19.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:19.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:19.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:19.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:19.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:19.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:19.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:19.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:19.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:19.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:19.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:19.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:19.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:19.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:19.447 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:35:19.924 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:35:20.402 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:35:20.880 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:35:21.358 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:35:21.836 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:35:22.314 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:35:22.792 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:35:23.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:23.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:23.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:23.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:23.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:23.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:23.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:23.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:23.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:23.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:23.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:23.129 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:23.129 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:23.129 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:35:23.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.130 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:23.131 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:28.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:28.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:28.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:28.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:28.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:28.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:28.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:28.140 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:28.140 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:28.140 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:28.140 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:35:28.143 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:35:28.143 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:35:28.143 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:28.144 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:28.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:28.144 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:35:28.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:28.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:35:28.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:28.146 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:28.146 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:35:28.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:28.148 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:35:28.148 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:35:28.148 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:28.148 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:28.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:28.148 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:35:28.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:28.149 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:35:28.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:35:28.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:35:28.152 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:35:28.152 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:35:28.152 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:28.157 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:35:28.640 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:35:28.674 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:35:28.675 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:35:28.676 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:35:28.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:28.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:28.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:28.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:28.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:28.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:28.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:28.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:28.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:28.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:28.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:28.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:28.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:28.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:28.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:28.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:28.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:29.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:29.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:29.117 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:35:29.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:29.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:29.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:29.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:29.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:29.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:29.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:29.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:29.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:29.128 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:29.128 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:29.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:29.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:29.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:29.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:29.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:29.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:29.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.595 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:35:29.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:29.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:29.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:29.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:29.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:29.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:29.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:29.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:29.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:29.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:29.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:29.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:29.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:29.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:29.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:29.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:29.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:29.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:30.071 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:35:30.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:30.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:30.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:30.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:30.549 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:35:30.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:30.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:30.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:30.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:30.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:30.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:30.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:30.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:30.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:30.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:30.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:30.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:30.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:30.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:30.738 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:30.738 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:30.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:30.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:30.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:30.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:31.026 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:35:31.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:31.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:31.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:31.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:31.504 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:35:31.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:31.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:31.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:31.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:31.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:31.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:31.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:31.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:31.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:31.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:31.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:31.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:31.841 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:31.841 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:31.841 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:35:31.841 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:31.841 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:31.842 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:31.842 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:31.842 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:31.842 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:36.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:36.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:36.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:36.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:36.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:36.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:36.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:36.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:36.870 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:36.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:35:36.870 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:35:36.874 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:35:36.874 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:35:36.874 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:36.874 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:36.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:36.875 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:35:36.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:35:36.876 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:35:36.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:36.880 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:35:36.881 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:35:36.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:36.881 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:36.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:36.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:35:36.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:35:36.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:35:36.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:36.884 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:35:36.884 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:35:36.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:36.884 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:35:36.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:36.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:35:36.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:35:36.885 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:35:36.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:35:36.890 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:35:36.890 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:35:36.890 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:35:36.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:35:36.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:35:36.895 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:35:37.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:35:37.421 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:35:37.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:37.423 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:35:37.424 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:35:37.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:37.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:37.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:37.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:37.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:37.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:37.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:37.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:37.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:37.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:37.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:37.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:37.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:37.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:37.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:37.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:37.855 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:35:37.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:37.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:37.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:37.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:38.332 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:35:38.810 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:35:38.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:38.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:38.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:38.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:39.288 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:35:39.766 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:35:39.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:39.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:39.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:39.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:40.244 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:35:40.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:40.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:40.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:40.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:40.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:40.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:40.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:40.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:40.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:40.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:40.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:40.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:40.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:40.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:40.427 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:40.427 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:40.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:40.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:40.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:40.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:40.722 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:35:40.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:40.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:40.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:40.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:41.200 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:35:41.678 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:35:41.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:41.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:41.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:41.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:42.156 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:35:42.634 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:35:43.113 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:35:43.591 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:35:44.069 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:35:44.547 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:35:45.025 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:35:45.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:45.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:45.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:45.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:45.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:45.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:45.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:45.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:45.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:45.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:45.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:45.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:45.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:45.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:45.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:45.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:45.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:45.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:45.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:45.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:45.502 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:35:45.980 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:35:46.458 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:35:46.935 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:35:47.413 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:35:47.891 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:35:48.369 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:35:48.846 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:35:49.324 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:35:49.802 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:35:50.280 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:35:50.758 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:35:51.235 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:35:51.713 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:35:51.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:51.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:51.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:51.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:51.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:51.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:51.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:51.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:51.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:51.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:35:51.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:51.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:51.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:51.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:51.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:35:51.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:35:51.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:35:51.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:35:51.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:51.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:52.189 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:35:52.667 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:35:53.145 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:35:53.622 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:35:54.101 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:35:54.579 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:35:55.056 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:35:55.534 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:35:56.011 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:35:56.489 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:35:56.966 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:35:57.444 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:35:57.922 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:35:58.400 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:35:58.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:35:58.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:35:58.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:35:58.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:35:58.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:35:58.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:35:58.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:35:58.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:35:58.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:35:58.737 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:35:58.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:35:58.737 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:35:58.737 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:35:58.737 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:35:58.737 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4664 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:35:58.737 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4665 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:03.737 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:03.737 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:03.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:03.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:03.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:03.741 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:03.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:03.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:03.749 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:03.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:03.749 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:03.751 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:03.751 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:03.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:03.752 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:03.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:03.752 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:03.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:03.753 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:03.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:03.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:03.754 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:03.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:03.755 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:03.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:03.755 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:03.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:03.755 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:03.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:03.757 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:03.757 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:03.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:03.757 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:03.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:03.758 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:03.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:03.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:03.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:03.761 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:03.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:03.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:03.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:03.761 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:03.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:03.762 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:03.762 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:03.762 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:03.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:03.767 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:04.250 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:04.287 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:04.287 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:04.287 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:04.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:04.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:04.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:04.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:04.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:04.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:04.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:04.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:04.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:04.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:04.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:04.302 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:36:04.302 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:36:04.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:04.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:04.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:04.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:04.721 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:04.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:04.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:04.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:04.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:05.199 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:05.677 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:36:05.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:05.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:05.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:05.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:06.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:06.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:06.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:06.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:06.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:06.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:06.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:06.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:06.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:06.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:06.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:06.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:06.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:06.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:06.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:36:06.116 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:36:06.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:06.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:06.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:06.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:06.154 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:36:06.632 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:36:06.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:06.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:06.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:07.111 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:36:07.589 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:36:07.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:07.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:07.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:07.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:08.067 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:36:08.544 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:36:08.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:08.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:08.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:08.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:08.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:08.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:08.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:08.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:08.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:08.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:08.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:08.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:08.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:08.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:08.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:08.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:08.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:08.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:36:08.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:36:08.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:08.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:08.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:08.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:09.020 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:36:09.498 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:36:09.976 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:36:10.454 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:36:10.931 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:36:11.409 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:36:11.887 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:36:12.364 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:36:12.841 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:36:13.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:13.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:13.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:13.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:13.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:13.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:13.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:13.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:13.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:13.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:13.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:36:13.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:13.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:13.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:13.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:36:13.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:36:13.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:36:13.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:36:13.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:13.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:13.318 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:36:13.796 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:36:14.273 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:36:14.751 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:36:15.229 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:36:15.707 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:36:16.185 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:36:16.663 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:36:17.141 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:36:17.618 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:36:17.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:36:17.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:17.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:36:17.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:36:17.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:17.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:17.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:17.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:17.718 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:17.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:17.718 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:17.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:17.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:17.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:17.718 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:17.718 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2981 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:22.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:22.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:22.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:22.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:22.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:22.724 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:22.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:22.733 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:22.733 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:22.733 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:22.734 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:22.736 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:22.737 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:22.737 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:22.737 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:22.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:22.738 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:22.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:22.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:22.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:22.740 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:22.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:22.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:22.742 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:22.742 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:22.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:22.742 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:22.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:22.742 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:22.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:22.743 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:22.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:22.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:22.746 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:22.746 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:22.746 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:22.751 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:23.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:23.273 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:23.275 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:23.277 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:23.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.702 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:23.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:23.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:23.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:23.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:23.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:23.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.175 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:24.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:24.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:24.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:24.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:24.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:24.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:24.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:24.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:24.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:24.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:24.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:24.594 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:29.598 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:29.598 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:29.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:29.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:29.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:29.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:29.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:29.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:29.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:29.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:29.614 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:29.616 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:29.616 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:29.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:29.617 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:29.617 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:29.617 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:29.617 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:29.617 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:29.618 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:29.618 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:29.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:29.620 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:29.620 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:29.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:29.623 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:29.623 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:29.623 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:29.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:29.627 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:30.111 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:30.146 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:30.148 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:30.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.150 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:30.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.588 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:30.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:30.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:30.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:30.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:30.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:30.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.060 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:31.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:31.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:31.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:31.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:31.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:31.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:31.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:31.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:31.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:31.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:31.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:31.522 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:31.522 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:31.523 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:31.523 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:31.523 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:31.523 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:31.523 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:36.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:36.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:36.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:36.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:36.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:36.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:36.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:36.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:36.538 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:36.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:36.539 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:36.543 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:36.543 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:36.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:36.544 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:36.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:36.545 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:36.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:36.545 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:36.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:36.547 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:36.547 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:36.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:36.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:36.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:36.547 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:36.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:36.548 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:36.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:36.550 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:36.550 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:36.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:36.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:36.554 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:36.554 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:36.554 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:36.559 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:37.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:37.077 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:37.079 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:37.081 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:37.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.521 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:37.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:37.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:37.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:37.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:37.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:37.999 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:38.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:38.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:38.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:38.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:38.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:38.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:38.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:38.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:38.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:38.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:38.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:38.405 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:38.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.406 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.406 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.406 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.406 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:38.406 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:43.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:43.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:43.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:43.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:43.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:43.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:43.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:43.419 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:43.419 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:43.419 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:43.420 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:43.423 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:43.423 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:43.424 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:43.424 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:43.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:43.425 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:43.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:43.425 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:43.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:43.426 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:43.426 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:43.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:43.426 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:43.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:43.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:43.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:43.427 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:43.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:43.428 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:43.428 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:43.428 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:43.428 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:43.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:43.429 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:43.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:43.429 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:43.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:43.431 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:43.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:43.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:43.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:43.431 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:43.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:43.432 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:43.432 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:43.432 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:43.437 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:43.920 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:43.947 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:43.948 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:43.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:43.948 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:43.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:43.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.389 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:44.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:44.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:44.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:44.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:44.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.858 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:44.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:44.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:45.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:45.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:45.267 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:45.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:45.268 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:50.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:50.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:50.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:50.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:50.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:50.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:50.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:50.285 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:50.285 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:50.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:50.286 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:50.290 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:50.290 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:50.291 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:50.291 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:50.291 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:50.291 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:50.291 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:50.291 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:50.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:50.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:50.295 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:50.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:50.295 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:50.295 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:50.295 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:50.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:50.295 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:50.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:50.298 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:50.298 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:50.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:50.298 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:50.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:50.298 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:50.299 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:50.299 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:50.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:50.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.303 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:50.303 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:50.303 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:50.303 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:50.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.308 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:50.791 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:50.835 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:50.838 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:50.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:50.840 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:50.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:50.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:50.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.268 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:51.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:51.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:51.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:51.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:51.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.748 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:51.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:51.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:52.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:52.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:52.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:52.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:52.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:52.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:52.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:52.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:52.151 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:52.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:52.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:52.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:52.151 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:52.151 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:52.151 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:52.151 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:52.151 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:52.151 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:57.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:57.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:57.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:57.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:57.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:57.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:57.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:57.169 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:57.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:36:57.169 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:36:57.172 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:36:57.172 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:36:57.173 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:57.173 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:57.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:57.173 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:36:57.174 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:36:57.174 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:36:57.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:57.175 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:36:57.175 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:36:57.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:57.177 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:36:57.177 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:36:57.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:57.177 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:36:57.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:57.177 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:36:57.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:36:57.177 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:36:57.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:36:57.181 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:36:57.181 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:36:57.181 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.185 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:36:57.669 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:36:57.707 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:36:57.710 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:36:57.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:57.712 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:36:57.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:36:57.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:57.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:57.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:57.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.145 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:36:58.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:58.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:58.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:58.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:58.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.623 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:36:58.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:58.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:59.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:59.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:59.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:59.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:36:59.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:36:59.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:36:59.053 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:36:59.054 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:04.054 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:04.054 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:04.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:04.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:04.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:04.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:04.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:04.057 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:04.058 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:04.058 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:04.058 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:04.059 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:04.059 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:04.059 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:04.060 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:04.060 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:04.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:04.060 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:04.060 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:04.060 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:04.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:04.061 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:04.061 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:04.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:04.063 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:04.063 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:04.063 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:04.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:04.068 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:04.536 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:04.578 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:04.578 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:04.579 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:04.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:04.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.005 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:37:05.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:05.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:05.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:05.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:05.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.473 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:37:05.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:05.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:05.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:05.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:05.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:05.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:05.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:05.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:05.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:05.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:05.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:05.878 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:10.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:10.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:10.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:10.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:10.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:10.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:10.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:10.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:10.884 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:10.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:10.884 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:10.885 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:10.885 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:10.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:10.887 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:10.887 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:10.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:10.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:10.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:10.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.889 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:10.890 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:10.890 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:10.890 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:10.894 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:11.363 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:11.405 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:11.406 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:11.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.407 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:11.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:11.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:11.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:11.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:11.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:11.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:11.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:11.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:11.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:11.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:11.482 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:11.482 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:16.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:16.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:16.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:16.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:16.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:16.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:16.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:16.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:16.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:16.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:16.492 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:16.494 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:16.494 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:16.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:16.495 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:16.495 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:16.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:16.496 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:16.496 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:16.496 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:16.496 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:16.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:16.497 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:16.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:16.497 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:16.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:16.498 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:16.498 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:16.498 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:16.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:16.503 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:16.973 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:17.025 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:17.026 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:17.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.028 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:17.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:17.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:17.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:17.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:17.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:17.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:17.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:17.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:17.142 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:17.142 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:17.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:17.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:22.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:22.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:22.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:22.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:22.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:22.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:22.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:22.148 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:22.148 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:22.148 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:22.148 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:22.148 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:22.149 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:22.149 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:22.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:22.150 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:22.150 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:22.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:22.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:22.152 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:22.152 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:22.152 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:22.157 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:22.631 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:22.666 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:22.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.667 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:22.667 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:22.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:22.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:22.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:22.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:22.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:22.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:22.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:22.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:22.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:22.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:22.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:22.745 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:27.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:27.746 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:27.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:27.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:27.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:27.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:27.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:27.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:27.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:27.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:27.751 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:27.752 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:27.752 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:27.752 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:27.752 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:27.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:27.752 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:27.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:27.753 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:27.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:27.754 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:27.754 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:27.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:27.755 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:27.755 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:27.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:27.755 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:27.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:27.755 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:27.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:27.756 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:27.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:27.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:27.758 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:27.758 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:27.758 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:27.763 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:28.236 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:28.285 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:28.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.286 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:28.287 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:28.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:28.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:28.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:28.347 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:28.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:28.347 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:28.347 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:28.348 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:28.348 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:28.348 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:28.348 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:28.348 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.350 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:33.350 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:33.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:33.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:33.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:33.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:33.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:33.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:33.366 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:33.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:33.367 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:33.370 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:33.370 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:33.370 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:33.370 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:33.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:33.370 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:33.371 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:33.371 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:33.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:33.371 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:33.372 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:33.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:33.372 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:33.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:33.372 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:33.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:33.372 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:33.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:33.373 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:33.373 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:33.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:33.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:33.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:33.375 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:33.375 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.380 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:33.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:33.897 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:33.899 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:33.900 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:33.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:33.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:33.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:33.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:33.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:33.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:33.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:33.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:33.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:33.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:33.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:33.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:33.962 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:33.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:38.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:38.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:38.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:38.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:38.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:38.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:38.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:38.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:38.970 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:38.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:38.970 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:38.974 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:38.974 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:38.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:38.975 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:38.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:38.975 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:38.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:38.975 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:38.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:38.977 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:38.977 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:38.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:38.977 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:38.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:38.978 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:38.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:38.978 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:38.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:38.980 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:38.980 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:38.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:38.983 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:38.983 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:38.983 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:38.988 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:39.462 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:39.510 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:39.511 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:39.513 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:39.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:39.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:39.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:39.641 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:39.642 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:44.644 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:44.644 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:44.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:44.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:44.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:44.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:44.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:44.662 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:44.662 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:44.663 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:44.663 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:44.664 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:44.664 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:44.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:44.665 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:44.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:44.665 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:44.665 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:44.665 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:44.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:44.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:44.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:44.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:44.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:44.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:44.667 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:44.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:44.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:44.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:44.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:44.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:44.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:44.668 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:44.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:44.668 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:44.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:44.668 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:44.669 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:44.671 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:44.671 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:44.671 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:44.676 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:45.154 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:45.186 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:45.186 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:45.186 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:45.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:45.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:45.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:45.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:45.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:45.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:45.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:45.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:45.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:45.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:45.277 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:45.277 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:45.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:50.280 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:50.280 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:50.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:50.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:50.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:50.287 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:50.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:50.302 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:50.302 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:50.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:50.303 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:50.306 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:50.306 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:50.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:50.306 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:50.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:50.306 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:50.307 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:50.307 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:50.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:50.309 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:50.309 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:50.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:50.311 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:50.311 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:50.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:50.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:50.315 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:50.315 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:50.315 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:50.320 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:50.790 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:50.844 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:50.847 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:50.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:50.849 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:50.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:37:50.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:37:50.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:37:50.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:37:50.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:37:50.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:37:50.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:37:50.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:37:51.260 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:37:51.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:51.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:51.319 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:51.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:51.730 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:37:52.200 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:37:52.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:52.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:52.319 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:52.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:52.672 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:37:53.143 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:37:53.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:53.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:53.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:53.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:53.616 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:37:54.088 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:37:54.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:37:54.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:37:54.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:54.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:54.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:54.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:54.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:54.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:54.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:54.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:54.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:54.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:54.304 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:37:54.304 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:54.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:54.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:54.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:54.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:54.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:54.305 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:37:59.305 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:37:59.305 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:37:59.305 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:59.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:59.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:59.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:59.307 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:37:59.307 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:59.308 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:59.308 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:37:59.308 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:59.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:37:59.309 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:37:59.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:37:59.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:37:59.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:37:59.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:59.311 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:59.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:37:59.312 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:37:59.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:37:59.312 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:37:59.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:59.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:37:59.314 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:37:59.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:37:59.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:37:59.317 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:37:59.317 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:37:59.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:37:59.322 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:37:59.799 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:37:59.862 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:37:59.864 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:37:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:37:59.866 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:37:59.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:37:59.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:37:59.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:37:59.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:37:59.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:37:59.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:37:59.888 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:37:59.888 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:37:59.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:37:59.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:37:59.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:37:59.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:37:59.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:00.269 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:38:00.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:00.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:00.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:00.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:00.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:00.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:00.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:00.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:00.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:00.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:00.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:00.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:00.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:00.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:00.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:00.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:00.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:00.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:00.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:00.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:00.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:00.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:00.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:00.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:00.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:00.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:00.512 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.513 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=258 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:00.514 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=259 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:05.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:05.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:05.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:05.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:05.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:05.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:05.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:05.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:05.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:05.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:05.513 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:05.514 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:05.514 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:38:05.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:05.515 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:05.515 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:38:05.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:05.515 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:05.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:05.516 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:38:05.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:05.516 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:38:05.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:38:05.517 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:38:05.517 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:38:05.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:05.522 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:38:05.994 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:38:06.031 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:38:06.032 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:38:06.032 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:38:06.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:06.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:06.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:06.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:06.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:06.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:06.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:06.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:06.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:06.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:38:06.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:06.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:06.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:06.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:06.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:06.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:06.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:06.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:06.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:06.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:06.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:06.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:06.208 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:06.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:06.465 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:38:06.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:06.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:06.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:06.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:06.935 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:38:07.404 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:38:07.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:07.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:07.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:07.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:07.874 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:38:08.344 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:38:08.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:08.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:08.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:08.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:08.815 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:38:09.286 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:38:09.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:09.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:09.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:09.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:09.757 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:38:10.228 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:38:10.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:10.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:10.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:10.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:10.697 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:38:11.166 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:38:11.636 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:38:12.106 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:38:12.577 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:38:13.048 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:38:13.519 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:38:13.989 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:38:14.460 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:38:14.935 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:38:15.407 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:38:15.878 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:38:16.352 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:38:16.821 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:38:17.290 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:38:17.761 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:38:18.232 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:38:18.704 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:38:19.173 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:38:19.646 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:38:20.117 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:38:20.587 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:38:21.057 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:38:21.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:21.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:21.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:21.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:21.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:21.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:21.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:21.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:21.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:21.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:21.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:21.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:21.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:21.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:21.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:21.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:21.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:21.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:21.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:21.391 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:21.391 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:21.391 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:38:21.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:21.392 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:26.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:26.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:26.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:26.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:26.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:26.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:26.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:26.395 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:26.395 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:26.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:26.396 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:38:26.396 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:38:26.396 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:38:26.396 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:26.396 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:26.397 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:26.397 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:38:26.397 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:26.397 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:38:26.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:26.398 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:26.398 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:38:26.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:26.399 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:26.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:38:26.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:38:26.401 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:38:26.401 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:38:26.401 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:26.406 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:38:26.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:38:26.913 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:38:26.914 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:38:26.914 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:38:26.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:26.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:26.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:26.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:26.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:26.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:26.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:26.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:26.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:26.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:38:26.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:26.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:26.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:26.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:27.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:27.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:38:27.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:27.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:27.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:27.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:27.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:27.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:27.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:27.270 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:27.270 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:27.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:27.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:27.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:27.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:27.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:27.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:27.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:27.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:27.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:27.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:27.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:27.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:27.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:27.309 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=197 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=197 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=197 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=197 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=197 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=197 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.310 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:27.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:32.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:32.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:32.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:32.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:32.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:32.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:32.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:32.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:32.328 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:32.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:32.328 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:32.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:32.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:38:32.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:32.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:32.332 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:38:32.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:32.334 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:38:32.334 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:38:32.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:32.334 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:32.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:32.335 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:38:32.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:32.335 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:38:32.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:38:32.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:38:32.339 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:38:32.344 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:38:32.818 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:38:32.871 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:38:32.872 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:38:32.873 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:38:32.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:32.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:32.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:32.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:32.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:32.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:32.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:32.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:32.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:32.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:38:32.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:32.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:32.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:32.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:33.290 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:38:33.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:33.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:33.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:33.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:33.761 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:38:34.232 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:38:34.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:34.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:34.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:34.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:34.703 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:38:34.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:34.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:34.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:34.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:38:34.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:38:34.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:38:34.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:38:34.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:38:34.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:38:34.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:38:34.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:38:34.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:38:34.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:34.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:34.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:34.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:34.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:34.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:34.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:34.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:34.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:34.999 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:38:35.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:35.000 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.000 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.000 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.000 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.000 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:35.001 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=576 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:38:39.996 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:39.996 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:39.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:39.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:39.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:39.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:39.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:39.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:40.000 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:40.000 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:40.000 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:40.000 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:38:40.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:40.001 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:40.001 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:38:40.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:40.002 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:40.002 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:38:40.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:38:40.003 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:38:40.003 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:38:40.003 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:40.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:40.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:40.004 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:40.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:45.005 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:45.005 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:45.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:45.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:45.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:45.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:45.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:45.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:45.011 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:45.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:38:45.011 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:45.012 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:38:45.012 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:38:45.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:45.013 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:38:45.013 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:38:45.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:45.014 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:38:45.014 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:38:45.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:38:45.015 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:38:45.015 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:45.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:45.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:45.016 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:38:45.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:38:50.364 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.40.20:5700'
2026-03-02 02:38:50.364 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.40.20:5802)
2026-03-02 02:38:50.364 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.40.20:5801)
2026-03-02 02:38:50.364 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.40.22:6700'
2026-03-02 02:38:50.364 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.40.22:6802)
2026-03-02 02:38:50.364 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.40.22:6801)
2026-03-02 02:38:50.364 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.40.20:5700/1'
2026-03-02 02:38:50.364 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.40.20:5804)
2026-03-02 02:38:50.364 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.40.20:5803)
2026-03-02 02:38:50.364 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.40.20:5700/2'
2026-03-02 02:38:50.364 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.40.20:5806)
2026-03-02 02:38:50.364 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.40.20:5805)
2026-03-02 02:38:50.364 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.40.20:5700/3'
2026-03-02 02:38:50.364 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.40.20:5808)
2026-03-02 02:38:50.364 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.40.20:5807)
2026-03-02 02:38:50.364 [INFO] fake_trx.py:429 Init complete
2026-03-02 02:38:50.364 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-02 02:38:51.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:38:51.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:38:51.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:38:51.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:38:51.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:38:51.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:02.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:02.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:02.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:02.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:07.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:07.535 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:07.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:07.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:07.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:07.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:07.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:07.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:12.552 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:12.552 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:12.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:12.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:12.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:12.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:12.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:12.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:12.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:12.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:17.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:17.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:17.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:17.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:17.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:17.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:17.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:17.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:17.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:17.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:22.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:22.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:22.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:22.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:22.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:22.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:22.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:22.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:22.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:22.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:27.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:27.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:27.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:27.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:27.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:27.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:27.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:27.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:27.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:27.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:32.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:32.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:32.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:32.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:32.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:32.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:32.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:32.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:32.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:32.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:37.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:37.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:37.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:37.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:37.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:37.693 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:37.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:37.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:37.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:37.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:42.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:42.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:42.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:42.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:42.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:42.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:42.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:42.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:42.747 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:42.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:47.750 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:47.750 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:47.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:47.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:47.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:47.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:47.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:47.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:47.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:47.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:52.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:52.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:52.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:52.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:52.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:52.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 0 -> 1
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 0 -> 1
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 0 -> 1
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:39:52.782 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 0 -> 1
2026-03-02 02:39:52.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:39:52.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:52.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:52.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:52.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:57.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:39:57.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:39:57.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:57.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:39:57.791 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:57.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:57.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:39:57.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:39:57.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:39:57.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:02.805 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:02.805 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:02.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:02.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:02.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:02.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:02.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:02.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:02.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:02.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:40:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:02.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:07.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:07.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:07.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:07.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:07.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:07.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:07.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:07.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:07.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:07.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:12.848 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:12.848 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:12.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:12.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:12.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:12.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:12.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:12.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:12.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:12.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:17.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:17.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:17.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:17.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:17.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:17.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:17.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:17.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:17.894 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:17.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:22.896 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:22.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:22.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:22.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:22.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:22.898 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:22.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:22.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:22.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:22.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:31.743 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.40.20:5700'
2026-03-02 02:40:31.743 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.40.20:5802)
2026-03-02 02:40:31.743 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.40.20:5801)
2026-03-02 02:40:31.743 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.40.22:6700'
2026-03-02 02:40:31.743 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.40.22:6802)
2026-03-02 02:40:31.743 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.40.22:6801)
2026-03-02 02:40:31.743 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.40.20:5700/1'
2026-03-02 02:40:31.743 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.40.20:5804)
2026-03-02 02:40:31.743 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.40.20:5803)
2026-03-02 02:40:31.743 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.40.20:5700/2'
2026-03-02 02:40:31.743 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.40.20:5806)
2026-03-02 02:40:31.743 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.40.20:5805)
2026-03-02 02:40:31.743 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.40.20:5700/3'
2026-03-02 02:40:31.743 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.40.20:5808)
2026-03-02 02:40:31.743 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.40.20:5807)
2026-03-02 02:40:31.743 [INFO] fake_trx.py:429 Init complete
2026-03-02 02:40:31.743 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-02 02:40:32.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:32.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:32.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:32.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:32.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:32.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:35.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:35.921 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:35.921 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:35.921 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:35.921 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 0 -> 1
2026-03-02 02:40:35.924 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:40:35.925 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:40:35.925 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:40:35.925 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:35.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:35.925 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:40:35.926 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:40:35.926 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 0 -> 1
2026-03-02 02:40:35.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:35.931 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:40:35.931 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:40:35.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:40:35.931 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:35.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:35.931 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:40:35.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:40:35.932 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 0 -> 1
2026-03-02 02:40:35.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:35.933 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:40:35.934 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:40:35.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:40:35.934 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:35.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:35.934 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:40:35.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:40:35.934 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 0 -> 1
2026-03-02 02:40:35.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:35.935 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:40:35.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:40:35.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:40:35.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:40:35.935 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:40:35.936 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:40:35.936 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:40:35.936 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:35.941 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:40:36.414 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:40:36.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:36.477 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:40:36.479 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:40:36.479 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:40:36.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:36.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:36.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:36.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:36.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:36.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:36.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:36.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:36.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:36.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:36.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:36.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:36.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:36.883 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:40:36.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:36.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:36.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:36.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:37.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:37.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:37.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:37.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:37.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:37.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:37.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:37.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:37.103 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:37.103 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:37.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:37.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:37.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:37.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.352 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:40:37.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:37.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:37.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:37.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:37.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:37.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:37.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:37.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:37.579 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:37.579 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:37.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:37.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:37.651 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:37.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:37.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:37.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:37.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:37.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:37.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:37.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:37.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:37.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:37.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:37.823 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:40:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:37.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:37.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:37.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:37.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:37.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:37.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:37.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:38.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:38.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:38.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:38.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:38.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:38.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:38.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:38.294 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:40:38.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:38.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:38.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:38.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:38.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:38.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:38.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:38.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:38.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:38.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:38.765 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:40:38.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:38.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:38.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:38.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:39.236 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:40:39.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:39.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:39.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:39.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:39.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:39.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:39.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:39.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:39.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:39.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:39.296 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:39.296 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:39.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:39.506 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:39.507 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:40:39.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:39.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:39.706 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:40:39.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:39.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:39.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:39.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:40.177 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:40:40.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:40.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:40.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:40.309 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:40.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:40.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:40.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:40.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:40.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:40.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:40.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:40.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:40.448 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:40.448 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:40:40.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.648 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:40:40.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:40.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:40.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:40.851 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:40.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:40.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:40.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:40.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:40.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:40.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:40.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:40.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:40.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:40.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:40.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:40.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:40.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:41.119 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:40:41.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:41.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:41.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:41.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:41.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:41.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:41.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:41.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:41.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:41.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:41.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:41.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:41.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:41.589 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:40:41.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:41.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:41.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:41.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:42.060 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:40:42.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:42.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:42.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:42.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:42.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:42.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:42.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:42.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:42.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:42.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:42.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:42.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:42.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:42.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:42.533 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:40:42.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:42.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:42.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:42.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:43.002 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:40:43.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:43.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:43.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:43.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:43.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:43.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:43.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:43.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:43.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:43.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:43.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:43.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:43.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:43.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:40:43.508 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:43.508 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:40:43.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:43.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:43.943 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:40:44.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:44.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:44.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:44.268 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:44.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:44.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:44.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:44.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:44.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:44.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:44.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:44.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:44.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:44.413 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:40:44.449 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:44.449 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:40:44.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:44.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:44.884 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:40:45.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:45.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:45.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:45.293 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:45.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:45.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:45.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:45.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:45.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:45.314 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:45.314 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:45.355 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:40:45.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:45.418 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:45.418 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:45.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:45.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:45.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:45.515 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:45.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:45.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:45.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:45.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:45.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:45.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:45.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:45.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:45.653 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:45.653 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:45.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.826 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:40:45.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:45.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:46.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:46.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:46.003 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:46.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:46.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:46.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:46.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:46.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:46.025 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:46.025 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:46.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:46.125 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:46.125 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:46.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.296 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:40:46.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:46.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:46.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:46.494 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:46.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:46.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:46.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:46.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:46.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:46.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:46.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:46.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:46.592 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:46.592 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:46.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.766 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:40:46.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:46.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:46.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:46.976 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:46.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:46.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:46.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:46.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:46.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:46.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:46.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:46.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:47.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:47.059 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:47.059 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:47.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:47.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:47.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:47.151 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:47.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:47.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:47.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:47.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:47.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:47.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:47.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:47.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:47.234 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:40:47.270 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:47.270 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:47.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:47.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:47.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:47.641 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:47.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:47.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:47.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:47.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:47.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:47.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:47.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:47.703 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:40:47.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:47.765 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:47.765 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:47.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:47.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:48.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:48.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:48.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:48.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:48.130 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:48.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:48.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:48.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:48.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:48.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:40:48.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:40:48.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:40:48.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:40:48.171 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:40:48.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:48.234 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:40:48.234 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:40:48.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:48.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:48.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:40:48.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:48.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:48.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:48.619 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:40:48.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:48.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:48.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:48.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:48.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:48.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:48.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:48.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:48.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:48.633 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:40:48.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:48.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2754 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:40:53.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:53.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:53.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:53.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:53.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:53.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:53.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:53.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:53.635 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:53.635 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:53.635 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:40:53.635 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:40:53.636 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:40:53.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:40:53.636 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:53.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:53.636 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:40:53.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:40:53.636 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:40:53.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:40:53.637 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:40:53.637 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:40:53.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:53.638 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:40:53.639 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:40:53.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:40:53.639 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:53.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:53.639 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:40:53.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:40:53.639 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:40:53.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:53.640 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:40:53.641 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:40:53.641 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:40:53.641 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:53.646 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:40:54.114 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:40:54.158 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:40:54.158 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:40:54.159 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:40:54.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:40:54.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:40:54.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:40:54.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
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2026-03-02 02:40:54.582 [DEBUG] clck_gen.py:113 IND CLOCK 204
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2026-03-02 02:40:54.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:54.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:54.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:54.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:54.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:40:54.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:54.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:54.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:54.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:54.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:54.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:54.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:54.728 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:54.728 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:54.728 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:40:54.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:59.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:40:59.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:40:59.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:59.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:59.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:59.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:59.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:40:59.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:59.739 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:59.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:40:59.739 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:40:59.740 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:40:59.740 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:40:59.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:40:59.741 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:59.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:40:59.741 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:40:59.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:40:59.741 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:40:59.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:40:59.743 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:40:59.743 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:40:59.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:40:59.745 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:40:59.745 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:40:59.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:40:59.748 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:40:59.748 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:40:59.748 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:40:59.753 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:41:00.225 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:41:00.272 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:41:00.273 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:41:00.274 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:41:00.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:00.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:00.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:00.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:00.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:00.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:00.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:00.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:00.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:00.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:00.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:00.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:00.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:00.303 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:00.303 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:41:00.303 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:41:00.303 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:41:05.303 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:41:05.303 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:41:05.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:05.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:05.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:05.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:05.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:05.309 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:41:05.309 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:05.309 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:41:05.309 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:41:05.311 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:41:05.311 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:41:05.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:05.313 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:41:05.313 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:41:05.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:41:05.313 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:05.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:05.313 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:41:05.314 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:41:05.314 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:41:05.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:05.315 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:41:05.315 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:41:05.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:41:05.316 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:05.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:05.316 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:41:05.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:41:05.316 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:41:05.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.319 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:41:05.319 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:41:05.319 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:41:05.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:05.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:05.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:41:05.796 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:41:05.846 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:41:05.847 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:41:05.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:05.848 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:41:05.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:05.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:05.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:05.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:05.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:05.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:05.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:05.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:05.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:05.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:05.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:05.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:41:05.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:41:05.872 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:41:05.872 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:41:05.873 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:41:05.873 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:41:05.873 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:41:05.873 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:41:10.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:41:10.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:41:10.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:10.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:10.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:10.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:10.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:10.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:41:10.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:10.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:41:10.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:41:10.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:41:10.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:41:10.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:41:10.883 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:10.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:10.883 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:41:10.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:41:10.884 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:41:10.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:10.885 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:41:10.885 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:41:10.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:41:10.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:10.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:10.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:41:10.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:41:10.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:41:10.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:41:10.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:41:10.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:41:10.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:10.891 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:41:10.892 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:41:10.892 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:41:10.892 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:10.897 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:41:11.369 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:41:11.415 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:41:11.417 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:41:11.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:11.418 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:41:11.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:11.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:11.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:11.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:11.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:11.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:11.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:11.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:11.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:11.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:11.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:11.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:41:11.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:41:11.659 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:41:16.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:41:16.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:41:16.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:16.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:16.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:16.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:16.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:41:16.667 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:41:16.667 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:16.667 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:41:16.667 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:41:16.669 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:41:16.669 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:41:16.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:16.671 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:41:16.672 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:41:16.672 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:41:16.672 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:16.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:41:16.672 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:41:16.672 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:41:16.672 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:41:16.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:41:16.674 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:41:16.674 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:41:16.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:41:16.678 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:41:16.678 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:41:16.678 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:41:16.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:16.683 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:41:17.154 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:41:17.202 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:41:17.203 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:41:17.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:17.205 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:41:17.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:17.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:17.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:17.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:17.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:17.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:17.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:17.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:17.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:17.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:17.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:17.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:17.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:17.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:17.626 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:41:17.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:17.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:17.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:17.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:18.096 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:41:18.567 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:41:18.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:18.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:18.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:18.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:19.038 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:41:19.509 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:41:19.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:19.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:19.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:19.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:19.980 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:41:20.450 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:41:20.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:20.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:20.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:20.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:20.921 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:41:21.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:21.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:21.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:21.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:21.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:21.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:21.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:21.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:21.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:21.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:21.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:21.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:21.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:21.392 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:41:21.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:21.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:21.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:21.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:21.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:21.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:41:21.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:41:21.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:41:21.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:41:21.863 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:41:22.333 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:41:22.804 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:41:23.275 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:41:23.746 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:41:24.216 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:41:24.687 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:41:25.158 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:41:25.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:25.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:25.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:25.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:25.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:25.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:25.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:25.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:25.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:25.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:25.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:25.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:25.629 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:41:25.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:25.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:25.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:25.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:25.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:26.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:26.100 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:41:26.570 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:41:27.041 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:41:27.512 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:41:27.983 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:41:28.453 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:41:28.924 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:41:29.395 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:41:29.866 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:41:30.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:30.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:30.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:30.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:30.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:30.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:30.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:30.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:30.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:30.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:30.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:30.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:30.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:30.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:30.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:30.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:30.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:30.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:30.337 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:41:30.807 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:41:31.279 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:41:31.749 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:41:32.220 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:41:32.690 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:41:33.161 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:41:33.632 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:41:34.103 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:41:34.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:34.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:34.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:34.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:34.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:34.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:34.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:34.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:34.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:34.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:34.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:34.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:34.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:34.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:34.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:34.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:34.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:34.573 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:41:34.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:35.044 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:41:35.515 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:41:35.986 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:41:36.457 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:41:36.928 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:41:37.398 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:41:37.869 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:41:38.340 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:41:38.810 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:41:38.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:38.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:38.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:38.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:38.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:38.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:38.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:38.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:38.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:38.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:38.933 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:38.933 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:38.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:38.952 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:41:38.952 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:41:38.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:38.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:39.281 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:41:39.752 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:41:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:40.223 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:41:40.693 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:41:41.164 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:41:41.635 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:41:42.106 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:41:42.577 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:41:43.048 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:41:43.519 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:41:43.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:43.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:43.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:43.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:43.787 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:41:43.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:43.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:43.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:43.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:43.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:43.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:43.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:43.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:43.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:43.849 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:41:43.849 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:41:43.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:43.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:43.989 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:41:44.460 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:41:44.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:44.930 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:41:45.422 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:41:45.894 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:41:46.365 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:41:46.836 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:41:47.307 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:41:47.779 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:41:48.252 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:41:48.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:48.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:48.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:48.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:48.636 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:41:48.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:48.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:48.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:48.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:48.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:48.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:48.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:48.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:48.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:48.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:48.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:48.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:48.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:48.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:48.723 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:41:49.194 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:41:49.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:49.665 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:41:50.136 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:41:50.608 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:41:51.079 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:41:51.553 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:41:52.024 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:41:52.496 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:41:52.968 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:41:53.441 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:41:53.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:53.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:53.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:53.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:53.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:53.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:53.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:53.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:53.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:53.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:53.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:53.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:53.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:53.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:53.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:53.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:53.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:53.912 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:41:54.384 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:41:54.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:54.857 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:41:55.330 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:41:55.802 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:41:56.273 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:41:56.745 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:41:57.217 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:41:57.689 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:41:58.160 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:41:58.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:58.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:58.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:58.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:58.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:41:58.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:41:58.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:41:58.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:58.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:58.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:58.415 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:41:58.415 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:41:58.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:41:58.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:58.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:41:58.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:41:58.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:58.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:41:58.631 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:41:59.102 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:41:59.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:41:59.573 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:42:00.044 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:42:00.515 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:42:00.986 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:42:01.460 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:42:01.930 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:42:02.399 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:42:02.867 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:42:03.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:03.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:03.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:03.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:03.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:03.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:03.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:03.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:03.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:03.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:03.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:03.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:03.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:03.192 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:03.192 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:42:03.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:03.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:03.335 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:42:03.803 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:42:03.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:04.271 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 02:42:04.740 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 02:42:05.208 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 02:42:05.675 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 02:42:06.143 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 02:42:06.611 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 02:42:07.080 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 02:42:07.548 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 02:42:07.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:07.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:07.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:07.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:07.933 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:07.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:07.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:07.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:07.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:07.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:07.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:07.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:07.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:07.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:07.968 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:07.968 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:42:07.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:07.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:08.016 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 02:42:08.486 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 02:42:08.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:08.955 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 02:42:09.423 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 02:42:09.892 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 02:42:10.361 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 02:42:10.830 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 02:42:11.299 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 02:42:11.768 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 02:42:12.236 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 02:42:12.705 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 02:42:12.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:12.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:12.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:12.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:12.769 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:12.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:12.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:12.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:12.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:12.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:12.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:12.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:12.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:12.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:12.795 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:12.795 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:12.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:12.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:12.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:13.174 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 02:42:13.644 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 02:42:14.113 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 02:42:14.581 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 02:42:15.050 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 02:42:15.518 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 02:42:15.987 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 02:42:16.456 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 02:42:16.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:16.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:16.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:16.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:16.859 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:16.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:16.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:16.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:16.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:16.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:16.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:16.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:16.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:16.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:16.926 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 02:42:16.928 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:16.928 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:16.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:16.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:17.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:17.394 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 02:42:17.863 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 02:42:18.332 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 02:42:18.800 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 02:42:19.268 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 02:42:19.737 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 02:42:20.205 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 02:42:20.674 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 02:42:21.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:21.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:21.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:21.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:21.096 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:21.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:21.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:21.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:21.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:21.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:21.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:21.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:21.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:21.142 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:21.142 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:21.142 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 02:42:21.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:21.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:21.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:21.610 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 02:42:22.078 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 02:42:22.546 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 02:42:23.014 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 02:42:23.482 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 02:42:23.950 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 02:42:24.418 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 02:42:24.887 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 02:42:25.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:25.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:25.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:25.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:25.332 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:25.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:25.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:25.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:25.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:25.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:25.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:25.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:25.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:25.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:25.353 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:25.353 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:25.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:25.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:25.354 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 02:42:25.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:25.822 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 02:42:26.290 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 02:42:26.759 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 02:42:27.229 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 02:42:27.697 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 02:42:28.166 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 02:42:28.636 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 02:42:29.105 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 02:42:29.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:29.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:29.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:29.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:29.566 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:29.574 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 02:42:29.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:29.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:29.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:29.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:29.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:29.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:29.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:29.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:29.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:29.619 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:29.619 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:29.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:29.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:29.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:30.043 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 02:42:30.511 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 02:42:30.980 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 02:42:31.448 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 02:42:31.916 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 02:42:32.385 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 02:42:32.854 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 02:42:33.323 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 02:42:33.792 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 02:42:33.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:33.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:33.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:33.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:33.964 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:33.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:33.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:33.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:33.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:33.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:33.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:33.977 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:33.977 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:34.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:34.026 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:34.026 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:34.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:34.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:34.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:34.261 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 02:42:34.729 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 02:42:35.197 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 02:42:35.665 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 02:42:36.134 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 02:42:36.602 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 02:42:37.072 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 02:42:37.541 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 02:42:38.010 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 02:42:38.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:38.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:38.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:38.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:38.204 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:38.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:38.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:38.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:38.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:38.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:38.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:38.222 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:38.222 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:38.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:38.246 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:38.246 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:38.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:38.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:38.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:38.479 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 02:42:38.948 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 02:42:39.417 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 02:42:39.886 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 02:42:40.355 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 02:42:40.825 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 02:42:41.294 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 02:42:41.764 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 02:42:42.234 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-02 02:42:42.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:42.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:42.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:42.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:42.439 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:42.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:42.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:42.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:42.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:42.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:42.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:42.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:42.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:42.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:42.468 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:42.468 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:42:42.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:42.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:42.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:42.704 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-02 02:42:43.181 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-02 02:42:43.654 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-02 02:42:44.127 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-02 02:42:44.604 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-02 02:42:45.077 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-02 02:42:45.549 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-02 02:42:46.021 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-02 02:42:46.489 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-02 02:42:46.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:46.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:46.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:46.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:46.683 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:46.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:42:46.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:42:46.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:42:46.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:42:46.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:42:46.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:42:46.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:42:46.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:42:46.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:42:46.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:42:46.699 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:42:46.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19529 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:46.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19529 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:46.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19529 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:46.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19529 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:46.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19529 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:46.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=19529 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:51.698 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:42:51.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:42:51.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:42:51.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:42:51.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:42:51.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:42:51.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:42:51.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:42:51.713 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:51.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:42:51.714 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:42:51.715 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:42:51.716 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:42:51.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:42:51.716 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:51.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:42:51.716 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:42:51.717 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:42:51.717 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:42:51.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:42:51.717 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:42:51.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:42:51.719 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:42:51.719 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:42:51.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:51.721 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:42:51.721 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:42:51.721 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:42:51.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:42:51.722 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:51.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:51.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.726 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:42:56.726 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:42:56.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:42:56.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:42:56.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:42:56.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:42:56.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:42:56.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:42:56.737 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:56.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:42:56.737 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:42:56.739 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:42:56.739 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:42:56.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:42:56.739 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:56.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:42:56.739 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:42:56.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:42:56.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:42:56.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:42:56.741 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:42:56.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:42:56.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:42:56.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:56.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:42:56.741 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:42:56.742 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:42:56.742 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:42:56.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:42:56.743 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:42:56.743 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:42:56.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.745 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:42:56.745 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:42:56.745 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:42:56.745 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:42:56.750 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:42:57.219 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:42:57.270 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:42:57.272 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:42:57.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:57.274 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:42:57.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:57.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:57.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:57.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.299 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:57.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:57.299 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:57.299 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:57.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:57.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:57.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:57.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:57.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:57.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:57.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:57.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:57.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:57.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:57.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:57.445 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:57.445 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:57.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:57.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:57.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:57.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.689 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:42:57.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:42:57.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:42:57.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:42:57.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:42:57.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:57.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:57.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:57.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:57.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:57.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:57.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:57.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:57.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:57.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:57.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:57.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:57.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:57.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:57.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:58.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:58.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:58.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:58.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:58.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:58.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:58.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:58.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:58.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:58.158 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:42:58.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:58.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:58.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:58.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:58.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:58.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:58.615 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=407 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:42:58.626 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:42:58.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:58.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:58.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:58.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:58.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:58.636 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:58.636 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:58.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:58.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:58.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:58.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:58.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:42:58.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:42:58.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:42:58.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:42:59.096 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:42:59.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:59.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:59.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:59.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:59.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:59.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:59.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:59.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:59.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:59.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:59.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:59.196 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:59.196 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:42:59.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.565 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:42:59.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:59.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:59.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:59.671 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:42:59.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:42:59.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:42:59.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:42:59.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:42:59.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:42:59.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:42:59.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:42:59.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:42:59.735 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:42:59.735 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:42:59.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:42:59.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:42:59.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:42:59.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:42:59.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:00.035 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:43:00.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:00.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:00.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:00.207 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:00.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:00.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:00.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:00.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:00.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:00.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:00.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:00.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:00.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:00.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:00.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:00.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.505 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:43:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:00.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:00.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:00.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:00.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:00.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:00.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:00.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:00.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:00.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:00.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:00.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:00.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:00.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:00.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:00.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:00.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:00.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:00.975 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:43:01.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:01.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:01.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:01.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:01.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:01.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:01.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:01.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:01.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:01.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:01.290 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:01.290 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:01.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:01.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:01.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:01.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:01.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:01.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:01.444 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:43:01.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:01.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:01.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:01.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:01.914 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:43:02.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:02.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:02.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:02.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:02.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:02.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:02.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:02.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:02.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:02.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:02.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:02.258 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:02.258 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:43:02.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.387 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:43:02.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:02.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:02.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:02.668 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:02.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:02.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:02.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:02.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:02.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:02.688 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:02.688 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:02.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:02.738 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:02.738 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:43:02.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:02.857 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:43:03.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:03.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.202 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:03.202 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:03.202 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:03.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:03.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:03.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:03.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:03.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:03.211 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:03.211 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:03.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:03.267 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:03.267 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:03.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.331 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:43:03.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:03.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:03.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:03.485 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:03.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:03.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:03.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:03.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:03.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:03.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:03.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:03.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:03.540 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:03.540 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:03.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.801 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:43:03.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:03.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:03.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:03.976 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:03.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:03.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:03.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:03.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:03.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:03.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:03.998 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:03.998 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:04.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:04.050 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:04.050 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:04.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.270 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:43:04.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:04.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:04.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:04.465 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:04.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:04.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:04.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:04.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:04.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:04.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:04.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:04.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:04.541 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:04.541 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:04.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.740 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:43:04.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:04.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:04.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:04.954 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:04.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:04.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:04.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:04.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:04.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:04.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:04.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:04.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:05.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:05.025 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:05.025 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:05.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:05.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:05.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:05.134 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:05.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:05.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:05.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:05.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:05.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:05.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:05.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:05.210 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:43:05.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:05.212 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:05.212 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:05.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:05.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:05.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:05.617 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:05.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:05.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:05.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:05.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:05.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:05.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:05.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:05.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:05.679 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:05.679 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:05.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:05.681 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:43:06.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:06.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:06.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:06.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:06.112 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:06.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:06.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:06.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:06.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:06.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:06.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:06.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:06.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:06.155 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:43:06.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:06.181 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:06.182 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:06.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:06.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:06.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:06.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:06.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:06.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:06.601 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:06.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:06.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:06.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:06.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:06.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:43:06.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:43:06.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:43:06.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:43:06.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:43:06.613 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:43:06.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:06.613 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:11.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:43:11.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:43:11.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:43:11.619 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:43:11.619 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:43:11.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:43:11.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:43:11.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:43:11.633 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:11.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:43:11.633 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:43:11.635 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:43:11.635 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:43:11.635 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:43:11.635 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:11.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:43:11.636 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:43:11.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:43:11.636 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:43:11.637 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:43:11.637 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:43:11.637 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:43:11.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:43:11.639 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:43:11.639 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:43:11.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.641 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:43:11.641 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:43:11.641 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:43:11.642 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:11.646 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:43:12.120 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:43:12.294 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:43:12.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:12.295 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:43:12.296 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:43:12.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:12.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:12.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:12.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:12.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:12.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:12.305 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:12.305 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:12.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:12.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:12.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:12.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:12.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:12.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:12.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:12.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:12.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:12.758 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:43:13.233 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:43:13.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:13.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:13.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:13.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:13.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:13.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:13.707 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:43:13.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:13.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:13.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:13.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:13.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:13.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:13.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:13.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:13.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:13.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:13.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:13.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:13.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:13.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:13.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:13.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:13.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:14.177 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:43:14.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:14.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:14.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:14.646 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:43:14.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:14.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:15.116 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:43:15.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:15.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:15.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:15.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:15.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:15.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:15.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:15.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:15.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:15.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:15.344 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:15.344 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:15.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:15.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:15.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:15.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:15.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:15.587 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:43:15.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:15.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:15.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:15.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:16.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:16.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:16.057 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:43:16.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:16.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:16.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:16.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:16.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:16.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:16.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:16.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:16.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:16.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:16.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:16.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:16.526 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:43:16.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:16.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:16.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:16.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:16.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:16.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:16.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:16.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:16.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:16.996 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:43:17.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:17.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:17.466 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:43:17.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:17.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:17.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:17.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:17.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:17.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:17.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:17.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:17.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:17.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:17.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:17.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:17.936 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:43:17.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:17.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:17.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:17.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:17.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:18.409 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:43:18.886 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:43:19.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:19.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:19.359 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:43:19.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:19.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:19.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:19.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:19.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:19.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:19.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:19.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:19.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:19.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:19.519 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:19.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:19.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:19.569 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:19.569 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:43:19.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:19.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:19.831 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:43:20.300 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:43:20.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:20.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:20.771 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:43:20.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:20.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:20.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:20.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:20.995 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:21.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:21.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:21.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:21.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:21.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:21.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:21.008 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:21.008 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:21.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:21.058 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:21.058 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:43:21.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:21.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:21.243 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:43:21.713 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:43:22.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:22.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:22.183 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:43:22.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:22.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:22.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:22.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:22.492 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:22.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:22.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:22.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:22.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:22.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:22.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:22.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:22.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:22.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:22.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:22.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:22.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:22.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:22.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:22.652 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:43:23.120 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:43:23.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:23.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:23.588 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:43:23.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:23.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:23.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:23.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:23.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:23.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:23.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:23.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:23.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:23.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:23.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:23.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:24.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:24.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:24.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:24.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:24.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:24.058 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:43:24.525 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:43:24.995 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:43:25.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:25.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:25.464 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:43:25.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:25.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:25.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:25.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:25.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:25.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:25.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:25.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:25.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:25.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:25.486 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:25.486 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:25.532 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:25.532 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:25.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:25.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:25.933 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:43:26.402 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:43:26.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:26.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:26.870 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:43:27.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:27.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:27.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:27.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:27.339 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:43:27.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:27.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:27.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:27.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:27.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:27.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:27.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:27.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:27.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:27.389 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:27.389 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:43:27.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:27.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:27.807 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:43:28.276 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:43:28.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:28.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:28.745 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:43:28.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:28.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:28.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:28.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:28.761 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:28.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:28.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:28.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:28.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:28.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:28.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:28.775 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:28.775 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:28.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:28.821 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:28.821 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:43:28.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:28.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:29.213 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:43:29.681 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:43:29.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:29.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:30.149 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:43:30.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:30.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:30.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:30.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:30.256 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:30.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:30.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:30.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:30.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:30.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:30.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:30.267 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:30.267 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:30.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:30.313 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:30.313 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:30.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:30.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:30.617 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:43:31.085 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:43:31.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:31.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:31.554 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:43:31.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:31.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:31.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:31.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:31.706 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:31.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:31.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:31.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:31.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:31.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:31.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:31.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:31.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:31.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:31.761 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:31.761 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:31.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:31.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:32.023 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:43:32.491 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:43:32.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:32.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:32.959 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:43:33.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:33.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:33.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:33.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:33.131 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:33.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:33.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:33.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:33.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:33.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:33.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:33.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:33.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:33.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:33.194 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:33.194 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:33.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:33.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:33.428 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:43:33.897 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:43:34.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:34.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:34.366 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:43:34.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:34.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:34.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:34.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:34.553 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:34.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:34.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:34.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:34.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:34.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:34.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:34.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:34.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:34.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:34.610 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:34.610 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:34.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:34.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:34.835 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:43:35.305 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:43:35.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:35.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:35.774 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:43:35.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:35.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:35.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:35.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:35.985 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:35.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:35.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:35.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:36.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:36.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:36.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:36.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:36.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:36.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:36.045 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:36.045 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:36.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:36.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:36.245 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:43:36.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:36.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:36.716 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:43:37.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:37.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:37.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:37.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:37.106 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:37.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:37.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:37.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:37.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:37.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:37.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:37.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:37.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:37.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:37.165 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:37.165 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:37.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:37.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:37.187 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:43:37.657 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:43:38.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:38.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:38.128 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:43:38.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:38.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:38.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:38.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:38.538 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:38.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:38.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:38.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:38.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:38.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:38.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:38.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:38.557 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:38.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:38.599 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:43:38.603 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:38.603 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:38.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:38.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:39.070 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:43:39.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:39.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:39.540 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:43:39.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:39.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:39.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:39.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:39.968 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:39.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:39.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:39.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:39.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:39.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:39.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:39.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:39.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:40.011 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:43:40.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:40.030 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:43:40.030 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:43:40.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:40.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:40.482 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:43:40.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:40.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:40.953 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:43:41.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:41.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:41.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:41.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:41.399 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:43:41.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:41.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:41.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:41.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:41.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:43:41.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:43:41.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:43:41.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:43:41.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:43:41.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:43:41.405 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:43:41.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6424 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:43:46.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:43:46.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:43:46.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:43:46.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:43:46.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:43:46.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:43:46.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:43:46.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:43:46.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:46.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:43:46.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:43:46.414 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:43:46.415 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:43:46.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:43:46.415 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:46.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:43:46.415 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:43:46.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:43:46.415 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:43:46.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:43:46.417 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:43:46.417 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:43:46.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:46.419 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:43:46.419 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:43:46.419 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:43:46.419 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:43:46.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:43:46.419 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:43:46.419 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:43:46.420 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:43:46.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.422 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:43:46.423 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:43:46.423 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:43:46.423 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:43:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:43:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:43:46.428 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:43:46.900 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:43:46.967 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:43:46.968 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:43:46.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:46.969 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:43:46.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:46.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:46.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:46.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:46.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:46.990 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:46.990 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:46.990 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:47.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:47.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:47.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:47.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:47.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:47.372 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:43:47.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:47.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:47.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:47.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:47.842 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:43:48.313 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:43:48.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:48.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:48.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:48.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:48.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:43:49.255 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:43:49.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:49.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:49.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:49.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:49.725 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:43:50.196 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:43:50.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:50.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:50.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:50.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:50.667 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:43:50.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:50.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:50.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:50.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:50.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:50.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:50.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:50.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:50.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:50.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:50.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:50.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:50.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:50.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:50.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:50.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:50.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:51.138 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:43:51.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:43:51.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:43:51.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:43:51.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:43:51.609 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:43:52.079 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:43:52.549 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:43:53.020 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:43:53.491 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:43:53.962 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:43:54.434 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:43:54.905 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:43:55.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:55.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:55.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:55.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:55.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:55.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:55.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:55.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:55.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:55.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:55.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:55.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:55.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:55.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:55.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:55.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:55.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:55.377 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:43:55.848 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:43:56.320 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:43:56.791 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:43:57.262 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:43:57.734 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:43:58.205 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:43:58.676 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:43:59.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:59.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:59.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:59.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:59.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:43:59.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:43:59.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:43:59.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:59.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:59.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:59.130 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:43:59.130 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:43:59.146 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:43:59.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:43:59.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:43:59.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:43:59.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:59.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:43:59.617 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:44:00.088 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:44:00.559 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:44:01.029 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:44:01.500 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:44:01.970 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:44:02.441 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:44:02.912 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:44:03.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:03.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:03.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:03.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:03.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:03.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:03.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:03.383 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:44:03.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:03.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:03.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:03.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:03.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:03.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:03.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:03.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:03.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:03.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:03.854 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:44:04.325 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:44:04.796 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:44:05.267 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:44:05.737 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:44:06.208 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:44:06.679 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:44:07.149 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:44:07.620 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:44:08.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:08.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:08.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:08.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:08.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:08.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:08.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:08.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:08.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:08.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:08.045 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:08.045 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:08.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:08.091 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:44:08.093 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:44:08.093 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:44:08.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:08.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:08.562 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:44:09.033 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:44:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:44:09.974 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:44:10.445 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:44:10.916 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:44:11.386 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:44:11.857 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:44:12.328 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:44:12.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:12.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:12.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:12.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:12.405 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:44:12.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:12.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:12.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:12.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:12.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:12.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:12.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:12.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:12.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:12.486 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:44:12.486 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:44:12.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:12.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:12.799 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:44:13.270 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:44:13.740 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:44:14.211 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:44:14.682 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:44:15.153 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:44:15.623 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:44:16.094 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:44:16.565 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:44:16.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:16.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:16.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:16.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:16.785 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:44:16.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:16.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:16.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:16.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:16.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:16.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:16.801 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:16.801 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:16.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:16.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:16.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:16.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:16.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:16.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:17.036 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:44:17.506 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:44:17.977 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:44:18.448 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:44:18.918 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:44:19.389 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:44:20.526 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:44:20.997 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:44:21.468 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:44:21.939 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:44:22.410 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:44:22.881 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:44:23.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:23.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:23.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:23.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:23.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:23.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:23.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:44:23.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:44:23.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:44:23.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:44:23.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:44:23.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:44:23.206 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:44:28.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:44:28.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:44:28.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:44:28.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:44:28.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:44:28.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:44:28.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:44:28.213 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:44:28.213 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:28.213 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:44:28.213 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:44:28.215 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:44:28.215 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:44:28.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:44:28.217 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:44:28.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:44:28.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:28.218 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:44:28.218 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:44:28.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:44:28.218 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:28.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:44:28.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:44:28.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:44:28.219 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:44:28.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:28.221 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:44:28.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:44:28.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:44:28.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:44:34.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:44:34.227 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:44:34.228 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.228 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:44:34.228 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:44:34.228 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:44:34.228 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:44:34.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:44:34.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:44:34.233 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:44:34.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:44:35.174 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:44:35.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:35.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:35.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:35.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:35.643 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:44:36.114 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:44:36.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:36.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:36.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:36.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:36.582 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:44:37.051 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:44:37.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:37.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:37.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:37.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:37.521 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:44:37.634 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:44:37.635 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:44:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:37.637 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:44:37.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:37.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:37.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:37.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:37.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:37.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:37.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:37.664 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:37.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:37.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:37.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:37.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:37.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:37.991 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:44:38.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:38.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:38.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:38.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:38.460 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:44:38.930 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:44:39.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:44:39.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:44:39.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:44:39.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:44:39.403 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:44:39.872 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:44:40.341 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:44:40.810 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:44:41.279 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:44:41.748 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:44:42.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:42.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:42.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:42.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:42.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:42.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:42.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:42.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:42.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:42.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:42.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:42.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:42.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:42.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:42.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:42.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:42.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:42.216 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:44:42.684 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:44:43.153 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:44:43.622 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:44:44.090 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:44:44.558 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:44:45.027 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:44:45.495 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:44:45.963 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:44:46.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:46.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:46.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:46.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:46.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:46.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:46.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:46.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:46.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:46.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:46.381 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:46.381 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:46.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:46.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:46.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:46.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:46.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:46.432 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:44:46.901 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:44:47.369 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:44:47.837 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:44:48.306 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:44:48.776 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:44:49.244 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:44:49.712 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:44:50.180 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:44:50.648 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:44:50.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:50.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:50.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:50.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:50.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:50.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:50.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:50.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:50.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:50.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:50.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:50.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:50.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:50.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:50.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:50.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:50.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:51.116 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:44:51.584 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:44:52.052 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:44:52.519 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:44:52.988 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:44:53.455 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:44:53.923 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:44:54.391 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:44:54.859 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:44:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:55.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:55.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:55.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:55.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:55.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:55.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:55.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:55.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:55.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:55.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:55.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:55.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:55.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:55.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:55.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:55.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:55.328 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:44:55.796 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:44:56.263 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:44:56.731 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:44:57.199 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:44:57.666 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:44:58.134 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:44:58.602 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:44:59.069 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:44:59.537 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:44:59.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:59.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:59.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:59.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:59.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:44:59.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:44:59.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:44:59.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:59.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:44:59.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:44:59.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:44:59.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:44:59.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:44:59.736 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:44:59.736 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:44:59.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:44:59.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:00.005 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:45:00.473 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:45:00.941 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:45:01.409 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:45:01.878 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:45:02.346 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:45:02.815 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:45:03.283 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:45:03.751 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:45:04.219 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:45:04.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:04.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:04.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:04.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:04.512 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:04.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:04.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:04.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:04.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:04.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:04.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:04.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:04.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:04.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:04.564 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:04.564 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:45:04.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:04.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:04.686 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:45:05.154 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:45:05.622 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:45:06.091 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:45:06.558 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:45:07.025 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:45:07.493 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:45:07.961 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:45:08.429 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:45:08.897 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:45:09.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:09.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:09.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:09.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:09.345 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:09.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:09.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:09.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:09.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:09.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:09.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:09.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:09.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:09.364 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:45:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:45:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:09.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:09.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:09.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:09.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:09.832 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:45:10.300 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:45:10.768 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:45:11.236 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:45:11.703 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:45:12.171 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:45:12.638 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:45:13.106 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:45:13.574 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:45:14.042 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:45:14.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:14.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:14.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:14.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:14.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:14.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:14.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:14.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:14.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:14.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:14.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:14.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:14.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:14.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:14.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:14.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:14.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:14.510 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:45:14.979 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:45:15.449 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:45:15.918 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:45:16.387 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:45:16.856 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:45:17.326 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:45:17.794 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:45:18.264 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:45:18.732 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:45:19.201 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:45:19.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:19.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:19.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:19.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:19.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:19.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:19.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:19.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:19.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:19.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:19.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:19.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:19.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:45:19.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:19.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:19.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:19.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:19.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:19.669 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:45:20.137 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:45:20.606 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:45:21.073 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:45:21.541 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 02:45:22.008 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 02:45:22.476 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 02:45:22.944 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 02:45:23.412 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 02:45:23.879 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 02:45:24.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:24.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:24.202 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:24.202 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:24.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:24.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:24.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:24.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:24.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:24.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:24.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:24.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:24.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:24.270 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:24.270 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:45:24.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:24.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:24.348 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 02:45:24.816 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 02:45:25.284 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 02:45:25.752 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 02:45:26.220 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 02:45:26.689 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 02:45:27.157 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 02:45:27.624 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 02:45:28.092 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 02:45:28.560 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 02:45:29.028 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 02:45:29.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:29.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:29.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:29.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:29.449 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:29.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:29.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:29.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:29.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:29.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:29.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:29.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:29.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:29.496 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 02:45:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:29.504 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:29.504 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:45:29.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:29.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:29.964 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 02:45:30.432 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 02:45:30.899 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 02:45:31.367 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 02:45:31.835 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 02:45:32.302 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 02:45:32.770 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 02:45:33.238 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 02:45:33.706 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 02:45:34.173 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 02:45:34.641 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 02:45:34.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:34.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:34.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:34.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:34.757 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:34.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:34.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:34.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:34.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:34.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:34.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:34.770 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:34.770 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:34.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:34.813 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:34.813 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:45:34.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:34.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:35.111 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 02:45:35.579 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 02:45:36.046 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 02:45:36.514 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 02:45:36.981 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 02:45:37.449 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 02:45:37.916 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 02:45:38.384 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 02:45:38.927 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 02:45:39.395 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 02:45:39.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:39.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:39.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:39.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:39.668 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:39.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:39.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:39.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:39.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:39.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:39.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:39.677 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:39.677 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:39.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:39.721 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:39.721 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:45:39.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:39.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:39.863 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 02:45:40.332 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 02:45:40.799 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 02:45:41.266 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 02:45:41.734 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 02:45:42.202 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 02:45:42.669 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 02:45:43.137 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 02:45:43.605 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 02:45:44.073 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 02:45:44.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:44.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:44.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:44.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:44.436 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:44.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:44.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:44.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:44.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:44.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:44.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:44.445 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:44.445 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:44.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:44.492 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:44.492 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:45:44.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:44.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:44.799 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 02:45:45.267 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 02:45:45.735 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 02:45:46.202 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 02:45:46.670 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 02:45:47.138 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 02:45:47.605 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 02:45:48.076 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 02:45:48.544 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 02:45:49.012 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 02:45:49.480 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 02:45:49.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:49.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:49.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:49.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:49.865 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:49.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:49.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:49.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:49.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:49.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:49.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:49.883 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:49.883 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:49.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:49.934 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:49.934 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:45:49.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:49.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:49.949 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 02:45:50.420 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 02:45:50.888 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 02:45:51.357 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 02:45:51.826 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 02:45:52.295 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 02:45:52.763 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 02:45:53.232 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 02:45:53.700 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 02:45:54.168 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 02:45:54.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:54.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:54.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:54.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:54.564 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:54.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:54.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:54.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:54.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:54.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:54.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:54.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:54.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:54.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:54.616 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:54.617 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:45:54.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:54.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:54.637 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 02:45:55.104 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 02:45:55.572 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 02:45:56.040 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 02:45:56.508 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 02:45:56.976 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 02:45:57.443 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 02:45:57.911 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 02:45:58.378 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 02:45:58.846 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 02:45:59.315 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 02:45:59.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:59.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:59.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:59.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:59.428 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:45:59.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:45:59.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:45:59.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:45:59.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:59.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:45:59.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:45:59.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:45:59.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:45:59.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:45:59.484 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:45:59.484 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:45:59.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:59.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:45:59.783 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-02 02:46:00.251 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-02 02:46:00.718 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-02 02:46:01.186 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-02 02:46:01.653 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-02 02:46:02.121 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-02 02:46:02.589 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-02 02:46:03.057 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-02 02:46:03.524 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-02 02:46:03.992 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-02 02:46:04.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:04.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:04.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:04.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:04.126 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:04.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:04.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:04.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:04.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:04.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:04.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:04.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:04.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:04.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:04.180 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:04.180 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:04.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:04.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:04.460 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-02 02:46:04.928 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-02 02:46:05.396 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-02 02:46:05.865 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-02 02:46:06.334 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-02 02:46:06.803 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-02 02:46:07.271 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-02 02:46:07.739 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-02 02:46:08.208 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-02 02:46:08.676 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-02 02:46:08.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:08.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:08.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:08.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:08.822 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:08.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:08.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:08.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:08.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:08.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:08.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:08.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:08.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:08.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:08.881 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:08.881 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:08.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:08.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:09.145 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-02 02:46:09.615 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-02 02:46:10.083 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-02 02:46:10.551 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-02 02:46:11.019 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-02 02:46:11.487 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-02 02:46:11.956 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-02 02:46:12.424 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-02 02:46:12.893 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-02 02:46:13.362 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-02 02:46:13.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:13.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:13.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:13.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:13.528 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:13.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:13.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:13.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:13.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:13.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:13.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:13.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:13.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:13.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:46:13.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:46:13.533 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:46:18.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:46:18.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:46:18.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:18.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:18.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:18.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:18.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:18.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:46:18.542 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:18.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:46:18.542 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:46:18.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:46:18.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:46:18.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:46:18.544 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:46:18.544 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:46:18.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:18.545 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:46:18.545 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:46:18.545 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:46:18.545 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:18.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:18.546 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:46:18.546 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:46:18.546 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:46:18.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:46:18.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:46:18.548 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:46:18.548 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:46:18.548 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:18.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:18.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:18.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:18.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:18.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:18.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:46:18.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:46:18.549 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:46:23.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:46:23.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:46:23.551 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:23.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:23.552 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:23.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:23.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:23.555 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:46:23.555 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:23.555 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:46:23.555 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:46:23.556 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:46:23.556 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:46:23.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:46:23.557 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:46:23.557 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:46:23.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:46:23.558 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:46:23.558 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:46:23.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:23.559 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:46:23.560 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:46:23.560 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:46:23.560 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:23.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:23.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:23.565 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:46:24.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:46:24.073 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:46:24.073 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:46:24.074 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:46:24.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:24.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:24.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:24.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:24.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:24.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:24.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:24.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:24.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:24.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:24.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:24.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:24.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:24.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:24.501 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:46:24.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:24.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:24.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:24.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:24.969 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:46:25.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:25.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:25.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:25.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:25.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:25.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:25.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:25.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:25.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:25.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:25.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:25.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:25.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:25.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:25.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:25.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:25.437 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:46:25.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:25.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:25.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:25.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:25.907 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:46:26.380 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:46:26.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:26.858 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:46:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:26.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:26.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:26.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:26.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:26.941 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=668 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:26.941 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=668 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:26.941 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=668 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:26.941 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=669 tn=0 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:26.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:26.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:26.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:26.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:26.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:26.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:26.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:26.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:26.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:26.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:26.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:26.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:26.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:27.408 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:46:27.881 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:46:27.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:27.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:27.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:27.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:28.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:28.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:28.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:28.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:28.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:28.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:28.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:28.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:28.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:28.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:28.324 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:28.324 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:28.350 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:46:28.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:28.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:28.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:28.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:28.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:28.818 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:46:28.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:28.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:28.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:28.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:29.286 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:46:29.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:29.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:29.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:29.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:29.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:29.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:29.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:29.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:29.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:29.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:29.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:29.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:29.754 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:46:29.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:29.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:29.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:29.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:29.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:30.223 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:46:30.692 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:46:30.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:30.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:30.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:30.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:30.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:30.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:30.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:30.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:30.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:30.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:30.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:30.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:30.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:30.872 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:30.873 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:46:30.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:30.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:31.160 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:46:31.627 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:46:31.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:31.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:31.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:31.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:31.831 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:31.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:31.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:31.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:31.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:31.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:31.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:31.840 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:31.840 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:31.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:31.884 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:31.884 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:46:31.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:31.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:32.097 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:46:32.565 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:46:32.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:32.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:32.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:32.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:32.846 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:32.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:32.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:32.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:32.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:32.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:32.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:32.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:32.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:32.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:32.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:32.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:32.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:32.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:32.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:33.033 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:46:33.502 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:46:33.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:33.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:33.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:33.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:33.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:33.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:33.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:33.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:33.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:33.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:33.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:33.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:33.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:33.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:33.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:33.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:33.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:33.971 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:46:34.439 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:46:34.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:34.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:34.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:34.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:34.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:34.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:34.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:34.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:34.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:34.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:34.885 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:34.885 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:34.908 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:46:34.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:34.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:34.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:34.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:34.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:34.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:35.380 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:46:35.848 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:46:36.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:36.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:36.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:36.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:36.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:36.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:36.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:36.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:36.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:36.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:36.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:36.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:36.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:36.314 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:36.314 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:46:36.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:36.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:36.318 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:46:36.787 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:46:37.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:37.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:37.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:37.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:37.212 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:37.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:37.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:37.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:37.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:37.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:37.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:37.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:37.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:37.256 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:46:37.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:37.264 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:37.264 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:46:37.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:37.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:37.725 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:46:38.195 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:46:38.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:38.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:38.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:38.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:38.231 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:38.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:38.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:38.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:38.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:38.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:38.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:38.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:38.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:38.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:38.303 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:38.303 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:38.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:38.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:38.665 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:46:39.136 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:46:39.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:39.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:39.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:39.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:39.289 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:39.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:39.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:39.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:39.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:39.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:39.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:39.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:39.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:39.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:39.351 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:39.351 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:39.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:39.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:39.605 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:46:40.075 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:46:40.544 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:46:40.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:40.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:40.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:40.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:40.716 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:40.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:40.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:40.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:40.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:40.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:40.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:40.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:40.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:40.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:40.778 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:40.778 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:40.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:40.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:41.014 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:46:41.484 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:46:41.954 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:46:42.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:42.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:42.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:42.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:42.142 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:42.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:42.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:42.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:42.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:42.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:42.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:42.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:42.152 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:42.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:42.199 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:42.199 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:42.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:42.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:42.424 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:46:42.944 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:46:43.413 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:46:43.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:43.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:43.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:43.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:43.625 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:43.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:43.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:43.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:43.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:43.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:43.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:43.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:43.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:43.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:43.701 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:43.701 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:43.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:43.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:43.882 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:46:44.351 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:46:44.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:44.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:44.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:44.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:44.738 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:44.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:44.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:44.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:44.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:44.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:44.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:44.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:44.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:44.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:44.819 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:44.819 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:44.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:44.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:44.820 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:46:45.288 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:46:45.760 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:46:46.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:46.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:46.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:46.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:46.167 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:46.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:46.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:46.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:46.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:46.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:46.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:46.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:46.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:46.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:46.229 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:46:46.229 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:46.229 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:46.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:46.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:46.698 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:46:47.168 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:46:47.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:47.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:47.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:47.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:47.598 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:47.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:47.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:47.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:47.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:47.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:47.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:47.615 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:47.615 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:47.638 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:46:47.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:47.669 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:46:47.670 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:46:47.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:47.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:48.106 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:46:48.576 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:46:49.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:49.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:49.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:49.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:49.027 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:46:49.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:49.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:49.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:49.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:49.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:49.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:49.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:49.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:49.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:46:49.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:46:49.048 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5509 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:49.050 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5510 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:54.047 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:46:54.047 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:46:54.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:54.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:54.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:54.051 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:54.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:46:54.058 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:46:54.058 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:54.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:46:54.059 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:46:54.061 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:46:54.061 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:46:54.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:46:54.061 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:54.061 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:46:54.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:46:54.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:46:54.061 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:46:54.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:46:54.063 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:46:54.063 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:46:54.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:46:54.064 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:46:54.064 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:46:54.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:46:54.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:46:54.066 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:46:54.066 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:46:54.071 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:46:54.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:46:54.589 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:46:54.590 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:46:54.592 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:46:54.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:54.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:54.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:54.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:54.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:54.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:54.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:54.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:54.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:46:54.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:54.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:54.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:54.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:55.009 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:46:55.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:55.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:55.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:55.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:55.479 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:46:55.948 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:46:56.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:56.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:56.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:56.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:56.417 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:46:56.887 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:46:57.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:57.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:57.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:57.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:57.357 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:46:57.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:57.827 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:46:58.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:58.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:58.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:58.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:58.298 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:46:58.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:46:58.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:58.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:46:58.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:46:58.371 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=936 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:58.372 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=936 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:58.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:46:58.372 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=936 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:58.372 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:58.372 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=936 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:46:58.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:58.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:58.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:58.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:46:58.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:46:58.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:46:58.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:46:58.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:46:58.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:58.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:46:58.769 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:46:59.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:46:59.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:46:59.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:46:59.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:46:59.240 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:46:59.709 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:47:00.177 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:47:00.646 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:47:01.117 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:47:01.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:01.586 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:47:02.055 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:47:02.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:02.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:02.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:02.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:02.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:02.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:02.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:02.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:02.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:02.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:02.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:02.207 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:02.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:02.252 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:02.252 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:47:02.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:02.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:02.523 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:47:02.991 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:47:03.460 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:47:03.930 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:47:04.400 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:47:04.870 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:47:05.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:05.339 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:47:05.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:05.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:05.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:05.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:05.790 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:05.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:05.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:05.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:05.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:05.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:05.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:05.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:05.809 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:05.809 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:47:05.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:05.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:05.810 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:47:06.283 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:47:06.754 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:47:07.225 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:47:07.695 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:47:08.164 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:47:08.632 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:47:08.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:09.100 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:47:09.569 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:47:09.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:09.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:09.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:09.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:09.623 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:09.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:09.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:09.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:09.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:09.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:09.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:09.639 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:09.639 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:09.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:09.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:09.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:09.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:09.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:10.040 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:47:10.511 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:47:10.982 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:47:11.451 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:47:11.920 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:47:12.389 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:47:12.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:12.859 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:47:13.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:13.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:13.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:13.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:13.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:13.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:13.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:13.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:13.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:13.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:13.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:13.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:13.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:13.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:13.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:13.328 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:47:13.798 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:47:14.268 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:47:14.739 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:47:15.207 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:47:15.677 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:47:16.147 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:47:16.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:16.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:16.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:16.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:16.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:16.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:16.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:16.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:16.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:16.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:16.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:16.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:16.591 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:16.615 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:47:16.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:16.636 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:16.636 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:47:16.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:16.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:17.085 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:47:17.555 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:47:18.024 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:47:18.492 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:47:18.961 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:47:19.430 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:47:19.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:19.898 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:47:20.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:20.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:20.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:20.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:20.288 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:20.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:20.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:20.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:20.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:20.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:20.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:20.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:20.315 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:20.315 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:47:20.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:20.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:20.368 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:47:20.836 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:47:21.306 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:47:21.774 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:47:22.243 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:47:22.714 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:47:23.185 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:47:23.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:23.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:23.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:23.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:23.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:23.578 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:23.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:23.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:23.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:23.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:23.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:47:23.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:47:23.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:47:23.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:47:23.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:47:23.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:47:23.594 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6413 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6413 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6413 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6413 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6413 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6413 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.595 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:23.596 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:47:28.590 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:47:28.590 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:47:28.591 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:47:28.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:47:28.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:47:28.592 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:47:28.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:47:28.594 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:47:28.594 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:47:28.594 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:47:28.594 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:47:28.595 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:47:28.595 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:47:28.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:47:28.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:47:28.596 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:47:28.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:47:28.597 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:47:28.597 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:47:28.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.598 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:47:28.598 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:47:28.598 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:47:28.599 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:47:28.603 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:47:29.077 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:47:29.110 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:47:29.110 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:47:29.111 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:47:29.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:29.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:29.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:29.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:29.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:29.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:29.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:29.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:29.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:29.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:29.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:29.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:29.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:29.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:29.545 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:47:29.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:29.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:29.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:29.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:30.015 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:47:30.485 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:47:30.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:30.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:30.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:30.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:30.953 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:47:31.423 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:47:31.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:31.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:31.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:31.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:31.894 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:47:32.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:32.362 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:47:32.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:32.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:32.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:32.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:32.831 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:47:32.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:32.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:32.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:32.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:32.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:32.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:32.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:32.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:32.901 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:32.901 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:32.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:32.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:32.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:32.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:32.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:33.299 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:47:33.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:47:33.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:47:33.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:47:33.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:47:33.770 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:47:34.239 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:47:34.708 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:47:35.177 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:47:35.646 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:47:35.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:36.117 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:47:36.586 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:47:36.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:36.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:36.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:36.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:36.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:36.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:36.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:36.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:36.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:36.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:36.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:36.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:36.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:36.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:36.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:37.054 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:47:37.522 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:47:37.991 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:47:38.461 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:47:38.930 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:47:39.399 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:47:39.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:39.868 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:47:40.338 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:47:40.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:40.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:40.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:40.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:40.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:40.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:40.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:40.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:40.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:40.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:40.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:40.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:40.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:40.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:40.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:40.806 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:47:41.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:41.278 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:47:41.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:41.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:41.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:41.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:41.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:41.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:41.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:41.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:41.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:41.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:41.538 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:41.538 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:41.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:41.587 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:41.587 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:47:41.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:41.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:41.748 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:47:42.217 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:47:42.686 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:47:43.155 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:47:43.624 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:47:44.094 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:47:44.564 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:47:44.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:45.033 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:47:45.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:45.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:45.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:45.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:45.109 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:45.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:45.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:45.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:45.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:45.110 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:45.110 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:45.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:45.126 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:45.126 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:47:45.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:45.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:45.505 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:47:45.973 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:47:46.442 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:47:46.911 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:47:47.378 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:47:47.848 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:47:48.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:48.316 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:47:48.787 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:47:48.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:48.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:48.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:48.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:48.933 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:48.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:48.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:48.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:48.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:48.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:48.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:48.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:48.966 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:48.966 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:47:48.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:48.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:49.256 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:47:49.725 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:47:50.193 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:47:50.664 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:47:51.135 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:47:51.604 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:47:51.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:52.074 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:47:52.543 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:47:52.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:52.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:52.760 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:52.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:52.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:52.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:52.774 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:47:52.774 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:47:52.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:52.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:53.011 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:47:53.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:53.479 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:47:53.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:53.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:53.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:53.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:53.716 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:47:53.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:53.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:53.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:53.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:53.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:53.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:53.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:53.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:53.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:53.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:53.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:53.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:53.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:53.947 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:47:54.414 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:47:54.882 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:47:55.349 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:47:55.817 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:47:56.284 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:47:56.752 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:47:56.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:57.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:47:57.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:57.187 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:47:57.187 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:47:57.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:47:57.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:47:57.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:47:57.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:57.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:47:57.219 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:47:57.687 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:47:58.155 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:47:58.622 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:47:59.091 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:47:59.558 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:48:00.026 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:48:00.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:00.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:00.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:00.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:00.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:00.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:48:00.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:00.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:00.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:00.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:00.494 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:48:00.961 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:48:01.485 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:48:01.952 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:48:02.420 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:48:02.887 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:48:03.355 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:48:03.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:03.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:03.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:03.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:03.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:03.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:48:03.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:03.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:03.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:03.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:03.823 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:48:04.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:04.291 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:48:04.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:04.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:04.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:04.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:04.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:04.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:04.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:04.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:04.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:04.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:04.732 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:04.732 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:04.759 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:48:04.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:48:04.779 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:48:04.779 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:48:04.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:04.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:05.226 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:48:05.694 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:48:06.162 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:48:06.629 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:48:07.118 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:48:07.586 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:48:07.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:08.054 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:48:08.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:08.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:08.440 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:08.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:08.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:08.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:48:08.468 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:48:08.468 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:48:08.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:08.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:08.521 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:48:08.989 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:48:09.457 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:48:09.925 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:48:10.393 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:48:10.860 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:48:11.328 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:48:11.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:11.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:11.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:11.717 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:11.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:11.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:11.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:48:11.745 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:48:11.745 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:48:11.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:11.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:11.796 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:48:12.263 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:48:12.731 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:48:13.199 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:48:13.666 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:48:14.137 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:48:14.607 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:48:14.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:14.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:14.994 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:14.994 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:14.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:15.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:48:15.022 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:48:15.022 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:48:15.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:15.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:15.076 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:48:15.545 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:48:15.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:15.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:15.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:15.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:15.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:15.932 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:48:15.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:15.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:15.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:15.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:15.937 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:15.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:15.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:15.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:15.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:48:15.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:48:15.937 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:48:20.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:48:20.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:48:20.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:20.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:20.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:20.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:20.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:20.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:48:20.944 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:20.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:48:20.944 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:48:20.945 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:48:20.945 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:48:20.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:48:20.946 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:48:20.946 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:48:20.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:20.947 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:48:20.947 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:48:20.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:48:20.947 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:20.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:20.947 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:48:20.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:48:20.948 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:48:20.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:48:20.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:48:20.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:48:20.950 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:20.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:20.954 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:48:21.422 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:48:21.465 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:48:21.466 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:48:21.466 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:48:21.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:21.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:21.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:21.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:21.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:21.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:21.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:21.468 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:21.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:21.889 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:48:21.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:21.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:21.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:21.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:22.357 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:48:22.825 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:48:22.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:22.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:22.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:22.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:23.293 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:48:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:48:23.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:23.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:23.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:23.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:24.228 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:48:24.697 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:48:24.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:24.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:24.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:24.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:25.165 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:48:25.633 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:48:25.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:25.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:25.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:25.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:26.101 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:48:26.569 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:48:27.037 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:48:27.504 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:48:27.972 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:48:28.440 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:48:28.908 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:48:29.375 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:48:29.844 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:48:30.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:30.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:30.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:30.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:48:30.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:48:30.235 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:48:35.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:48:35.236 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:48:35.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:35.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:35.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:35.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:35.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:35.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:48:35.240 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:48:35.241 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:48:35.241 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:48:35.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:48:35.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:48:35.242 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:48:35.242 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:48:35.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:48:35.243 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:48:35.243 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:48:35.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:48:35.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:48:35.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:48:35.245 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:48:35.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:35.250 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:48:35.717 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:48:35.758 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:48:35.759 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:35.760 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:35.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:35.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:35.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:36.185 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:48:36.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:36.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:36.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:36.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:36.653 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:48:37.121 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:48:37.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:37.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:37.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:37.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:37.588 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:48:38.057 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:48:38.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:38.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:38.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:38.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:38.525 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:48:38.993 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:48:39.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:39.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:39.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:39.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:39.461 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:48:39.929 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:48:40.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:40.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:40.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:40.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:40.397 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:48:40.864 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:48:41.333 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:48:41.801 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:48:42.269 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:48:42.737 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:48:43.204 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:48:43.672 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:48:44.140 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:48:44.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:44.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:44.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:44.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:44.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:44.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:44.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:44.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:44.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:44.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:44.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:48:44.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:48:44.480 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:48:49.481 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:48:49.481 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:48:49.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:49.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:49.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:49.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:49.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:48:49.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:48:49.485 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:49.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:48:49.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:48:49.486 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:48:49.486 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:48:49.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:48:49.487 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:48:49.487 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:48:49.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:49.488 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:48:49.488 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:48:49.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:48:49.488 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:48:49.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:48:49.488 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:48:49.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:48:49.489 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:48:49.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.490 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:48:49.490 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:48:49.490 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:48:49.495 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:48:49.963 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:48:50.003 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:48:50.003 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:48:50.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:48:50.004 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:48:50.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:48:50.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:48:50.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:48:50.430 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:48:50.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:50.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:50.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:50.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:50.897 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:48:51.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:48:51.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:48:51.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:48:51.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:48:51.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:48:51.365 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:48:51.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:51.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:51.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:51.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:51.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:48:52.301 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:48:52.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:52.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:52.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:52.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:52.769 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:48:53.236 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:48:53.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:53.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:53.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:53.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:53.704 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:48:54.172 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:48:54.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:48:54.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:48:54.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:48:54.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:48:54.640 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:48:55.110 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:48:55.579 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:48:56.047 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:48:56.515 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:48:56.983 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:48:57.452 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:48:57.922 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:48:58.390 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:48:58.859 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:48:59.327 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:48:59.796 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:49:00.263 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:49:00.731 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:49:01.199 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:49:01.668 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:49:02.136 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:49:02.604 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:49:02.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:02.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:02.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:02.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:02.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:02.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:02.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:02.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:02.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:02.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:02.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:02.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:02.835 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:49:02.835 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2908 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:02.835 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2908 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:02.835 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2908 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:02.835 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2908 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:02.835 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2908 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:02.835 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2908 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:07.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:07.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:07.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:07.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:07.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:07.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:07.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:07.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:07.840 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:07.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:07.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:07.841 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:07.841 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:49:07.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:07.842 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:07.842 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:49:07.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:07.843 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:49:07.843 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:49:07.843 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:07.843 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:07.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:07.844 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:49:07.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:07.844 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:49:07.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.845 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:49:07.845 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:49:07.846 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:49:07.846 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:07.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:07.850 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:49:08.318 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:49:08.360 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:08.361 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:49:08.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:08.362 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:49:08.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:08.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:08.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:08.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:08.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:08.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:08.364 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:08.364 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:08.787 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:49:08.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:08.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:08.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:08.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:09.257 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:49:09.407 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:09.725 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:49:09.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:09.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:09.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:09.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:09.921 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:10.193 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:49:10.438 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:10.661 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:49:10.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:10.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:10.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:10.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:11.129 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:49:11.598 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:49:11.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:11.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:11.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:11.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:12.067 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:49:12.450 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:12.536 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:49:12.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:12.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:12.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:12.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:12.967 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:13.005 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:49:13.473 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:49:13.479 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:13.941 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:49:13.996 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:14.412 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:49:14.880 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:49:15.347 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:49:15.816 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:49:15.999 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:16.284 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:49:16.752 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:49:17.220 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:49:17.688 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:49:18.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:18.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:18.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:18.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:18.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:18.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:18.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:18.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:18.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:18.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:18.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:18.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:18.031 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:49:18.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2219 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:18.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2219 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:18.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2219 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:18.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2219 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:18.031 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2219 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:18.032 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2219 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:23.032 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:23.032 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:23.033 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:23.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:23.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:23.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:23.038 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:23.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:23.038 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:23.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:23.038 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:23.039 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:23.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:49:23.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:23.040 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:23.040 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:49:23.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:23.041 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:23.041 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:49:23.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:23.042 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:49:23.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:49:23.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:49:23.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:49:23.042 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:49:23.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:49:23.043 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:49:23.043 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:49:23.043 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:23.048 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:49:23.516 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:49:23.560 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:23.561 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:49:23.561 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:49:23.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:23.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:23.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:23.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:23.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:23.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:23.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:23.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:23.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:23.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:23.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:23.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:23.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:23.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:23.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:23.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:23.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:23.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:23.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:23.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:23.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:23.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:23.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:23.751 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:23.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:23.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:23.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:23.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:23.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:23.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:23.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:23.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:23.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:23.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:23.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:23.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:23.985 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:49:23.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:23.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:23.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:23.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:23.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:24.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:24.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:24.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:24.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.208 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.228 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.228 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.228 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.275 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.275 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.310 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.310 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:49:24.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.312 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:24.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.320 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.320 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.358 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.358 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:49:24.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.374 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:24.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:24.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.454 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:49:24.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:24.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.509 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.509 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.545 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.545 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:49:24.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.552 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:24.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.592 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.592 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:49:24.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.599 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:24.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.639 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.639 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:24.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.756 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:24.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.764 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.764 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.780 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.780 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:24.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:24.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.783 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:24.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:24.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:24.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:24.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:24.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:24.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:24.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:24.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:24.825 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:24.825 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:24.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:24.922 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:49:25.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.018 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:25.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:25.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:25.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:25.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:25.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:25.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:25.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:25.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:25.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:25.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:25.056 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:25.056 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:25.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.277 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:25.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:25.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:25.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:25.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:25.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:25.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:25.292 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:25.292 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:25.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.295 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:25.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:25.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:25.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:25.303 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:25.303 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:25.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:25.339 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:25.339 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:25.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.391 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:49:25.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.558 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:25.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:25.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:25.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:25.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:25.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:25.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:25.624 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:25.624 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:25.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:25.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.799 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:25.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:25.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:25.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:25.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:25.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:25.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:25.807 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:25.862 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:49:25.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:25.868 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:49:25.868 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:49:25.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:25.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:26.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:26.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:26.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:26.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:26.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:26.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:26.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:26.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:26.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:26.059 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:49:26.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:26.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:26.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:26.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:26.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:26.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:26.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:26.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:26.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:26.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:26.071 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:49:26.071 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=658 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.071 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=658 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.071 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=658 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.071 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=658 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.071 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=658 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=658 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:26.072 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=659 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:31.067 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:31.067 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:31.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:31.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:31.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:31.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:31.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:31.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:31.071 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:31.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:31.072 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:49:31.072 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:49:31.072 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:49:31.072 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:31.072 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:31.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:31.072 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:49:31.072 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:31.072 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:31.073 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:31.073 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:49:31.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:31.074 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:31.074 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:49:31.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:49:31.076 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:49:31.076 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:49:31.076 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:31.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:31.081 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:49:31.549 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:49:31.589 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:31.590 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:49:31.590 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:49:31.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:31.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:31.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:31.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:49:31.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:31.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:31.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:31.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:49:31.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:49:31.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 02:49:31.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:49:31.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:49:31.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:31.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:49:31.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:32.019 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:49:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:32.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:32.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:32.497 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:49:32.974 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:49:33.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:33.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:33.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:33.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:33.444 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:49:33.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:49:33.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:49:33.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:33.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:33.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:33.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:33.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:33.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:33.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:33.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:33.692 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:33.692 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:33.692 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:49:33.692 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=566 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:33.692 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=566 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:33.693 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=566 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:38.693 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:38.693 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:38.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:38.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:38.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:38.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:38.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:38.704 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:38.704 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:38.704 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:38.704 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:49:38.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:38.705 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:38.705 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:49:38.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:38.706 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:38.706 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:49:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:38.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:49:38.708 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:49:38.708 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:49:38.708 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:38.708 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:38.708 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:38.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:43.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:43.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:43.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:43.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:43.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:43.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:43.714 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:43.714 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:43.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:49:43.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:43.714 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:43.715 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:43.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:49:43.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:43.716 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:43.716 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:49:43.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:49:43.718 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:49:43.718 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:49:43.718 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:43.722 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:49:44.191 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:49:44.231 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:44.231 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:49:44.231 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:49:44.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:44.658 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:49:44.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:44.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:44.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:44.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:45.126 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:49:45.593 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:49:45.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:45.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:45.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:45.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:46.062 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:49:46.530 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:49:46.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:46.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:46.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:46.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:46.998 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:49:47.466 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:49:47.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:47.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:47.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:47.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:47.933 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:49:48.401 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:49:48.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:48.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:48.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:48.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:48.868 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:49:49.336 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:49:49.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:49.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:49.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:49.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:49.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:49.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:49.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:49.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:49.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:49.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:49.725 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:49.725 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:49:54.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:49:54.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:49:54.726 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:54.726 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:54.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:54.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:54.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:49:54.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:54.730 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:54.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:49:54.730 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:54.731 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:49:54.731 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:49:54.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:54.732 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:49:54.732 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:49:54.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:54.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:49:54.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:49:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.734 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:49:54.734 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:49:54.734 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:49:54.734 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:49:54.739 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:49:55.207 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:49:55.246 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:49:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:49:55.247 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:49:55.247 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:49:55.674 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:49:55.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:55.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:55.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:55.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:56.142 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:49:56.611 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:49:56.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:56.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:56.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:56.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:57.079 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:49:57.546 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:49:57.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:57.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:57.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:57.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:58.013 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:49:58.481 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:49:58.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:58.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:58.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:58.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:58.948 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:49:59.416 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:49:59.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:49:59.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:49:59.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:49:59.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:49:59.883 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:50:00.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:00.250 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:00.250 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:00.250 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:50:05.251 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:05.251 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:05.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:05.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:05.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:05.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:05.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:05.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:05.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:05.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:05.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:05.256 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:05.256 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:50:05.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:05.257 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:05.257 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:50:05.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:05.258 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:50:05.258 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:50:05.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:05.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:05.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:05.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:50:05.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:05.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:50:05.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:50:05.261 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:50:05.261 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:05.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:05.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:05.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:05.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:05.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:05.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:05.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:05.262 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:50:10.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:10.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:10.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:10.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:10.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:10.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:10.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:10.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:10.267 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:10.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:10.267 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:10.268 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:10.268 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:50:10.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:10.269 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:10.269 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:50:10.269 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:10.270 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:10.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:10.270 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:50:10.270 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:10.270 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:50:10.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:50:10.271 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:50:10.271 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:50:10.271 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:10.276 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:50:10.744 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:50:10.786 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:10.786 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:10.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:10.787 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:50:10.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:10.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:10.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:50:11.212 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:50:11.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:11.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:11.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:11.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:11.679 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:50:11.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:11.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:50:11.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:50:11.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:50:11.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:50:12.147 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:50:12.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:12.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:12.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:12.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:12.614 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:50:13.082 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:50:13.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:13.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:13.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:13.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:13.550 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:50:14.018 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:50:14.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:14.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:14.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:14.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:14.485 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:50:14.953 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:50:15.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:15.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:15.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:15.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:15.421 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:50:15.889 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:50:16.356 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:50:16.824 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:50:17.292 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:50:17.760 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:50:18.227 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:50:18.695 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:50:19.163 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:50:19.631 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:50:20.098 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:50:20.566 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:50:21.034 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:50:21.501 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:50:21.969 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:50:22.437 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:50:22.905 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:50:23.372 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:50:23.840 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:50:24.328 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:50:24.796 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:50:25.263 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:50:25.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:25.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:25.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:25.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:25.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:25.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:25.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:25.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:25.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:25.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:25.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:25.579 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:25.579 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:25.579 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3335 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:30.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:30.579 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:30.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:30.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:30.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:30.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:30.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:30.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:30.584 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:30.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:30.584 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:30.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:30.585 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:50:30.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:30.586 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:30.586 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:50:30.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:30.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:50:30.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:50:30.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:30.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:30.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:30.587 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:50:30.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:30.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:50:30.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.589 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:50:30.589 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:50:30.589 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:50:30.590 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:30.594 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:50:31.062 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:50:31.104 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:31.104 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:31.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:31.105 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:50:31.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:31.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:31.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:50:31.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:31.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:50:31.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:50:31.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:50:31.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:50:31.151 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:31.152 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:31.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:31.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:50:31.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:50:31.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:31.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:31.530 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:50:31.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:31.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:31.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:31.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:31.998 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:50:32.466 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:50:32.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:32.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:32.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:32.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:32.933 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:50:33.401 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:50:33.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:33.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:33.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:33.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:33.869 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:50:34.337 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:50:34.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:34.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:34.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:34.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:34.805 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:50:35.272 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:50:35.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:35.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:35.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:35.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:35.741 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:50:36.210 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:50:36.678 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:50:37.147 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:50:37.615 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:50:38.085 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:50:38.554 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:50:39.023 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:50:39.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:39.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:39.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:39.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:39.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:39.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:39.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:39.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:39.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:39.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:39.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:39.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:39.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:39.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:39.214 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:39.214 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1880 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:50:44.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:44.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:44.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:44.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:44.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:44.216 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:44.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:44.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:44.222 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:44.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:44.222 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:50:44.223 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:50:44.223 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:50:44.223 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:44.223 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:44.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:44.223 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:50:44.224 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:44.224 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:50:44.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:44.225 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:44.225 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:50:44.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:44.227 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:44.227 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:50:44.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:50:44.229 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:50:44.229 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:50:44.229 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:44.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:44.234 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:50:44.702 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:50:44.744 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:44.744 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:44.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:44.745 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:50:44.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:44.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:44.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:50:44.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:44.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:50:44.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:50:44.754 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:50:44.754 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:50:44.791 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:44.792 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:44.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:44.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:50:44.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:50:44.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:44.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:45.170 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:50:45.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:45.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:45.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:45.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:45.638 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:50:46.105 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:50:46.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:46.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:46.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:46.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:46.573 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:50:47.041 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:50:47.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:47.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:47.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:47.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:47.509 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:50:47.977 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:50:48.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:48.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:48.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:48.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:48.445 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:50:48.913 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:50:49.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:49.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:49.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:49.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:49.381 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:50:49.850 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:50:50.317 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:50:50.785 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:50:51.254 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:50:51.722 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:50:52.190 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:50:52.659 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:50:52.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:52.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:52.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:52.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:52.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:52.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:52.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:52.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:52.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:52.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:52.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:52.802 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:52.802 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:52.802 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:50:52.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:57.802 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:57.802 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:57.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:57.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:57.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:57.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:57.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:57.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:57.806 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:57.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:50:57.806 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:57.807 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:50:57.807 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:50:57.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:57.808 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:50:57.808 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:50:57.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:57.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:50:57.809 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:50:57.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.810 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:50:57.810 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:50:57.810 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:50:57.811 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:50:57.815 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:50:58.283 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:50:58.322 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:58.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:58.323 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:58.324 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:50:58.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:58.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:58.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:50:58.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:58.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:50:58.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:50:58.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:50:58.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:50:58.372 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:50:58.373 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:50:58.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:50:58.377 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:50:58.377 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:50:58.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:58.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:50:58.751 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:50:58.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:58.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:58.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:58.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:58.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:50:58.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:50:58.937 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:50:58.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:50:58.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:50:58.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:50:58.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:50:58.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:50:58.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:50:58.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:50:58.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:50:58.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:50:58.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:50:58.938 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:51:03.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:03.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:03.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:03.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:03.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:03.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:03.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:03.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:03.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:03.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:03.943 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:03.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:03.944 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:51:03.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:03.946 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:03.946 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:51:03.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:03.947 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:03.947 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:51:03.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:03.949 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:51:03.950 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:51:03.950 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:51:03.950 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:03.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:03.955 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:51:04.423 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:51:04.461 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:04.462 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:04.462 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:51:04.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:04.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:04.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:04.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:04.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:04.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:04.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:04.471 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:04.471 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:04.512 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:04.513 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:04.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:04.517 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:51:04.517 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:51:04.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:04.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:04.891 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:51:04.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:04.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:04.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:04.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:05.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:05.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:05.077 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:51:05.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:05.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:05.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:05.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:05.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:05.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:05.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:05.078 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:05.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:05.078 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:51:05.078 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:10.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:10.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:10.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:10.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:10.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:10.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:10.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:10.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:10.083 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:10.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:10.083 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:10.084 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:10.084 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:51:10.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:10.085 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:10.085 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:51:10.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:10.086 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:10.086 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:51:10.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:51:10.087 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:51:10.087 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:51:10.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.087 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:10.092 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:51:10.561 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:51:10.599 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:10.599 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:10.599 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:51:10.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:10.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:10.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:10.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:10.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:10.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:10.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:10.608 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:10.608 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:10.650 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:10.651 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:10.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:10.655 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:51:10.655 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:51:10.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:10.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:11.028 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:51:11.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:11.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:11.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:11.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:11.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:11.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:11.215 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:51:11.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:11.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:11.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:11.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:11.216 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:11.216 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:11.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:11.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:11.216 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:11.216 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:11.216 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:51:16.217 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:16.217 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:16.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:16.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:16.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:16.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:16.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:16.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:16.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:16.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:16.224 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:16.225 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:16.225 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:51:16.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:16.226 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:51:16.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:51:16.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:16.226 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:16.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:16.227 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:51:16.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:16.227 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:51:16.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:16.228 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:16.228 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:51:16.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:16.229 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:51:16.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:51:16.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:51:16.230 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:51:16.230 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:51:16.230 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:16.235 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:51:16.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:51:16.744 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:16.744 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:16.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:16.745 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:51:16.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:16.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:16.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:16.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:16.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:16.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:16.753 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:16.753 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:16.793 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:16.793 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:16.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:16.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:16.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:16.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:16.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:17.171 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:51:17.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:17.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:17.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:17.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:17.639 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:51:18.107 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:51:18.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:18.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:18.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:18.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:18.575 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:51:19.042 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:51:19.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:19.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:19.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:19.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:19.510 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:51:19.979 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:51:20.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:20.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:20.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:20.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:20.447 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:51:20.915 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:51:21.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:21.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:21.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:21.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:21.382 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:51:21.851 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:51:22.319 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:51:22.787 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:51:23.255 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:51:23.723 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:51:24.191 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:51:24.659 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:51:24.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:24.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:24.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:24.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:24.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:24.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:24.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:24.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:24.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:24.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:24.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:24.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:24.838 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:24.839 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:24.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:24.844 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:51:24.844 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:51:24.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:24.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:25.127 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:51:25.595 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:51:25.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:25.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:25.826 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:25.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:25.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:25.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:25.828 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:51:30.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:30.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:30.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:30.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:30.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:30.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:30.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:30.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:30.832 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:30.832 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:30.832 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:30.833 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:30.833 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:51:30.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:30.834 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:51:30.834 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:51:30.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:30.835 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:30.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:30.835 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:51:30.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:30.835 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:51:30.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:30.836 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:30.836 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:51:30.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:51:30.838 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:51:30.838 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:51:30.838 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:30.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:30.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:30.843 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:51:31.312 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:51:31.351 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:31.352 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:31.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:31.353 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:51:31.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:31.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:31.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:31.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:31.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:31.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:31.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:31.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:31.401 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:31.402 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:31.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:31.406 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:51:31.406 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:51:31.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:31.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:31.781 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:51:31.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:31.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:31.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:31.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:31.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:31.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:31.966 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:51:31.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:31.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:31.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:31.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:31.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:31.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:31.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:31.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:31.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:31.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:31.967 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:51:36.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:51:36.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:51:36.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:36.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:36.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:36.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:36.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:51:36.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:36.973 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:36.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:51:36.973 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:36.974 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:51:36.974 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:51:36.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:36.975 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:51:36.975 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:51:36.975 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:36.975 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:36.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:51:36.975 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:51:36.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:51:36.976 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:51:36.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:36.977 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:51:36.977 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:51:36.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:51:36.979 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:51:36.979 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:51:36.979 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:51:36.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:51:36.984 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:51:37.452 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:51:37.492 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:37.492 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:37.492 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:51:37.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:37.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:37.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:37.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:37.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:37.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:37.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:37.502 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:37.502 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:37.632 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:37.633 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:37.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:37.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:37.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:37.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:37.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:37.920 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:51:37.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:37.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:37.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:37.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:38.388 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:51:38.856 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:51:38.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:38.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:38.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:38.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:39.325 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:51:39.794 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:51:39.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:39.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:39.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:39.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:40.263 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:51:40.732 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:51:40.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:40.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:40.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:40.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:41.200 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:51:41.669 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:51:41.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:51:41.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:51:41.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:51:41.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:51:42.137 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:51:42.606 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:51:43.074 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:51:43.544 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:51:44.013 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:51:44.481 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:51:44.949 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:51:45.417 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:51:45.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:45.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:45.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:45.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:45.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:45.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:45.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:45.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:45.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:45.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:45.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:45.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:45.693 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:45.695 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:45.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:45.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:45.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:45.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:45.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:45.885 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:51:46.354 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:51:46.822 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:51:47.291 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:51:47.759 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:51:48.228 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:51:48.695 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:51:49.164 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:51:49.632 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:51:50.101 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:51:50.569 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:51:51.039 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:51:51.509 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:51:51.980 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:51:52.451 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:51:52.923 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:51:53.394 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:51:53.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:53.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:53.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:53.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:53.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:51:53.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:51:53.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:51:53.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:53.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:53.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:53.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:51:53.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:51:53.766 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:51:53.768 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:51:53.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:51:53.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:51:53.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:51:53.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:53.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:51:53.865 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:51:54.336 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:51:54.806 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:51:55.275 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:51:55.745 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:51:56.215 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:51:56.684 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:51:57.153 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:51:57.623 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:51:58.092 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:51:58.563 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:51:59.036 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:51:59.508 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:51:59.980 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:52:00.451 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:52:00.922 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:52:01.393 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:52:01.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:01.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:01.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:01.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:01.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:01.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:01.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:52:01.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:01.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:01.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:01.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:52:01.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:52:01.807 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:01.808 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:01.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:01.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:01.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:01.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:01.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:01.863 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:52:02.332 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:52:02.802 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:52:03.270 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:52:03.739 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:52:04.207 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:52:04.676 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:52:05.144 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:52:05.613 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:52:06.080 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:52:06.549 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:52:07.017 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:52:07.487 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:52:07.956 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:52:08.425 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:52:08.894 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:52:09.363 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:52:09.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:09.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:09.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:09.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:09.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:09.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:09.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:09.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:09.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:09.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:09.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:09.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:09.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:09.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:09.820 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:52:14.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:14.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:14.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:14.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:14.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:14.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:14.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:14.829 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:14.829 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:14.829 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:14.829 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:14.830 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:14.830 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:52:14.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:14.831 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:14.831 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:52:14.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:14.832 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:14.832 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:52:14.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.834 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:52:14.834 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:52:14.834 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:52:14.834 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:14.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:14.839 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:52:15.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:52:15.350 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:15.351 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:15.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:15.352 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:52:15.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:15.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:15.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:52:15.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:15.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:15.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:15.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:52:15.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:52:15.397 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:15.398 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:15.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:15.403 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:52:15.403 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:52:15.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:15.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:15.777 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:52:15.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:15.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:15.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:15.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:16.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:52:16.713 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:52:16.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:16.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:16.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:16.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:16.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:16.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:16.936 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:52:16.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:16.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:16.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:16.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:16.937 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:16.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:16.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:16.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:16.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:16.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:16.937 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:52:21.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:21.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:21.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:21.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:21.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:21.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:21.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:21.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:21.942 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:21.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:21.942 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:21.943 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:21.943 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:52:21.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:21.944 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:21.944 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:52:21.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:21.945 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:52:21.946 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:52:21.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:21.946 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:21.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:21.946 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:52:21.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:21.946 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:52:21.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:52:21.948 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:52:21.948 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:52:21.948 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:21.953 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:52:22.420 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:52:22.461 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:22.461 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:22.461 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:52:22.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:22.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:22.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:22.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:52:22.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:22.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:22.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:22.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:52:22.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:52:22.509 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:22.510 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:22.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:22.514 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:52:22.514 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:52:22.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:22.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:22.888 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:52:22.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:22.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:22.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:22.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:23.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:23.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:23.073 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:52:23.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:23.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:23.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:23.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:23.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:23.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:23.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:23.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:23.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:23.075 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:52:23.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:28.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:28.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:28.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:28.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:28.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:28.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:28.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:28.081 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:28.081 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:28.081 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:28.081 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:28.082 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:28.082 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:52:28.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:28.083 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:28.083 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:52:28.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:28.084 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:28.084 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:52:28.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.085 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:52:28.086 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:52:28.086 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:52:28.086 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:28.090 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:52:28.558 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:52:28.599 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:28.599 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:28.600 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:52:28.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:28.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:28.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:28.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:52:28.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:28.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:28.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:28.608 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:52:28.608 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:52:28.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:28.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:28.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:28.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:28.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:29.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:52:29.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:29.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:29.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:29.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:29.493 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:52:29.961 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:52:30.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:30.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:30.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:30.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:30.429 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:52:30.897 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:52:31.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:31.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:31.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:31.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:31.365 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:52:31.833 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:52:32.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:32.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:32.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:32.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:32.301 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:52:32.768 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:52:33.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:33.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:33.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:33.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:33.236 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:52:33.703 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:52:34.171 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:52:34.639 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:52:35.107 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:52:35.575 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:52:36.043 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:52:36.511 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:52:36.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:36.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:36.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:36.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:36.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:36.656 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:36.656 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:36.656 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:52:41.657 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:41.657 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:41.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:41.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:41.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:41.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:41.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:41.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:41.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:41.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:41.661 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:52:41.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:52:41.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:52:41.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:41.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:41.662 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:52:41.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:41.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:41.662 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:52:41.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:41.664 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:41.664 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:52:41.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:41.665 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:41.665 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:52:41.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:52:41.667 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:52:41.667 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:52:41.667 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:41.672 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:52:42.141 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:52:42.182 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:42.183 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:42.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:42.184 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:52:42.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:42.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:42.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:52:42.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:42.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:42.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:42.198 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:52:42.198 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:52:42.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:42.238 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:52:42.238 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:52:42.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:42.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:42.611 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:52:42.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:42.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:42.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:42.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:43.079 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:52:43.548 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:52:43.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:43.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:43.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:43.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:44.016 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:52:44.485 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:52:44.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:44.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:44.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:44.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:44.953 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:52:45.421 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:52:45.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:45.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:45.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:45.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:45.889 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:52:46.357 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:52:46.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:46.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:46.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:46.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:46.940 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:52:47.467 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:52:47.934 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:52:48.402 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:52:48.870 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:52:49.337 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:52:49.805 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:52:50.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:50.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:50.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:50.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:50.241 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:52:50.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:50.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:50.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:50.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:50.245 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:52:50.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:50.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:50.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:50.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:50.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:50.246 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:50.246 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1832 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:52:55.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:52:55.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:52:55.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:55.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:55.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:55.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:55.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:52:55.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:55.250 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:55.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:52:55.250 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:55.251 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:52:55.251 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:52:55.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:55.252 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:52:55.252 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:52:55.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:55.253 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:52:55.253 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:52:55.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:52:55.255 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:52:55.255 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:52:55.255 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:52:55.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:52:55.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:52:55.260 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:52:55.728 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:52:55.769 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:52:55.769 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:52:55.770 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:52:55.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:52:55.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:52:55.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:52:55.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:52:55.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:52:55.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:52:55.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:52:55.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:52:55.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:52:56.195 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:52:56.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:56.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:56.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:56.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:56.663 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:52:57.131 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:52:57.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:57.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:57.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:57.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:57.599 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:52:58.066 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:52:58.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:58.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:58.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:58.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:58.534 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:52:59.001 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:52:59.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:52:59.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:52:59.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:52:59.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:52:59.469 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:52:59.936 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:53:00.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:00.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:00.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:00.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:00.404 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:53:00.872 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:53:01.340 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:53:01.809 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:53:02.277 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:53:02.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:02.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:02.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:02.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:02.420 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:02.421 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:07.421 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:07.421 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:07.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:07.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:07.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:07.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:07.425 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:07.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:07.425 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:07.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:07.425 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:07.426 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:07.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:53:07.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:07.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:53:07.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:53:07.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:07.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:07.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:53:07.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:07.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:07.427 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:53:07.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:07.429 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:07.429 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:53:07.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:07.430 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:53:07.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:53:07.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:53:07.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:53:07.430 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:53:07.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:53:07.431 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:53:07.431 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:53:07.431 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:07.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:07.436 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:53:07.905 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:53:08.011 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:53:08.012 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:53:08.012 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:53:08.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:53:08.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:08.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:08.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:53:08.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:08.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:53:08.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:53:08.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:53:08.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:53:08.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:08.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:08.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:08.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:08.468 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:53:08.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:53:09.407 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:53:09.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:09.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:09.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:09.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:09.875 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:53:10.343 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:53:10.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:10.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:10.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:10.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:10.811 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:53:11.280 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:53:11.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:11.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:11.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:11.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:11.749 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:53:12.218 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:53:12.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:12.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:12.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:12.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:12.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:12.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:12.688 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:53:13.158 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:53:13.629 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:53:14.099 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:53:14.570 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:53:15.041 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:53:15.511 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:53:15.983 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:53:16.451 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:53:16.920 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:53:17.389 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:53:17.474 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:17.474 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:17.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:17.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:17.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:17.474 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:53:17.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:17.475 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:17.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:17.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:17.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:17.479 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:17.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:17.479 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:17.481 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:17.481 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:53:17.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:17.483 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:17.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:53:17.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:17.485 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:17.485 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:53:17.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:17.488 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:53:17.489 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:53:17.489 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:53:17.489 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:17.490 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:17.490 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:17.490 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:53:22.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:22.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:22.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:22.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:22.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:22.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:22.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:22.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:22.499 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:22.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:22.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:53:22.499 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:53:22.499 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:22.500 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:22.500 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:22.500 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:22.500 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:22.501 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:22.501 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:22.501 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:53:22.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.503 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:53:22.503 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:53:22.504 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:53:22.504 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:22.508 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:53:22.977 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:53:23.022 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:53:23.022 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:53:23.023 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:53:23.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:53:23.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:23.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:23.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:53:23.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:23.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:53:23.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:53:23.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:53:23.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:53:23.447 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:53:23.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:23.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:23.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:23.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:23.915 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:53:24.383 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:53:24.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:24.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:24.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:24.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:24.851 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:53:25.320 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:53:25.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:25.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:25.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:25.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:25.787 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:53:26.256 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:53:26.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:26.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:26.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:26.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:26.725 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:53:27.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:53:27.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:27.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:27.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:27.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:27.664 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:53:28.132 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:53:28.600 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:53:28.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:29.069 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:53:29.538 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:53:29.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:30.006 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:53:30.474 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:53:30.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:30.943 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:53:31.411 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:53:31.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:31.879 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:53:32.347 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:53:32.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:32.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:32.814 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:53:33.282 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:53:33.750 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:53:34.219 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:53:34.687 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:53:35.156 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:53:35.625 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:53:36.095 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:53:36.564 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:53:36.686 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:37.033 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:53:37.503 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:53:37.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:37.973 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:53:38.443 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:53:38.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:38.912 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:53:39.381 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:53:39.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:39.849 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:53:40.319 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:53:40.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:40.796 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:53:41.274 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:53:41.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:41.745 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:53:42.215 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:53:42.687 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:53:43.156 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:53:43.625 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:53:43.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:43.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:43.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:43.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:43.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:43.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:43.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:43.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:43.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:43.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:43.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:43.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:43.767 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:53:43.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4623 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:43.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4623 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:43.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4623 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:43.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4623 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:43.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4623 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:43.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4623 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:48.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:48.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:48.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:48.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:48.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:48.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:48.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:48.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:48.774 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:48.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:48.774 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:48.775 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:48.775 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:53:48.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:48.776 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:48.776 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:53:48.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:48.777 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:53:48.778 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:53:48.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:48.778 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:48.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:48.778 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:53:48.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:48.778 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:53:48.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:53:48.780 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:53:48.780 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:53:48.780 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:48.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:48.784 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:53:49.261 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:53:49.298 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:53:49.299 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:53:49.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:53:49.299 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:53:49.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:49.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:49.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:53:49.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:49.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:53:49.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:53:49.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:53:49.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:53:49.350 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:53:49.352 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:53:49.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:53:49.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:53:49.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:53:49.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:49.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:49.731 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:53:49.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:49.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:49.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:49.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:50.199 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:53:50.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:53:50.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:50.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:50.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:50.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:50.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:50.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:50.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:50.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:50.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:50.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:50.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:50.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:50.651 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:50.652 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:53:50.652 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=406 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:50.652 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:50.652 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:50.652 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:50.652 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:50.652 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:55.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:55.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:55.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:55.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:55.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:55.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:55.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:55.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:55.652 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:55.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:53:55.652 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:55.653 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:53:55.653 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:53:55.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:55.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:53:55.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:53:55.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:55.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:55.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:55.654 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:53:55.655 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:55.655 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:53:55.655 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:53:55.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:55.656 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:53:55.657 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:53:55.657 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:53:55.657 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:53:55.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:53:55.662 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:53:56.132 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:53:56.170 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:53:56.171 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:53:56.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:53:56.171 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:53:56.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:56.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:56.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:53:56.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:56.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:53:56.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:53:56.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:53:56.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:53:56.221 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:53:56.222 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:53:56.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:53:56.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:53:56.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:53:56.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:56.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:56.601 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:53:56.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:56.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:56.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:56.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:57.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:53:57.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 02:53:57.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:53:57.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:53:57.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:53:57.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:53:57.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:53:57.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:53:57.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:53:57.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:53:57.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:53:57.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:53:57.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:53:57.531 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:53:57.531 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:53:57.531 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:53:57.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.531 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.532 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:53:57.533 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:54:02.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:54:02.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:54:02.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:54:02.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:54:02.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:54:02.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:54:02.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:54:02.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:54:02.532 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:54:02.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:54:02.532 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:54:02.533 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:54:02.533 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:54:02.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:54:02.534 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:54:02.534 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:54:02.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:54:02.535 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:54:02.535 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:54:02.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.536 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:54:02.536 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:54:02.536 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:54:02.537 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:02.541 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:54:03.009 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:54:03.052 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:54:03.053 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:54:03.054 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:54:03.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:03.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:03.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:03.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:54:03.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:03.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:54:03.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:54:03.064 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:54:03.064 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:54:03.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:03.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:54:03.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:54:03.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:03.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:03.478 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:54:03.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:54:03.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:54:03.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:54:03.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:54:03.946 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:54:04.419 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:54:04.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:54:04.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:54:04.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:54:04.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:54:04.888 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:54:05.357 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:54:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:54:05.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:54:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:54:05.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:54:05.825 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:54:06.293 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:54:06.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:54:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:54:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:54:06.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:54:06.761 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:54:07.230 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:54:07.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:54:07.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:54:07.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:54:07.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:54:07.699 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:54:08.169 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:54:08.637 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:54:09.106 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:54:09.577 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:54:10.045 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:54:10.515 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:54:10.985 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:54:11.455 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:54:11.925 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:54:12.394 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:54:12.863 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:54:13.332 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:54:13.803 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:54:14.271 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:54:14.740 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:54:15.208 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:54:15.677 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:54:16.145 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:54:16.614 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:54:17.083 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:54:17.554 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:54:18.023 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:54:18.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:18.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:18.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:18.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:18.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:18.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:18.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:54:18.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:18.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:54:18.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:54:18.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:54:18.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:54:18.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:18.349 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:54:18.349 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 02:54:18.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:18.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:18.492 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:54:18.960 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:54:19.428 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:54:19.898 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:54:20.366 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:54:20.837 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:54:21.307 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:54:21.775 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:54:22.245 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:54:22.713 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:54:23.181 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:54:23.649 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:54:24.117 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:54:24.585 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:54:25.053 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:54:25.520 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:54:25.988 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:54:26.456 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:54:26.924 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:54:27.392 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:54:27.860 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:54:28.328 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:54:28.795 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:54:29.263 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:54:29.731 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:54:30.200 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:54:30.667 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:54:31.135 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:54:31.603 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:54:32.070 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:54:32.538 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:54:33.006 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:54:33.474 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:54:33.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:33.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:33.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:33.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:33.650 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:54:33.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:33.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:33.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:54:33.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:33.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:54:33.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:54:33.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:54:33.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:54:33.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:33.707 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:54:33.707 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 02:54:33.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:33.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:33.943 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:54:34.411 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:54:34.879 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:54:35.347 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:54:35.814 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:54:36.282 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:54:36.750 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 02:54:37.220 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 02:54:37.687 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 02:54:38.155 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 02:54:38.623 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 02:54:39.106 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 02:54:39.574 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 02:54:40.042 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 02:54:40.510 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 02:54:40.978 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 02:54:41.446 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 02:54:41.913 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 02:54:42.381 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 02:54:42.849 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 02:54:43.317 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 02:54:43.785 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 02:54:44.253 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 02:54:44.722 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 02:54:45.189 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 02:54:45.657 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 02:54:46.125 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 02:54:46.592 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 02:54:47.060 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 02:54:47.528 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 02:54:47.995 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 02:54:48.463 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 02:54:48.932 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 02:54:48.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:48.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:48.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:48.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:48.994 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:54:49.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:54:49.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:54:49.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:54:49.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:49.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:54:49.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:54:49.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:54:49.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:54:49.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:54:49.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:54:49.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:54:49.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:54:49.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:49.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:54:49.401 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 02:54:49.869 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 02:54:50.338 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 02:54:50.806 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 02:54:51.274 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 02:54:51.742 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 02:54:52.209 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 02:54:52.677 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 02:54:53.145 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 02:54:53.613 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 02:54:54.081 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 02:54:54.549 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 02:54:55.017 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 02:54:55.484 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 02:54:55.952 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 02:54:56.420 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 02:54:56.888 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 02:54:57.356 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 02:54:57.823 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 02:54:58.291 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 02:54:58.759 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 02:54:59.227 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 02:54:59.694 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 02:55:00.162 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 02:55:00.630 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 02:55:01.098 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 02:55:01.565 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 02:55:02.033 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 02:55:02.501 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 02:55:02.970 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 02:55:03.438 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 02:55:03.906 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 02:55:04.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:04.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:04.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:55:04.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:55:04.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:04.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:04.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:04.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:04.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:04.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:04.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:04.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:04.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:04.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:04.327 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:55:09.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:09.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:09.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:09.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:09.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:09.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:09.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:09.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:09.335 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:09.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:09.335 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:09.336 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:09.336 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:55:09.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:09.337 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:09.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:55:09.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:09.338 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:55:09.338 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:55:09.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:09.338 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:09.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:09.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:55:09.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:09.339 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:55:09.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:09.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:55:09.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:55:09.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:55:09.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:55:09.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:55:09.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:55:09.341 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:55:09.341 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:55:09.341 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:09.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:09.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:09.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:09.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:09.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:09.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:09.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:09.342 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:55:14.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:14.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:14.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:14.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:14.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:14.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:14.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:14.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:14.352 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:14.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:14.352 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:14.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:14.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:55:14.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:14.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:14.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:55:14.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:14.355 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:14.355 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:55:14.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:55:14.357 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:55:14.357 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:55:14.357 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:14.362 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:55:14.829 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:55:14.871 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:55:14.871 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:55:14.872 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:55:14.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:14.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:55:14.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:55:14.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:55:14.883 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:55:14.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:14.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:55:14.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:55:14.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:55:14.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:55:14.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:14.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:55:14.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:55:14.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:14.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:15.298 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:55:15.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:15.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:15.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:15.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:15.765 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:55:16.233 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:55:16.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:16.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:16.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:16.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:16.701 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:55:17.169 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:55:17.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:17.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:17.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:17.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:17.637 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:55:18.104 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:55:18.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:18.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:18.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:18.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:18.572 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:55:19.039 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:55:19.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:19.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:19.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:19.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:19.507 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:55:19.975 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:55:20.443 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:55:20.911 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:55:21.380 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:55:21.849 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:55:22.318 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:55:22.787 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:55:23.257 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:55:23.726 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:55:24.196 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:55:24.664 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:55:25.134 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:55:25.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:25.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:25.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:55:25.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:55:25.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:25.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:25.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:25.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:25.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:25.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:25.306 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:25.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:25.306 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:55:25.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:25.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:30.307 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:30.307 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:30.307 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:30.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:30.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:30.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:30.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:30.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:30.312 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:30.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:30.312 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:55:30.313 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:55:30.313 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:55:30.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:30.313 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:30.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:30.314 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:55:30.314 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:30.314 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:55:30.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:30.315 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:30.315 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:55:30.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:30.316 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:30.316 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:55:30.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:55:30.318 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:55:30.318 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:55:30.318 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:30.323 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:55:30.791 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:55:30.833 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:55:30.834 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:55:30.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:30.835 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:55:30.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:55:30.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:55:30.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:55:30.848 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:55:30.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:30.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:55:30.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:55:30.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:55:30.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:55:30.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:30.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:55:30.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:55:30.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:30.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:31.260 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:55:31.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:31.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:31.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:31.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:31.728 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:55:32.197 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:55:32.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:32.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:32.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:32.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:32.665 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:55:33.132 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:55:33.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:33.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:33.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:33.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:33.601 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:55:34.071 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:55:34.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:34.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:34.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:34.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:34.540 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:55:35.009 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:55:35.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:35.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:35.479 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:55:35.947 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:55:36.416 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:55:36.885 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:55:37.354 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:55:37.822 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:55:38.291 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:55:38.760 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:55:39.306 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:55:39.774 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:55:40.243 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:55:40.711 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:55:41.179 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:55:41.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:41.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:41.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:55:41.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:41.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:41.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:41.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:41.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:41.270 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:55:46.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:55:46.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:55:46.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:46.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:46.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:46.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:46.278 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:55:46.279 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:46.279 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:46.279 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:55:46.279 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:46.281 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:55:46.281 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:55:46.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:46.283 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:55:46.283 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:55:46.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:46.284 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:55:46.284 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:55:46.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.285 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:55:46.285 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:55:46.285 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:55:46.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:55:46.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:55:46.759 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:55:46.801 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:55:46.801 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:55:46.802 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:55:46.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:46.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:55:46.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:55:46.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:55:46.813 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:55:46.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:46.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:55:46.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:55:46.814 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:55:46.814 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:55:46.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:55:46.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:55:46.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:55:46.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:46.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:55:47.227 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:55:47.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:47.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:47.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:47.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:47.695 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:55:47.706 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:55:48.163 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:55:48.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:48.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:48.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:48.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:48.632 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:55:49.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:55:49.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:49.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:49.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:49.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:49.570 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:55:50.039 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:55:50.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:50.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:50.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:50.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:50.509 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:55:50.978 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:55:51.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:55:51.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:55:51.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:55:51.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:55:51.446 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:55:51.914 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:55:52.383 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:55:52.851 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:55:53.320 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:55:53.788 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:55:54.255 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:55:54.723 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:55:55.191 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:55:55.659 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:55:56.127 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:55:56.596 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:55:57.064 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:55:57.532 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:55:58.000 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:55:58.469 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:55:58.937 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:55:59.405 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:55:59.874 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:56:00.345 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:56:00.822 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:56:01.613 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:56:02.090 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:56:02.563 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:56:03.033 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:56:03.503 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:56:03.974 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:56:04.445 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:56:04.915 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:56:05.387 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:56:05.858 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:56:06.328 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:56:06.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:06.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:06.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:06.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:06.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:06.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:06.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:06.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:06.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:06.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:06.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:06.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:06.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:06.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:06.443 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:56:06.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:06.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:06.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:06.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:06.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:06.444 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:11.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:11.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:11.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:11.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:11.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:11.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:11.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:11.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:56:11.446 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:11.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:56:11.446 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:56:11.447 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:56:11.447 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:56:11.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:56:11.448 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:56:11.448 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:56:11.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:56:11.449 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:56:11.449 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:56:11.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:11.450 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:56:11.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:56:11.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:56:11.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:56:11.450 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:56:11.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:56:11.451 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:56:11.451 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:56:11.451 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:11.456 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:56:11.923 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:56:11.970 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:56:11.971 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:11.971 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:56:11.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:11.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:11.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:11.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:56:11.982 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:11.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:11.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:56:11.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:56:11.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:56:11.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:56:12.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:12.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:56:12.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:56:12.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:12.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:12.392 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:56:12.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:12.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:12.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:12.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:12.860 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:56:12.875 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:13.330 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:56:13.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:13.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:13.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:13.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:13.798 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:56:13.830 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:14.266 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:56:14.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:14.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:14.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:14.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:14.734 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:56:14.785 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:15.202 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:56:15.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:15.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:15.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:15.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:15.670 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:56:15.736 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:16.138 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:56:16.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:16.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:16.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:16.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:16.606 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:56:16.691 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:17.074 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:56:17.542 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:56:17.647 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:18.011 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:56:18.479 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:56:18.603 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:18.948 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:56:19.416 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:56:19.558 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:19.884 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:56:20.353 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:56:20.513 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:20.822 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:56:21.292 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:56:21.469 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:21.761 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:56:22.230 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:56:22.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:22.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:22.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:22.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:22.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:22.401 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:56:22.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:22.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2385 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:27.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:27.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:27.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:27.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:27.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:27.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:27.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:27.406 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:56:27.406 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:27.406 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:56:27.406 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:56:27.407 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:56:27.407 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:56:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:56:27.408 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:56:27.408 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:56:27.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:56:27.410 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:56:27.410 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:56:27.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:56:27.412 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:56:27.412 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:56:27.412 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:27.416 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:56:27.889 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:56:27.934 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:56:27.934 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:27.935 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:56:27.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:27.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:27.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:27.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:56:27.946 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:56:27.947 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:27.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:27.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:56:27.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:56:27.948 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:56:27.948 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:56:27.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:27.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:56:27.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:56:27.994 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:27.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:27.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:28.359 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:56:28.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:28.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:28.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:28.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:28.828 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:56:28.842 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:29.297 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:56:29.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:29.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:29.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:29.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:29.767 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:56:30.238 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:56:30.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:30.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:30.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:30.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:30.707 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:56:31.178 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:56:31.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:31.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:31.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:31.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:31.648 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:56:32.118 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:56:32.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:32.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:32.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:32.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:32.589 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:56:33.058 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:56:33.528 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:56:33.999 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:56:34.471 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:56:34.939 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:56:35.407 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:56:35.875 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:56:36.345 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:56:36.815 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:56:37.284 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:56:37.752 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:56:38.220 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:56:38.418 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:38.690 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:56:39.160 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:56:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:56:40.102 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:56:40.570 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:56:41.041 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:56:41.512 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:56:41.985 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:56:42.454 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:56:42.923 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:56:43.392 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:56:43.860 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:56:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:44.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:44.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:44.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:44.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:44.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:44.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:44.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:44.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:44.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:44.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:44.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:44.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:44.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:44.175 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:56:44.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3640 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:44.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3640 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:44.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3640 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:44.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3640 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:44.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3640 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:56:49.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:49.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:49.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:49.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:49.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:49.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:49.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:56:49.181 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:56:49.181 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:56:49.181 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:49.181 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:56:49.182 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:56:49.182 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:56:49.182 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:56:49.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:56:49.183 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:56:49.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:56:49.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:56:49.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:56:49.185 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:56:49.185 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:56:49.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:56:49.190 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:56:49.659 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:56:49.704 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:56:49.704 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:49.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:49.705 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:56:49.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:49.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:49.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:56:49.716 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:56:49.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:49.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:56:49.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:56:49.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:56:49.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:56:49.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:49.751 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:56:49.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:56:49.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:49.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:50.128 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:56:50.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:50.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:50.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:50.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:50.600 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:56:50.611 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:56:51.069 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:56:51.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:51.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:51.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:51.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:51.539 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:56:52.010 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:56:52.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:52.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:52.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:52.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:52.480 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:56:52.949 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:56:53.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:53.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:53.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:53.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:53.417 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:56:53.885 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:56:54.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:54.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:54.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:54.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:54.353 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:56:54.821 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:56:55.289 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:56:55.757 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:56:56.225 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:56:56.692 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:56:57.160 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:56:57.629 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:56:58.096 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:56:58.564 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:56:59.032 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:56:59.499 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:56:59.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:56:59.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:56:59.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:56:59.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:56:59.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:56:59.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:56:59.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:56:59.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:56:59.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:56:59.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:56:59.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:56:59.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:56:59.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:56:59.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:56:59.756 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:57:04.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:04.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:04.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:04.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:04.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:04.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:04.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:04.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:04.761 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:04.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:04.761 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:04.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:04.762 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:57:04.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:04.763 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:04.763 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:57:04.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:04.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:04.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:57:04.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:57:04.766 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:57:04.766 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:57:04.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:04.770 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:57:05.239 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:57:05.277 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:57:05.278 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:57:05.278 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:57:05.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:05.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:05.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:05.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:05.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:05.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:05.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:05.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:05.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:05.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:05.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:05.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.707 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:57:05.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:05.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:05.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:05.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:05.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:05.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:05.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:05.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:05.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:05.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:05.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:05.751 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:57:05.751 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:57:05.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:05.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:05.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:05.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:05.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:06.175 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:57:06.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:06.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:06.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:06.427 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:57:06.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:06.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:06.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:06.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:06.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:06.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:06.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:06.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:06.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:06.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:06.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:06.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:06.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:06.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:06.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:06.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:06.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:06.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:06.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:06.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:06.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:06.642 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:57:06.642 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:57:06.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:06.642 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:57:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:06.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:06.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:06.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:07.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:07.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:07.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:07.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:07.027 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:57:07.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:07.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:07.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:07.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:07.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:07.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:07.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:07.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:07.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:07.030 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:57:07.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:07.030 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=495 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:12.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:12.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:12.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:12.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:12.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:12.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:12.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:12.035 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:12.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:12.035 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:12.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:12.037 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:57:12.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:12.038 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:12.038 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:57:12.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:12.039 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:12.039 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:57:12.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:57:12.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:57:12.041 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:57:12.041 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:12.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:12.046 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:57:12.513 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:57:12.555 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:57:12.556 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:57:12.556 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:57:12.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:12.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:12.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:12.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:12.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:12.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:12.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:12.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:12.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:12.602 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:57:12.603 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 02:57:12.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:12.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:12.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:12.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:12.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:12.981 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:57:12.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:12.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:12.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:12.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:12.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:12.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:12.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:12.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:12.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:12.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:12.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:12.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:12.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:12.989 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:57:12.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:12.989 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:17.990 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:17.990 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:17.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:17.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:17.991 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:17.991 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:17.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:17.994 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:17.994 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:17.994 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:17.994 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:17.995 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:17.995 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:57:17.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:17.996 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:17.996 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:57:17.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:17.997 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:17.997 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:57:17.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:17.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:57:17.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:57:17.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:57:18.000 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:18.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:18.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:57:18.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:57:18.512 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:57:18.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:18.513 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:57:18.514 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:57:18.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:18.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:18.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:18.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:18.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:18.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:18.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:18.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:18.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:18.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:18.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:18.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:18.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:18.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:18.939 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:57:19.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:19.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:19.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:19.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:19.407 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:57:19.875 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:57:20.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:20.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:20.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:20.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:20.342 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:57:20.810 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:57:21.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:21.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:21.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:21.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:21.278 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:57:21.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:21.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:21.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:21.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:21.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:21.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:21.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:21.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:21.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:21.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:21.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:21.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:21.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:21.694 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:57:21.694 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 02:57:21.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:21.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:21.745 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:57:21.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:22.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:22.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:22.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:22.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:22.215 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:57:22.684 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:57:23.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:23.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:23.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:23.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:23.151 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:57:23.618 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:57:24.086 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:57:24.555 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:57:24.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:24.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:24.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:24.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:24.827 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:57:24.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:24.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:24.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:24.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:24.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:24.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:24.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:24.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:24.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:24.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:24.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:24.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:24.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:25.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:25.023 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:57:25.492 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:57:25.962 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:57:26.429 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:57:26.897 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:57:27.365 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:57:27.833 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:57:28.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:28.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:28.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:28.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:28.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:28.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:28.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:28.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:28.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:28.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:28.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:28.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:28.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:28.067 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:57:28.067 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:57:28.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:28.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:28.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:28.301 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:57:28.769 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:57:29.236 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:57:29.704 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:57:30.171 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:57:30.639 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:57:31.107 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:57:31.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:31.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:31.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:31.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:31.220 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:57:31.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:31.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:31.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:31.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:31.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:31.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:31.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:31.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:31.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:31.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:31.225 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:31.225 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2884 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:36.225 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:36.225 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:36.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:36.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:36.226 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:36.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:36.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:36.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:36.234 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:36.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:36.234 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:36.235 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:36.235 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:57:36.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:36.236 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:57:36.236 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:57:36.236 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:36.236 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:36.237 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:57:36.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:36.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:36.237 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:57:36.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:36.238 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:36.238 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:36.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:57:36.241 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:57:36.241 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:57:36.241 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:36.246 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:57:36.714 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:57:36.753 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:57:36.754 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:57:36.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:36.755 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:57:36.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:36.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:36.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:36.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:36.757 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:36.757 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:36.757 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:36.757 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:37.182 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:57:37.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:37.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:37.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:37.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:37.650 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:57:38.117 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:57:38.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:38.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:38.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:38.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:38.586 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:57:39.054 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:57:39.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:39.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:39.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:39.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:39.523 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:57:39.991 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:57:40.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:40.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:40.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:40.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:40.459 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:57:40.927 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:57:41.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:41.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:41.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:41.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:41.395 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:57:41.862 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:57:42.331 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:57:42.799 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:57:43.266 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:57:43.734 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:57:44.202 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:57:44.669 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:57:45.138 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:57:45.609 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:57:46.077 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:57:46.545 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:57:47.013 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:57:47.503 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:57:47.971 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:57:48.438 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:57:48.906 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:57:49.374 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:57:49.842 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:57:50.310 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:57:50.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:50.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:50.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:50.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:50.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:50.591 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:50.591 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:57:50.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:50.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:57:55.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:57:55.592 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:57:55.592 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:55.592 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:55.592 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:55.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:55.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:57:55.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:55.596 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:55.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:57:55.596 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:55.597 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:57:55.597 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:57:55.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:55.598 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:57:55.598 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:57:55.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:55.599 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:57:55.599 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:57:55.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:55.599 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:57:55.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:57:55.600 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:57:55.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:57:55.600 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:57:55.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:57:55.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:57:55.602 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:57:55.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:57:55.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:57:55.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:57:55.606 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:57:56.076 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:57:56.117 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:57:56.117 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:57:56.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:56.118 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:57:56.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:56.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:56.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:56.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:56.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:56.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:56.125 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:56.125 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:56.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:57:56.168 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 02:57:56.168 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 02:57:56.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:56.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:56.544 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:57:56.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:56.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:56.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:56.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:57.012 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:57:57.480 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:57:57.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:57.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:57.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:57.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:57.949 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:57:58.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:58.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:57:58.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:57:58.168 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 02:57:58.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:57:58.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:57:58.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:57:58.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:57:58.170 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:57:58.170 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:57:58.418 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:57:58.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:58.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:58.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:58.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:58.886 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:57:59.354 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:57:59.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:57:59.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:57:59.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:57:59.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:57:59.821 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:58:00.289 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:58:00.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:00.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:00.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:00.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:00.757 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:58:01.225 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:58:01.692 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:58:02.161 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:58:02.628 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:58:03.096 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:58:03.564 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:58:04.031 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:58:04.499 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:58:04.966 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:58:05.434 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:58:05.902 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:58:06.370 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:58:06.838 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:58:07.305 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:58:07.774 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:58:08.242 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:58:08.709 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:58:09.177 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:58:09.645 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:58:10.114 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:58:10.581 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:58:11.049 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:58:11.517 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:58:11.985 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:58:12.452 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:58:12.921 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:58:13.389 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:58:13.856 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:58:14.324 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:58:14.791 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:58:15.259 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:58:15.727 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:58:16.195 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:58:16.662 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:58:17.129 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:58:17.597 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:58:18.064 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:58:18.532 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:58:19.000 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:58:19.468 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:58:19.936 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:58:20.404 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:58:20.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:58:20.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:58:20.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:58:20.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:20.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:20.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:20.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:20.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:58:20.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:58:20.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:58:20.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:58:20.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:58:20.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:58:20.674 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:58:25.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:58:25.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:58:25.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:58:25.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:58:25.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:58:25.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:58:25.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:58:25.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:58:25.680 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:25.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:58:25.680 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:58:25.681 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:58:25.681 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:58:25.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:25.682 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:58:25.682 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:58:25.682 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:58:25.682 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:25.683 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:58:25.683 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:58:25.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:58:25.683 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:58:25.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:58:25.684 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:58:25.684 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:58:25.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:58:25.686 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:58:25.686 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:58:25.686 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:25.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:25.691 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:58:26.158 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:58:26.201 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:58:26.202 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:58:26.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:58:26.202 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:58:26.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:58:26.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:58:26.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:58:26.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:58:26.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:58:26.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:58:26.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:58:26.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:58:26.626 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:58:26.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:26.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:26.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:26.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:27.094 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:58:27.561 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:58:27.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:27.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:27.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:27.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:28.030 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:58:28.497 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:58:28.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:28.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:28.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:28.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:28.965 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:58:29.433 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:58:29.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:29.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:29.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:29.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:29.901 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:58:30.368 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:58:30.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:30.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:30.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:30.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:30.837 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:58:31.305 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:58:31.773 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:58:32.241 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:58:32.709 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:58:33.177 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:58:33.645 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:58:34.112 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:58:34.581 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:58:35.049 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:58:35.516 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:58:35.984 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:58:36.452 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:58:36.920 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:58:37.388 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:58:37.856 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:58:38.324 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:58:38.792 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:58:39.260 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:58:39.728 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:58:40.196 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:58:40.665 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:58:41.133 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:58:41.601 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:58:42.069 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:58:42.537 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:58:43.005 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:58:43.473 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:58:43.941 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:58:44.409 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:58:44.877 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:58:45.346 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:58:45.817 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:58:46.287 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:58:46.757 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:58:47.228 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:58:47.699 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:58:47.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:58:47.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:58:47.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:47.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:47.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:47.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:47.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:58:47.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:58:47.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:58:47.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:58:47.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:58:47.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:58:47.704 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:58:47.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4797 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:58:47.705 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4797 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:58:47.705 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4797 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:58:47.705 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4797 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:58:52.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:58:52.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:58:52.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:58:52.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:58:52.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:58:52.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:58:52.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:58:52.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:58:52.714 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:52.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:58:52.714 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:58:52.716 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:58:52.716 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:58:52.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:58:52.716 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:52.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:58:52.716 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:58:52.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:58:52.716 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:58:52.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:52.718 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:58:52.718 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:58:52.718 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:58:52.718 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:52.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:58:52.719 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:58:52.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:58:52.719 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:58:52.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:58:52.721 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:58:52.721 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:58:52.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:58:52.725 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:58:52.725 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:58:52.725 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:58:52.730 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:58:53.201 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:58:53.247 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:58:53.249 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:58:53.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:58:53.250 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:58:53.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:58:53.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:58:53.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:58:53.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:58:53.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:58:53.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:58:53.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:58:53.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:58:53.672 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:58:53.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:53.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:53.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:53.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:54.141 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:58:54.610 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:58:54.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:54.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:54.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:54.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:55.079 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:58:55.549 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:58:55.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:55.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:55.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:55.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:56.019 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:58:56.488 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:58:56.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:56.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:56.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:56.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:56.956 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:58:57.424 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:58:57.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:58:57.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:58:57.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:58:57.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:58:57.892 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:58:58.361 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:58:58.829 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:58:59.299 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:58:59.768 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:59:00.237 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:59:00.706 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:59:01.175 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:59:01.644 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:59:02.112 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:59:02.580 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:59:03.048 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:59:03.517 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:59:03.985 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:59:04.453 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:59:04.921 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:59:05.389 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:59:05.857 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:59:06.324 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:59:06.793 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:59:07.260 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:59:07.728 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:59:08.196 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:59:08.664 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:59:09.133 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:59:09.602 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:59:10.070 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:59:10.538 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:59:11.006 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:59:11.473 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:59:11.941 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:59:12.409 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:59:12.877 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:59:13.345 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:59:13.812 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:59:14.281 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:59:14.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:59:14.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:59:14.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:14.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:14.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:14.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:14.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:59:14.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:59:14.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:59:14.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:59:14.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:59:14.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:59:14.740 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:59:19.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:59:19.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:59:19.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:59:19.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:59:19.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:59:19.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:59:19.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:59:19.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:59:19.745 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:19.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:59:19.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:59:19.746 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:59:19.746 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:59:19.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:59:19.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:59:19.747 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:59:19.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:59:19.748 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:59:19.748 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:59:19.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:59:19.750 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:59:19.750 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:59:19.750 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:19.754 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:59:20.222 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:59:20.263 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:59:20.264 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:59:20.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:59:20.265 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:59:20.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:59:20.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:59:20.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:59:20.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:59:20.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:59:20.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:59:20.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:59:20.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:59:20.689 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:59:20.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:20.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:20.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:20.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:21.157 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 02:59:21.624 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 02:59:21.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:21.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:21.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:21.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:22.092 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 02:59:22.559 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 02:59:22.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:22.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:22.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:22.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:23.027 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 02:59:23.494 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 02:59:23.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:23.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:23.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:23.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:23.962 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 02:59:24.430 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 02:59:24.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:24.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:24.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:24.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:24.897 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 02:59:25.365 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 02:59:25.833 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 02:59:26.301 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 02:59:26.769 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 02:59:27.236 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 02:59:27.703 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 02:59:28.171 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 02:59:28.638 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 02:59:29.106 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 02:59:29.573 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 02:59:30.040 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 02:59:30.508 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 02:59:30.976 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 02:59:31.443 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 02:59:31.911 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 02:59:32.378 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 02:59:32.846 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 02:59:33.314 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 02:59:33.781 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 02:59:34.249 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 02:59:34.716 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 02:59:35.185 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 02:59:35.654 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 02:59:36.121 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 02:59:36.590 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 02:59:37.058 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 02:59:37.526 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 02:59:37.994 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 02:59:38.462 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 02:59:38.930 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 02:59:39.398 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 02:59:39.865 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 02:59:40.333 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 02:59:40.802 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 02:59:41.270 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 02:59:41.738 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 02:59:42.206 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 02:59:42.674 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 02:59:43.142 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 02:59:43.609 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 02:59:44.077 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 02:59:44.545 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 02:59:45.013 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 02:59:45.481 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 02:59:45.950 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 02:59:46.419 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 02:59:46.888 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 02:59:47.356 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 02:59:47.825 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 02:59:48.293 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 02:59:48.761 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 02:59:49.230 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 02:59:49.698 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 02:59:50.166 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 02:59:50.634 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 02:59:51.102 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 02:59:51.571 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 02:59:52.039 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 02:59:52.508 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 02:59:52.976 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 02:59:53.444 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 02:59:53.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:59:53.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:59:53.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:53.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:53.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:53.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:53.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:59:53.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:59:53.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:59:53.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:59:53.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:59:53.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:59:53.776 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7417 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7417 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7417 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7417 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7417 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7417 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:53.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7418 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 02:59:58.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 02:59:58.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 02:59:58.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:59:58.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:59:58.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:59:58.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:59:58.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 02:59:58.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:59:58.795 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:58.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 02:59:58.795 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:59:58.797 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 02:59:58.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:58.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:59:58.799 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 02:59:58.799 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 02:59:58.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:59:58.801 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 02:59:58.801 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 02:59:58.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 02:59:58.803 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 02:59:58.803 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 02:59:58.803 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 02:59:58.808 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 02:59:59.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 02:59:59.335 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 02:59:59.337 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 02:59:59.339 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 02:59:59.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 02:59:59.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 02:59:59.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 02:59:59.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 02:59:59.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 02:59:59.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 02:59:59.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 02:59:59.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 02:59:59.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 02:59:59.761 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 02:59:59.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 02:59:59.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 02:59:59.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 02:59:59.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:00.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:00:00.699 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:00:00.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:00.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:00.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:00.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:01.172 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:00:01.641 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:00:01.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:01.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:01.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:01.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:02.111 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:00:02.581 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:00:02.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:02.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:02.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:02.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:03.050 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:00:03.520 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:00:03.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:03.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:03.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:03.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:03.990 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:00:04.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:00:04.931 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:00:05.400 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:00:05.868 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:00:06.339 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:00:06.810 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:00:07.281 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:00:07.750 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:00:08.218 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:00:08.689 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:00:09.159 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:00:09.628 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:00:10.097 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:00:10.567 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:00:11.038 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:00:11.507 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:00:11.976 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:00:12.445 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:00:12.914 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:00:13.382 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:00:13.852 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:00:14.320 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:00:14.790 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:00:15.259 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:00:15.729 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:00:16.198 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:00:16.667 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:00:17.136 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:00:17.606 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:00:18.077 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:00:18.547 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:00:19.016 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:00:19.485 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:00:19.955 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:00:20.431 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:00:20.903 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:00:21.373 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:00:21.842 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:00:22.312 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:00:22.780 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:00:23.249 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:00:23.718 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:00:24.187 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:00:24.658 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:00:25.126 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:00:25.594 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:00:26.065 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:00:26.536 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:00:26.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:00:26.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:00:26.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:26.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:26.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:26.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:26.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:26.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:26.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:26.832 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:26.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:26.832 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:00:26.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:26.832 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6084 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:26.833 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6085 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:31.831 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:31.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:31.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:31.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:31.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:31.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:31.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:31.853 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:31.853 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:31.854 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:31.854 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:00:31.855 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:00:31.856 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:00:31.856 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:31.856 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:31.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:31.857 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:00:31.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:31.857 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:00:31.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:31.857 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:00:31.857 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:00:31.858 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:31.858 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:31.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:31.858 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:00:31.858 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:31.858 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:00:31.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:31.859 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:00:31.859 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:00:31.859 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:31.859 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:31.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:31.860 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:00:31.860 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:31.860 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:00:31.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:00:31.862 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:00:31.862 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:00:31.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.862 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:31.867 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:00:32.340 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:00:32.386 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:00:32.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:00:32.388 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:00:32.390 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:00:32.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:32.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:32.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:32.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:32.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:32.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:32.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:32.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:32.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:32.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:32.404 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:00:32.404 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:32.404 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:32.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:32.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:32.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:32.405 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:37.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:37.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:37.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:37.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:37.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:37.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:37.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:37.407 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:37.407 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:37.407 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:37.407 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:37.409 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:37.409 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:00:37.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:37.411 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:37.411 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:00:37.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:37.412 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:37.412 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:00:37.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.414 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:00:37.415 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:00:37.415 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:00:37.415 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:37.419 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:00:37.887 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:00:37.930 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:00:37.931 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:00:37.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:00:37.931 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:00:37.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:37.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:37.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:37.935 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:00:42.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:42.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:42.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:42.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:42.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:42.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:42.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:42.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:42.955 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:42.955 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:42.955 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:00:42.957 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:00:42.958 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:00:42.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:42.958 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:42.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:42.958 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:00:42.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:42.958 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:00:42.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:42.960 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:42.960 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:00:42.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:42.962 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:42.962 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:00:42.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:42.964 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:00:42.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:00:42.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:00:42.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:00:42.964 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:00:42.965 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:00:42.965 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:00:42.965 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:00:42.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:42.970 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:00:43.440 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:00:43.489 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:00:43.491 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:00:43.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:00:43.493 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:00:43.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:43.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:43.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:43.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:43.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:43.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:43.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:43.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:43.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:43.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:43.511 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:43.512 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:00:48.508 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:48.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:48.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:48.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:48.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:48.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:48.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:48.512 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:48.512 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:48.512 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:00:48.512 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:00:48.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:00:48.513 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:00:48.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:48.513 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:48.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:48.513 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:00:48.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:00:48.513 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:00:48.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:48.514 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:00:48.514 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:00:48.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:48.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:48.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:48.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:00:48.515 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:48.515 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:00:48.515 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:00:48.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:00:48.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:00:48.517 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:00:48.517 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:00:48.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:00:48.522 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:00:48.990 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:00:49.038 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:00:49.039 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:00:49.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:00:49.041 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:00:49.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:00:49.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:00:49.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:00:49.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:00:49.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:00:49.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:00:49.045 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:00:49.045 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:00:49.462 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:00:49.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:49.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:49.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:49.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:49.933 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:00:50.401 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:00:50.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:50.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:50.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:50.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:50.869 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:00:51.337 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:00:51.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:51.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:51.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:51.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:51.805 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:00:52.273 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:00:52.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:52.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:52.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:52.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:52.741 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:00:53.208 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:00:53.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:53.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:53.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:53.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:53.676 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:00:54.143 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:00:54.611 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:00:55.078 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:00:55.547 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:00:56.015 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:00:56.482 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:00:56.950 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:00:57.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:00:57.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:00:57.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:00:57.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:00:57.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:00:57.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:00:57.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:00:57.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:00:57.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:00:57.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:00:57.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:00:57.084 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:00:57.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:02.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:02.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:02.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:02.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:02.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:02.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:02.088 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:02.088 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:02.088 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:02.088 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:02.088 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:02.089 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:02.089 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:01:02.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:02.090 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:02.090 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:01:02.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:02.091 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:02.091 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:01:02.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.092 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:01:02.092 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:01:02.092 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:01:02.093 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:02.097 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:01:02.565 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:01:02.604 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:01:02.605 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:01:02.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:01:02.605 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:01:02.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:02.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:02.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:01:02.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:01:02.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:01:02.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:01:02.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:01:02.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:01:03.032 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:01:03.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:03.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:03.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:03.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:03.500 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:01:03.968 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:01:04.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:04.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:04.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:04.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:04.436 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:01:04.904 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:01:05.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:05.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:05.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:05.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:05.372 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:01:05.840 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:01:06.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:06.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:06.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:06.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:06.307 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:01:06.775 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:01:07.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:07.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:07.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:07.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:07.243 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:01:07.710 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:01:08.178 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:01:08.646 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:01:09.113 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:01:09.581 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:01:10.048 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:01:10.516 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:01:10.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:10.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:10.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:10.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:10.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:10.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:10.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:10.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:10.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:10.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:10.611 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:10.611 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:01:10.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:10.611 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:15.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:15.620 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:15.620 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:15.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:15.620 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:15.621 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:15.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:01:15.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:15.622 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:01:15.622 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:01:15.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:15.623 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:15.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:15.623 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:01:15.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:15.623 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:01:15.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:15.624 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:15.624 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:01:15.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:01:15.626 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:01:15.626 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:01:15.626 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:15.631 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:01:16.098 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:01:16.139 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:01:16.140 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:01:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:01:16.140 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:01:16.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:16.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:16.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:01:16.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:01:16.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:01:16.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:01:16.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:01:16.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:01:16.566 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:01:16.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:16.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:16.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:16.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:17.033 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:01:17.501 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:01:17.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:17.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:17.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:17.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:17.969 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:01:18.436 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:01:18.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:18.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:18.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:18.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:18.904 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:01:19.371 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:01:19.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:19.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:19.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:19.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:19.839 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:01:20.307 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:01:20.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:20.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:20.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:20.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:20.774 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:01:21.242 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:01:21.710 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:01:22.177 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:01:22.645 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:01:23.113 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:01:23.580 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:01:24.049 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:01:24.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:24.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:24.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:24.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:24.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:24.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:24.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:24.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:24.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:24.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:24.192 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:24.192 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:24.192 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:01:29.193 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:29.193 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:29.193 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:29.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:29.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:29.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:29.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:29.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:29.197 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:29.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:29.197 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:29.198 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:29.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:01:29.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:29.199 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:01:29.200 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:01:29.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:29.200 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:29.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:29.200 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:01:29.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:29.200 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:01:29.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:29.201 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:29.201 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:01:29.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:01:29.203 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:01:29.203 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:29.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:29.208 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:01:29.675 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:01:29.719 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:01:29.720 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:01:29.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:01:29.720 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:01:29.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:29.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:29.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:01:29.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:01:29.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:01:29.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:01:29.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:01:29.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:01:30.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:01:30.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:30.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:30.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:30.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:30.611 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:01:31.078 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:01:31.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:31.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:31.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:31.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:31.547 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:01:32.014 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:01:32.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:32.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:32.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:32.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:32.482 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:01:32.949 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:01:33.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:33.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:33.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:33.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:33.417 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:01:33.885 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:01:34.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:34.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:34.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:34.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:34.352 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:01:34.821 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:01:35.288 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:01:35.756 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:01:36.224 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:01:36.692 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:01:37.160 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:01:37.627 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:01:37.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:37.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:37.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:37.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:37.767 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:37.768 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:42.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:42.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:42.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:42.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:42.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:42.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:42.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:42.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:42.772 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:42.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:42.772 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:01:42.773 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:01:42.773 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:01:42.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:42.773 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:42.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:42.774 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:01:42.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:42.774 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:01:42.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:42.775 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:42.775 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:01:42.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:42.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:42.776 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:01:42.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:01:42.778 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:01:42.778 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:01:42.778 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:42.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:42.783 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:01:43.250 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:01:43.293 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:01:43.294 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:01:43.294 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:01:43.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:01:43.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:43.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:43.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:01:43.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:01:43.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:01:43.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:01:43.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:01:43.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:01:43.718 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:01:43.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:43.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:43.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:43.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:44.185 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:01:44.653 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:01:44.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:44.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:44.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:44.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:45.121 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:01:45.589 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:01:45.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:45.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:45.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:45.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:46.056 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:01:46.524 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:01:46.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:46.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:46.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:46.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:46.992 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:01:47.459 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:01:47.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:47.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:47.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:47.927 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:01:48.395 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:01:48.863 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:01:49.331 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:01:49.799 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:01:50.268 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:01:50.736 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:01:51.205 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:01:51.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:51.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:51.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:51.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:51.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:51.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:51.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:51.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:51.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:51.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:51.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:51.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:51.346 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:51.346 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:01:56.346 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:01:56.346 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:01:56.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:56.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:56.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:56.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:56.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:01:56.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:56.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:56.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:01:56.350 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:56.351 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:01:56.351 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:01:56.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:56.352 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:01:56.352 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:01:56.352 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:56.352 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:56.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:01:56.352 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:01:56.352 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:01:56.352 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:01:56.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:56.354 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:01:56.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:01:56.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.355 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:01:56.355 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:01:56.355 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:01:56.356 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:01:56.360 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:01:56.828 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:01:56.872 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:01:56.873 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:01:56.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:01:56.874 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:01:56.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:01:56.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:01:56.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:01:56.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:01:56.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:01:56.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:01:56.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:01:56.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:01:57.297 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:01:57.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:57.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:57.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:57.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:57.766 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:01:58.236 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:01:58.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:58.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:58.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:58.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:58.705 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:01:59.176 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:01:59.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:01:59.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:01:59.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:01:59.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:01:59.645 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:02:00.114 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:02:00.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:00.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:00.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:00.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:00.585 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:02:01.054 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:02:01.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:01.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:01.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:01.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:01.523 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:02:01.993 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:02:02.463 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:02:02.933 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:02:03.402 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:02:03.871 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:02:04.340 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:02:04.808 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:02:05.276 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:02:05.744 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:02:06.213 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:02:06.681 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:02:07.148 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:02:07.616 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:02:08.085 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:02:08.553 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:02:09.021 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:02:09.489 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:02:09.957 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:02:10.425 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:02:10.893 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:02:11.362 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:02:11.830 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:02:12.299 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:02:12.767 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:02:12.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:12.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:12.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:12.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:12.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:12.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:12.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:12.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:12.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:12.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:12.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:12.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:12.923 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:02:17.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:17.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:17.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:17.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:17.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:17.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:17.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:17.929 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:17.929 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:17.929 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:17.929 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:17.930 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:17.930 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:17.930 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:02:17.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:17.931 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:17.931 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:02:17.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:02:17.933 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:02:17.933 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:02:17.933 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:17.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:17.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:17.938 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:02:18.413 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:02:18.446 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:02:18.446 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:02:18.447 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:02:18.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:02:18.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:18.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:18.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:02:18.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:02:18.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:02:18.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:02:18.451 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:02:18.451 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:02:18.881 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:02:18.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:18.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:18.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:18.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:19.349 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:02:19.817 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:02:19.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:19.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:19.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:19.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:20.286 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:02:20.755 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:02:20.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:20.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:20.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:20.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:21.223 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:02:21.692 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:02:21.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:21.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:21.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:21.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:22.161 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:02:22.632 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:02:22.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:22.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:22.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:22.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:23.103 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:02:23.573 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:02:24.044 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:02:24.515 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:02:24.986 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:02:25.456 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:02:25.927 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:02:26.398 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:02:26.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:26.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:26.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:26.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:26.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:26.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:26.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:26.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:26.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:26.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:26.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:26.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:26.467 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:26.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:31.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:31.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:31.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:31.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:31.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:31.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:31.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:31.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:31.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:31.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:31.472 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:31.473 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:31.473 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:02:31.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:31.474 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:02:31.474 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:02:31.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:31.474 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:31.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:31.475 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:02:31.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:31.475 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:02:31.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:31.476 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:31.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:02:31.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:31.477 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:02:31.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:02:31.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:02:31.478 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:02:31.478 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:02:31.478 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:31.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:31.483 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:02:31.953 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:02:31.996 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:02:31.997 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:02:31.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:02:31.997 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:02:32.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:32.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:32.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:02:32.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:02:32.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:02:32.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:02:32.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:02:32.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:02:32.421 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:02:32.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:32.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:32.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:32.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:32.890 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:02:33.358 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:02:33.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:33.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:33.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:33.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:33.826 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:02:34.294 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:02:34.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:34.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:34.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:34.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:34.762 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:02:35.230 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:02:35.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:35.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:35.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:35.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:35.697 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:02:36.165 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:02:36.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:36.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:36.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:36.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:36.632 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:02:37.100 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:02:37.567 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:02:38.039 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:02:38.508 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:02:38.976 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:02:39.447 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:02:39.916 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:02:40.385 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:02:40.855 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:02:41.325 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:02:41.794 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:02:42.263 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:02:42.733 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:02:43.203 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:02:43.672 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:02:44.148 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:02:44.620 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:02:45.091 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:02:45.561 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:02:46.030 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:02:46.503 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:02:46.972 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:02:47.440 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:02:47.910 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:02:48.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:48.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:48.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:48.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:48.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:48.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:48.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:48.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:48.057 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:02:48.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:53.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:53.059 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:53.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:53.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:53.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:53.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:53.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:53.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:53.063 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:53.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:02:53.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:53.064 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:02:53.064 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:02:53.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:53.065 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:53.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:53.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:53.066 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:53.066 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:02:53.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:53.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:53.067 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:02:53.067 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:02:53.068 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:02:53.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:53.069 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:02:53.069 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:02:53.069 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:02:53.069 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:53.074 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:02:53.542 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:02:53.597 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:02:53.598 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:02:53.600 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:02:53.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:02:53.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:53.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:53.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:02:53.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:53.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:53.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:53.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:53.616 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:53.616 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:53.616 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:53.616 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:53.616 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:53.616 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:53.616 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:02:53.616 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:53.617 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:53.617 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:53.617 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:53.617 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:53.617 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:53.617 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:58.617 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:58.617 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:58.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:58.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:58.622 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:58.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:58.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:58.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:58.638 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:58.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:02:58.638 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:02:58.641 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:02:58.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:02:58.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:58.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:58.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:58.642 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:02:58.642 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:02:58.642 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:02:58.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:58.644 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:02:58.644 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:02:58.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:58.646 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:02:58.646 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:02:58.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:58.646 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:02:58.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:58.646 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:02:58.647 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:02:58.647 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:02:58.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:02:58.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:02:58.650 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:02:58.650 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:02:58.650 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:02:58.655 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:02:59.127 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:02:59.168 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:02:59.169 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:02:59.169 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:02:59.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:02:59.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:02:59.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:02:59.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:02:59.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:02:59.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:02:59.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:02:59.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:02:59.199 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:02:59.199 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:02:59.199 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:02:59.199 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:02:59.199 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:02:59.199 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:02:59.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:02:59.200 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.200 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.200 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.200 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.200 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.200 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.201 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:02:59.201 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.203 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:04.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:04.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:04.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:04.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:04.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:04.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:04.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:04.210 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:04.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:04.210 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:03:04.211 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:03:04.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:03:04.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:04.212 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:04.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:04.212 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:03:04.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:04.212 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:03:04.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:04.214 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:04.214 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:03:04.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:04.216 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:03:04.216 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:03:04.216 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:04.216 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:04.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:04.216 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:03:04.216 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:04.216 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:03:04.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:03:04.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:03:04.220 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:03:04.220 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:03:04.220 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:04.225 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:03:04.697 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:03:04.744 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:03:04.745 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:03:04.745 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:03:04.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:03:04.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:04.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:04.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:04.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:04.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:04.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:04.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:04.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:04.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:04.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:04.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:04.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:04.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:04.777 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.777 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:04.778 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:09.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:09.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:09.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:09.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:09.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:09.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:09.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:09.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:09.781 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:09.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:09.782 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:03:09.783 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:03:09.783 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:03:09.783 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:09.784 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:09.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:09.784 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:03:09.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:09.784 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:03:09.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:09.785 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:03:09.785 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:03:09.785 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:09.785 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:09.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:09.786 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:03:09.786 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:09.786 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:03:09.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:09.787 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:03:09.787 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:03:09.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:09.787 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:09.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:09.788 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:03:09.788 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:09.788 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:03:09.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:03:09.790 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:03:09.790 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:03:09.790 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:09.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:09.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:09.795 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:03:10.269 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:03:10.310 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:03:10.311 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:03:10.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:03:10.312 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:03:10.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:10.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:10.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:10.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:10.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:10.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:10.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:10.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:10.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:10.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:10.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:10.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:10.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:10.338 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:03:15.340 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:15.340 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:15.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:15.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:15.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:15.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:15.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:15.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:15.344 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:15.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:15.344 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:15.346 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:15.346 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:03:15.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:15.348 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:03:15.348 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:03:15.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:15.348 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:15.348 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:03:15.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:15.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:15.349 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:03:15.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:15.351 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:03:15.351 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:03:15.351 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:15.351 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:15.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:15.351 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:03:15.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:15.352 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:03:15.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:15.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:03:15.355 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:03:15.355 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:03:15.355 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:15.360 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:03:15.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:03:15.873 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:03:15.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:03:15.874 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:03:15.875 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:03:15.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:15.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:15.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:15.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:15.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:15.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:15.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:15.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:15.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:15.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:15.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:15.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:15.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:15.896 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:15.896 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:15.896 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:03:15.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:15.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:20.898 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:20.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:20.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:20.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:20.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:20.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:20.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:20.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:20.912 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:20.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:20.912 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:03:20.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:03:20.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:03:20.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:20.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:20.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:20.915 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:03:20.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:20.915 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:03:20.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:20.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:20.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:03:20.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:20.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:03:20.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:03:20.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:20.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:20.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:20.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:03:20.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:20.921 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:03:20.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:03:20.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:03:20.924 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:03:20.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:20.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:03:21.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:03:21.460 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:03:21.462 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:03:21.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:03:21.463 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:03:21.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:21.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:21.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:21.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:21.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:21.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:21.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:21.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:21.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:21.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:21.494 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:03:21.494 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:21.494 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:21.494 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:21.494 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:21.494 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:03:26.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:03:26.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:03:26.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:26.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:26.503 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:26.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:26.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:03:26.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:26.516 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:26.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:03:26.516 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:26.519 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:03:26.519 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:03:26.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:26.522 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:03:26.522 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:03:26.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:26.524 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:03:26.524 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:03:26.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:26.524 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:03:26.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:03:26.525 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:03:26.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:03:26.525 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:03:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:26.527 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:03:26.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:03:26.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:03:26.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:03:26.527 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:03:26.528 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:03:26.528 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:03:26.528 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:03:26.533 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:03:27.002 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:03:27.044 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:03:27.045 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:03:27.045 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:03:27.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:03:27.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:03:27.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:03:27.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:03:27.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:03:27.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:03:27.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:03:27.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:03:27.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:03:27.470 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:03:27.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:27.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:27.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:27.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:27.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:03:28.410 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:03:28.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:28.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:28.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:28.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:28.879 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:03:29.350 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:03:29.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:29.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:29.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:29.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:29.819 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:03:30.288 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:03:30.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:30.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:30.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:30.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:30.756 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:03:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:03:31.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:03:31.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:03:31.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:03:31.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:03:31.707 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:03:32.183 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:03:32.655 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:03:33.131 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:03:33.600 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:03:34.069 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:03:34.540 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:03:35.010 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:03:35.482 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:03:35.955 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:03:36.431 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:03:36.903 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:03:37.379 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:03:37.851 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:03:38.326 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:03:38.795 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:03:39.265 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:03:39.736 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:03:40.206 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:03:40.675 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:03:41.148 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:03:41.620 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:03:42.088 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:03:42.555 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:03:43.026 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:03:43.493 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:03:43.962 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:03:44.431 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:03:44.899 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:03:45.369 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:03:45.837 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:03:46.305 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:03:46.773 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:03:47.242 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:03:47.710 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:03:48.178 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:03:48.647 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:03:49.116 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:03:49.586 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:03:50.054 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:03:50.522 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:03:50.993 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:03:51.464 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:03:51.932 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:03:52.400 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:03:52.872 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:03:53.340 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:03:53.809 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:03:54.277 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:03:54.744 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:03:55.214 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:03:55.685 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:03:56.154 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:03:56.622 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:03:57.090 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:03:57.559 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:03:58.029 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:03:58.500 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:03:58.969 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:03:59.438 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:03:59.910 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:04:00.378 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:04:00.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:04:00.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:04:00.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:00.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:00.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:00.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:00.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:00.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:00.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:00.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:00.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:00.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:00.549 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:04:05.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:05.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:05.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:05.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:05.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:05.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:05.553 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:05.553 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:05.553 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:05.553 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:05.553 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:05.554 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:05.554 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:04:05.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:05.555 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:05.555 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:04:05.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:05.556 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:05.556 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:04:05.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:04:05.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:04:05.558 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:04:05.558 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:05.563 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:04:06.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:04:06.089 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:04:06.090 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:04:06.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:06.091 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:04:06.505 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:04:06.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:06.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:06.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:06.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:06.973 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:04:07.440 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:04:07.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:07.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:07.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:07.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:07.907 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:04:08.377 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:04:08.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:08.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:08.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:08.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:08.845 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:04:09.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:09.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:09.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:09.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:09.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:09.105 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:09.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:09.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:09.105 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:09.105 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:09.105 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:04:09.105 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:14.105 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:14.105 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:14.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:14.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:14.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:14.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:14.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:14.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:14.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:14.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:14.109 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:14.110 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:14.110 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:04:14.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:14.111 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:04:14.111 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:04:14.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:14.111 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:14.111 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:14.111 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:04:14.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:14.111 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:04:14.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:14.112 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:04:14.113 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:04:14.113 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:14.113 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:14.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:14.113 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:04:14.113 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:14.113 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:04:14.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:04:14.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:04:14.115 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:04:14.115 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:04:14.115 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:14.119 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:04:14.587 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:04:14.629 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:04:14.629 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:04:14.630 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:04:14.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:15.055 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:04:15.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:15.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:15.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:15.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:15.522 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:04:15.990 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:04:16.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:16.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:16.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:16.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:16.457 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:04:16.925 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:04:17.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:17.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:17.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:17.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:17.392 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:04:17.859 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:04:18.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:18.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:18.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:18.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:18.327 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:04:18.794 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:04:19.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:19.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:19.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:19.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:19.262 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:04:19.730 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:04:20.198 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:04:20.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:20.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:20.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:20.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:20.634 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:04:25.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:25.635 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:25.635 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:25.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:25.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:25.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:25.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:25.639 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:25.640 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:25.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:25.640 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:25.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:25.641 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:04:25.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:25.642 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:25.642 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:04:25.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:25.643 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:04:25.644 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:04:25.644 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:25.644 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:25.644 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:25.644 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:04:25.644 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:25.644 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:04:25.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:04:25.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:04:25.646 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:04:25.646 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:04:25.646 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:25.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:25.650 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:04:26.118 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:04:26.161 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:04:26.161 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:04:26.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:26.162 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:04:26.585 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:04:26.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:26.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:26.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:26.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:27.053 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:04:27.521 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:04:27.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:27.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:27.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:27.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:27.988 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:04:28.455 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:04:28.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:28.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:28.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:28.653 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:28.923 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:04:29.390 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:04:29.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:29.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:29.653 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:29.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:29.858 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:04:30.325 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:04:30.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:30.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:30.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:30.653 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:30.792 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:04:31.261 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:04:31.728 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:04:32.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:32.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:32.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:32.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:32.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:32.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:32.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:32.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:32.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:32.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:04:32.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:37.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:37.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:37.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:37.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:37.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:37.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:37.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:37.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:37.175 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:37.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:37.175 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:37.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:37.176 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:04:37.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:37.177 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:04:37.178 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:04:37.178 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:37.178 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:37.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:37.178 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:04:37.178 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:37.178 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:04:37.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:37.179 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:37.179 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:04:37.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:04:37.181 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:04:37.181 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:04:37.181 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:37.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:37.186 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:04:37.653 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:04:37.697 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:04:37.697 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:04:37.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:37.698 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:04:38.121 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:04:38.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:38.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:38.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:38.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:38.597 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:04:39.068 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:04:39.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:39.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:39.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:39.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:39.537 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:04:40.005 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:04:40.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:40.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:40.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:40.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:40.476 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:04:40.946 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:04:41.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:41.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:41.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:41.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:41.417 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:04:41.888 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:04:42.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:42.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:42.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:42.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:42.359 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:04:42.830 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:04:43.300 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:43.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:43.701 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:04:43.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:48.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:48.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:48.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:48.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:48.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:48.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:48.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:48.707 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:48.707 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:48.707 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:04:48.707 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:48.708 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:04:48.708 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:48.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:48.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:04:48.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:04:48.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:48.711 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:04:48.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:04:48.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:04:48.713 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:04:48.713 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:04:48.713 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:04:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:04:48.718 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:04:49.188 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:04:49.226 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:04:49.227 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:04:49.227 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:04:49.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:49.656 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:04:49.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:49.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:49.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:49.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:50.127 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:04:50.595 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:04:50.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:50.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:50.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:50.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:51.062 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:04:51.529 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:04:51.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:51.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:51.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:51.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:51.996 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:04:52.463 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:04:52.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:52.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:52.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:52.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:52.931 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:04:53.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:04:53.398 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:04:53.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:53.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:53.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:53.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:53.865 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:04:54.332 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:04:54.799 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:04:55.267 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:04:55.734 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:04:56.201 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:04:56.669 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:04:57.136 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:04:57.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:04:57.238 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:04:57.238 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:04:57.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1860 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:04:57.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1860 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:04:57.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1860 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:04:57.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1860 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:04:57.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:04:57.239 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:02.239 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:02.239 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:02.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:02.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:02.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:02.243 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:02.243 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:02.243 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:02.243 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:02.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:02.244 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:02.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:02.245 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:02.245 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:02.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:02.246 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:02.246 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:02.246 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:02.246 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:02.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:02.247 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:02.247 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:02.247 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:02.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.248 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:02.248 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:02.248 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:02.249 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:02.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:02.253 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:02.722 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:02.761 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:02.762 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:02.762 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:02.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:03.191 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:05:03.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:03.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:03.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:03.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:03.661 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:05:04.131 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:05:04.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:04.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:04.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:04.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:04.600 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:05:05.070 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:05:05.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:05.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:05.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:05.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:05.541 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:05:06.012 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:05:06.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:06.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:06.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:06.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:06.483 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:05:06.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:06.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:06.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:06.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:06.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:06.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:06.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:06.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:06.769 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:11.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:11.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:11.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:11.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:11.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:11.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:11.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:11.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:11.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:11.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:11.773 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:11.774 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:11.774 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:11.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:11.775 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:11.775 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:11.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:11.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:11.776 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:11.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.778 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:11.778 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:11.778 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:11.778 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:11.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:11.783 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:12.251 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:12.294 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:12.295 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:12.296 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:12.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:12.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:12.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:12.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:12.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:12.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:12.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:12.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:12.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:12.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:12.300 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:12.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:17.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:17.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:17.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:17.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:17.301 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:17.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:17.307 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:17.307 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:17.307 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:17.307 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:17.307 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:17.308 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:17.308 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:17.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:17.309 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:17.309 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:17.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:17.310 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:17.310 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:17.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.311 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:17.311 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:17.311 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:17.312 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:17.316 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:17.786 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:17.824 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:17.825 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:17.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:17.826 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:17.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:17.830 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:17.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:17.830 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:17.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:17.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:22.831 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:22.831 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:22.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:22.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:22.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:22.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:22.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:22.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:22.835 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:22.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:22.836 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:22.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:22.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:22.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:22.836 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:22.837 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:22.837 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:22.837 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:22.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:22.838 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:22.838 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:22.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:22.840 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:22.840 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:22.840 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:22.844 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:23.314 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:23.351 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:23.352 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:23.352 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:23.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:23.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:23.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:23.356 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:23.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:28.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:28.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:28.360 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:28.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:28.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:28.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:28.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:28.368 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:28.368 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:28.368 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:28.368 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:28.371 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:28.372 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:28.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:28.372 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:28.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:28.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:28.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:28.372 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:28.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:28.375 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:28.375 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:28.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:28.375 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:28.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:28.375 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:28.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:28.375 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:28.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:28.377 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:28.378 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:28.378 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:28.378 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:28.378 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:28.378 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:28.378 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:28.378 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:28.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.381 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:28.381 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:28.381 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:28.382 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:28.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:28.386 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:28.869 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:28.913 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:28.915 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:28.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:28.917 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:28.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:05:28.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:05:28.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:05:28.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:28.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:05:28.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:05:28.939 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:05:28.939 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:05:29.347 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:05:29.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:29.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:29.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:29.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:29.824 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:05:30.301 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:05:30.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:30.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:30.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:30.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:30.779 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:05:31.256 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:05:31.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:31.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:31.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:31.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:31.734 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:05:31.976 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:05:31.976 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:05:31.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:31.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:32.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:05:32.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:05:32.021 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:05:32.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:32.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:32.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:32.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:32.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:32.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:32.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:32.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:32.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:32.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:32.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:32.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:37.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:37.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:37.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:37.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:37.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:37.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:37.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:37.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:37.040 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:37.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:37.041 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:37.044 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:37.045 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:37.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:37.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:37.046 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:37.046 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:37.047 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:37.047 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:37.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:37.047 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:37.048 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:37.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:37.048 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:37.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:37.048 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:37.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:37.048 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:37.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:37.050 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:37.050 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:37.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:37.050 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:37.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:37.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:37.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:37.051 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:37.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:37.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:37.054 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:37.055 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:37.059 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:37.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:37.582 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:37.584 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:37.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:37.585 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:37.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:05:37.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:05:37.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:05:37.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:37.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:05:37.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:05:37.589 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:05:37.589 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:05:38.016 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:05:38.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:38.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:38.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:38.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:38.492 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:05:38.969 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:05:39.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:39.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:39.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:39.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:39.447 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:05:39.925 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:05:40.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:40.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:40.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:40.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:40.403 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:05:40.645 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:05:40.646 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:05:40.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:40.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:40.881 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:05:41.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:41.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:41.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:41.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:41.358 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:05:41.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:05:41.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:05:41.370 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:05:41.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:41.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:41.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:41.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:41.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:41.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:41.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:41.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:41.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:41.381 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:41.381 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:41.381 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:41.381 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:41.381 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:41.381 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:41.381 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:41.381 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:41.381 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:05:46.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:46.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:46.382 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:46.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:46.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:46.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:46.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:46.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:46.391 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:46.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:05:46.391 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:05:46.393 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:05:46.393 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:05:46.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:46.394 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:46.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:46.394 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:05:46.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:05:46.394 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:05:46.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:46.396 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:05:46.396 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:05:46.396 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:46.396 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:46.396 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:46.396 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:05:46.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:05:46.397 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:05:46.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:46.398 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:05:46.398 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:05:46.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:46.399 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:05:46.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:05:46.399 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:05:46.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:05:46.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:05:46.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:46.401 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:05:46.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:05:46.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:05:46.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:05:46.401 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:05:46.402 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:05:46.402 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:05:46.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:05:46.407 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:05:46.892 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:05:46.933 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:05:46.936 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:05:46.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:46.938 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:05:46.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:05:46.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:05:46.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:05:46.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:46.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:05:46.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:05:46.948 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:05:46.948 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:05:47.364 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:05:47.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:47.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:47.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:47.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:47.842 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:05:48.316 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:05:48.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:48.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:48.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:48.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:48.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:05:49.261 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:05:49.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:49.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:49.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:49.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:49.738 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:05:49.999 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:05:50.000 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:05:50.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:50.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:05:50.215 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:05:50.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:50.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:50.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:50.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:50.693 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:05:51.170 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:05:51.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:51.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:51.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:51.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:51.648 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:05:52.126 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:05:52.600 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:05:53.078 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:05:53.551 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:05:54.027 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:05:54.505 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:05:54.983 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:05:55.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:05:55.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:05:55.003 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:05:55.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:05:55.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:05:55.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:05:55.021 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:05:55.021 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:05:55.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:00.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:00.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:00.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:00.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:00.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:00.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:00.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:00.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:00.041 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:00.042 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:00.042 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:06:00.044 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:06:00.044 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:06:00.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:00.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:00.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:00.045 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:06:00.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:00.045 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:06:00.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:00.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:06:00.047 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:06:00.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:00.047 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:00.047 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:06:00.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:00.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:00.047 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:06:00.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:00.048 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:06:00.048 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:06:00.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:00.048 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:00.048 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:06:00.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:00.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:00.048 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:06:00.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:06:00.051 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:06:00.051 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:06:00.051 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:00.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:06:00.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:06:00.571 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:06:00.572 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:06:00.573 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:06:00.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:00.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:00.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:00.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:06:00.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:00.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:06:00.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:06:00.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:06:00.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:06:01.016 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:06:01.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:01.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:01.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:01.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:01.493 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:06:01.970 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:06:02.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:02.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:02.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:02.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:02.448 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:06:02.926 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:06:03.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:03.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:03.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:03.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:03.403 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:06:03.645 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:06:03.645 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:06:03.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:03.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:03.881 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:06:04.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:04.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:04.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:04.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:04.354 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:06:04.823 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:06:05.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:05.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:05.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:05.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:05.293 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:06:05.763 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:06:06.233 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:06:06.710 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:06:07.188 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:06:07.666 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:06:08.140 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:06:08.609 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:06:08.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:08.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:08.649 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:06:08.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:08.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:08.666 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:08.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:08.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:08.668 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:08.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:08.668 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:08.668 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:08.668 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:08.668 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:06:08.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1850 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:08.668 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1851 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:13.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:13.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:13.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:13.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:13.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:13.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:13.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:13.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:13.681 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:13.682 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:13.682 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:06:13.684 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:06:13.684 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:06:13.685 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:13.685 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:13.685 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:13.686 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:06:13.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:13.686 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:06:13.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:13.687 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:06:13.687 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:06:13.688 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:13.688 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:13.688 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:13.688 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:06:13.688 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:13.688 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:06:13.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:13.690 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:06:13.690 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:06:13.690 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:13.690 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:13.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:13.690 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:06:13.691 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:13.691 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:06:13.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:13.693 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.694 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:06:13.694 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:06:13.694 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:06:13.695 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:13.699 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:06:14.182 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:06:14.223 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:06:14.224 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:06:14.226 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:06:14.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:14.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:14.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:14.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:06:14.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:14.231 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:06:14.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:06:14.231 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:06:14.231 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:06:14.659 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:06:14.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:14.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:14.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:14.704 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:15.137 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:06:15.615 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:06:15.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:15.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:15.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:15.704 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:16.093 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:06:16.570 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:06:16.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:16.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:16.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:16.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:17.048 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:06:17.290 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:06:17.290 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:06:17.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:17.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:17.523 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:06:17.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:17.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:17.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:17.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:17.992 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:06:18.461 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:06:18.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:18.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:18.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:18.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:18.931 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:06:19.409 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:06:19.887 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:06:20.364 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:06:20.842 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:06:21.320 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:06:21.798 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:06:22.275 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:06:22.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:22.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:22.293 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:06:22.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:22.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:22.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:22.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:22.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:22.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:22.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:22.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:22.313 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:06:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1845 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:22.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1846 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:27.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:27.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:27.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:27.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:27.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:27.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:27.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:27.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:27.325 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:27.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:27.326 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:06:27.329 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:06:27.329 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:06:27.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:27.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:27.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:27.331 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:06:27.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:27.331 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:06:27.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:27.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:06:27.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:06:27.333 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:27.333 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:27.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:27.333 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:06:27.333 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:27.333 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:06:27.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:27.335 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:06:27.335 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:06:27.336 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:27.336 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:27.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:27.336 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:06:27.336 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:27.336 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:06:27.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:27.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:06:27.340 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:06:27.340 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:06:27.340 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:27.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:06:27.826 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:06:27.865 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:06:27.866 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:06:27.868 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:06:27.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:27.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:27.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:27.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:06:27.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:27.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:06:27.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:06:27.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:06:27.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:06:27.917 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:06:27.917 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:06:27.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:27.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:28.304 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:06:28.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:28.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:28.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:28.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:28.783 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:06:29.261 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:06:29.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:29.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:29.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:29.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:29.739 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:06:30.217 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:06:30.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:30.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:30.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:30.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:30.694 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:06:31.172 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:06:31.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:31.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:31.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:31.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:31.647 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:06:32.116 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:06:32.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:32.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:32.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:32.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:32.589 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:06:32.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:32.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:32.919 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:06:32.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:32.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:32.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:32.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:32.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:32.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:32.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:32.930 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:32.930 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:32.930 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:06:32.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:32.930 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:37.929 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:37.929 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:37.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:37.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:37.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:37.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:37.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:37.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:37.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:37.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:37.944 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:06:37.947 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:06:37.947 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:06:37.948 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:37.948 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:37.948 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:37.949 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:06:37.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:37.950 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:06:37.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:37.951 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:06:37.951 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:06:37.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:37.952 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:37.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:37.952 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:06:37.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:37.953 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:06:37.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:37.954 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:06:37.955 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:06:37.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:37.955 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:37.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:37.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:06:37.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:37.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:06:37.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:37.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:06:37.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.959 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:06:37.959 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:06:37.960 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:06:37.960 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:37.965 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:06:38.443 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:06:38.493 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:06:38.495 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:06:38.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:38.497 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:06:38.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:38.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:38.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:06:38.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:38.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:06:38.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:06:38.508 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:06:38.508 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:06:38.919 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:06:38.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:38.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:38.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:38.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:39.397 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:06:39.875 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:06:39.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:39.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:39.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:39.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:40.352 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:06:40.829 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:06:40.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:40.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:41.308 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:06:41.550 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:06:41.550 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:06:41.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:41.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:41.786 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:06:41.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:41.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:41.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:41.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:42.263 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:06:42.741 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:06:42.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:42.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:42.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:42.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:43.219 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:06:43.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:43.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:43.552 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:06:43.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:43.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:43.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:43.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:43.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:43.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:43.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:43.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:43.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:43.565 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:06:43.565 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:43.565 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:43.565 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:43.565 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:43.565 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:43.565 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:48.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:48.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:48.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:48.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:48.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:48.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:48.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:48.575 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:48.575 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:48.575 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:48.576 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:06:48.578 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:06:48.578 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:06:48.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:48.578 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:48.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:48.579 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:06:48.579 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:48.579 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:06:48.579 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:48.582 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:48.582 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:06:48.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:48.585 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:48.585 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:06:48.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:48.588 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:06:48.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:06:48.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:06:48.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:06:48.588 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:06:48.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.589 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:06:48.589 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:06:48.589 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:06:48.589 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:48.594 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:06:49.078 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:06:49.115 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:06:49.116 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:06:49.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:49.118 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:06:49.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:49.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:49.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:06:49.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:49.123 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:06:49.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:06:49.123 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:06:49.123 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:06:49.555 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:06:49.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:49.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:49.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:49.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:50.027 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:06:50.505 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:06:50.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:50.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:50.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:50.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:50.983 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:06:51.460 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:06:51.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:51.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:51.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:51.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:51.938 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:06:52.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:52.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:52.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:52.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:52.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:52.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:52.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:52.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:52.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:52.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:52.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:52.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:52.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:52.243 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:06:52.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=782 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:52.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=782 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:52.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=782 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:52.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=782 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:52.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=782 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:52.243 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=782 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:06:57.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:06:57.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:06:57.247 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:57.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:57.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:57.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:57.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:06:57.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:57.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:57.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:06:57.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:06:57.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:06:57.257 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:06:57.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:57.257 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:57.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:06:57.257 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:06:57.258 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:57.258 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:06:57.258 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:06:57.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:57.259 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:06:57.259 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:06:57.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:57.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:06:57.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:06:57.260 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:06:57.260 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:06:57.260 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:06:57.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:06:57.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:06:57.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:06:57.262 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:06:57.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:06:57.266 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:06:57.748 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:06:57.785 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:06:57.786 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:06:57.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:06:57.787 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:06:57.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:06:57.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:06:57.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:06:57.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:06:57.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:06:57.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:06:57.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:06:57.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:06:58.225 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:06:58.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:58.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:58.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:58.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:58.702 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:06:59.180 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:06:59.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:06:59.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:06:59.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:06:59.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:06:59.657 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:07:00.130 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:07:00.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:00.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:00.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:00.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:00.602 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:07:00.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:00.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:00.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:00.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:00.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:00.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:00.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:00.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:00.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:00.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:00.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:00.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:00.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:00.920 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:05.922 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:05.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:05.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:05.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:05.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:05.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:05.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:05.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:05.932 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:05.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:05.932 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:07:05.936 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:07:05.936 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:07:05.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:05.936 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:05.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:05.937 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:07:05.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:05.937 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:07:05.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:05.939 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:07:05.940 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:07:05.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:05.940 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:05.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:05.940 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:07:05.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:05.940 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:07:05.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:05.942 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:07:05.943 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:07:05.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:05.943 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:05.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:05.943 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:07:05.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:05.943 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:07:05.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:05.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:07:05.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:07:05.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:07:05.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:07:05.946 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:07:05.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:07:05.947 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:07:05.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:05.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:05.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:07:06.433 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:07:06.480 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:07:06.481 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:07:06.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:06.482 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:06.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:06.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:06.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:07:06.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:06.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:07:06.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:07:06.486 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:07:06.486 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:07:06.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:06.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:06.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:06.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:06.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:06.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:06.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:06.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:06.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:06.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:06.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:06.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:06.759 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:11.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:11.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:11.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:11.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:11.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:11.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:11.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:11.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:11.768 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:11.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:11.768 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:11.771 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:11.771 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:07:11.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:11.773 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:07:11.773 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:07:11.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:11.773 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:11.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:11.773 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:07:11.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:11.774 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:07:11.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:11.775 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:11.775 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:07:11.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:07:11.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:07:11.778 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:07:11.778 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:07:11.778 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:11.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:11.782 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:07:12.259 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:07:12.295 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:07:12.295 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:07:12.296 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:12.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:12.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:12.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:12.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:07:12.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:12.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:07:12.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:07:12.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:07:12.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:07:12.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:12.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:12.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:12.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:12.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:12.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:12.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:12.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:12.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:12.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:17.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:17.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:17.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:17.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:17.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:17.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:17.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:17.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:17.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:17.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:17.350 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:07:17.352 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:07:17.352 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:07:17.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:17.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:17.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:17.353 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:07:17.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:17.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:07:17.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:17.355 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:07:17.355 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:07:17.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:17.355 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:17.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:17.355 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:07:17.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:17.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:07:17.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:17.357 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:07:17.357 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:07:17.358 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:17.358 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:17.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:17.358 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:07:17.358 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:17.358 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:07:17.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:17.360 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:07:17.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:07:17.361 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:07:17.361 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:07:17.361 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:07:17.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:17.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:17.366 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:07:17.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:07:17.892 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:07:17.894 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:07:17.896 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:17.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:17.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:17.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:17.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:07:17.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:17.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:07:17.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:07:17.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:07:17.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:07:18.328 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:07:18.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:18.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:18.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:18.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:18.806 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:07:19.284 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:07:19.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:19.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:19.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:19.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:19.756 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:07:20.232 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:07:20.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:20.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:20.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:20.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:20.710 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:07:21.186 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:07:21.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:21.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:21.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:21.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:21.664 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:07:22.140 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:07:22.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:22.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:22.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:22.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:22.617 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:07:23.095 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:07:23.570 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:07:24.047 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:07:24.524 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:07:25.002 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:07:25.479 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:07:25.956 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:07:26.434 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:07:26.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:26.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:26.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:26.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:26.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:26.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:26.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:26.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:26.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:26.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:26.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:26.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:26.781 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:26.781 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2015 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:31.782 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:31.782 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:31.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:31.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:31.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:31.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:31.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:31.798 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:31.798 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:31.798 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:31.798 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:07:31.800 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:07:31.800 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:07:31.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:31.800 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:31.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:31.801 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:07:31.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:31.801 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:31.802 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:31.802 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:07:31.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:31.804 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:31.804 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:07:31.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:07:31.807 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:07:31.807 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:07:31.807 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:31.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:31.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:31.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:31.812 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:07:32.296 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:07:32.338 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:07:32.340 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:07:32.343 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:32.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:32.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:32.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:32.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:07:32.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:32.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:07:32.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:07:32.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:07:32.354 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:07:32.773 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:07:32.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:32.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:32.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:32.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:33.251 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:07:33.729 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:07:33.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:33.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:33.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:33.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:34.206 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:07:34.683 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:07:34.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:34.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:34.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:34.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:35.160 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:07:35.637 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:07:35.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:35.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:35.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:35.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:36.106 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:07:36.583 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:07:36.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:36.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:36.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:36.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:37.057 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:07:37.535 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:07:38.013 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:07:38.488 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:07:38.967 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:07:39.444 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:07:39.922 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:07:40.400 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:07:40.878 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:07:41.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:41.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:41.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:41.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:41.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:41.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:41.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:41.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:41.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:41.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:41.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:41.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:41.235 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:41.235 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:41.236 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:41.236 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:41.236 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:41.236 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:41.236 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:41.236 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:46.231 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:46.231 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:46.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:46.234 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:46.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:46.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:46.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:46.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:46.239 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:46.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:46.239 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:07:46.242 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:07:46.242 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:07:46.242 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:46.242 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:46.242 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:07:46.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:46.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:46.243 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:07:46.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:46.247 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:07:46.247 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:07:46.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:46.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:46.248 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:07:46.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:46.248 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:46.248 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:07:46.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:46.252 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:46.252 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:07:46.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:07:46.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:07:46.257 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:07:46.257 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:07:46.257 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:46.262 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:07:46.746 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:07:46.785 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:07:46.787 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:07:46.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:46.790 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:46.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:46.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:46.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:07:46.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:46.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:07:46.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:07:46.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:07:46.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:07:47.224 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:07:47.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:47.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:47.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:47.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:47.701 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:07:48.178 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:07:48.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:48.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:48.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:48.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:48.656 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:07:49.133 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:07:49.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:49.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:49.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:49.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:49.610 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:07:49.851 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:07:49.851 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-02 03:07:49.851 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:49.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:49.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:07:50.083 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:07:50.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:50.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:50.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:50.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:50.552 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:07:50.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:07:50.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:07:50.887 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:07:50.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:50.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:50.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:50.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:50.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:50.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:50.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:50.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:50.896 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:50.896 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:50.896 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:50.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:50.896 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=994 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:55.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:55.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:55.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:55.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:55.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:55.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:55.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:55.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:55.908 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:55.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:07:55.909 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:07:55.911 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:07:55.911 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:07:55.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:55.912 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:55.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:55.913 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:07:55.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:07:55.913 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:07:55.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:55.914 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:07:55.914 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:07:55.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:55.915 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:55.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:55.915 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:07:55.915 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:07:55.915 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:07:55.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:55.917 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:07:55.917 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:07:55.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:07:55.920 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:07:55.920 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:07:55.920 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:07:55.924 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:07:56.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:07:56.442 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:07:56.443 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:07:56.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:07:56.444 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:07:56.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:07:56.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:07:56.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:07:56.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:07:56.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:07:56.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:07:56.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:07:56.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:07:56.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:07:56.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:07:56.519 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:07:56.520 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:56.520 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:56.520 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:56.520 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:56.520 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:07:56.520 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:01.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:01.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:01.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:01.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:01.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:01.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:01.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:01.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:01.536 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:01.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:01.536 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:01.540 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:01.541 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:01.541 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:01.541 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:01.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:01.542 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:01.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:01.542 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:01.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:01.544 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:01.544 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:01.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:01.544 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:01.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:01.544 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:01.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:01.545 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:01.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:01.546 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:01.546 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:01.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:01.547 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:01.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:01.547 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:01.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:01.547 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:01.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.550 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:01.550 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:01.550 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:01.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:01.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:01.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:02.040 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:02.079 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:02.080 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:02.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:02.081 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:02.516 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:08:02.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:02.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:02.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:02.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:02.998 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:08:03.494 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:08:03.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:03.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:03.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:03.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:03.976 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:08:04.458 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:08:04.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:04.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:04.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:04.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:04.938 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:08:05.414 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:08:05.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:05.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:05.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:05.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:05.889 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:08:06.357 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:08:06.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:06.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:06.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:06.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:06.831 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:08:07.312 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:08:07.789 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:08:08.266 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:08:08.744 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:08:09.222 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:08:09.699 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:08:10.177 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:08:10.654 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:08:11.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:11.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:11.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:11.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:11.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:11.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:11.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:11.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:11.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:11.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:11.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:11.112 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:08:11.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2039 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:11.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2039 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:11.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2039 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:11.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2039 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:11.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2039 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:11.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2039 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:16.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:16.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:16.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:16.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:16.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:16.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:16.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:16.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:16.123 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:16.124 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:16.124 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:16.127 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:16.127 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:16.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:16.128 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:16.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:16.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:16.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:16.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:16.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:16.131 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:16.131 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:16.131 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:16.131 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:16.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:16.131 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:16.131 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:16.131 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:16.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:16.134 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:16.134 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:16.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:16.134 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:16.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:16.134 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:16.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:16.135 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:16.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.138 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:16.139 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:16.139 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:16.139 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:16.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:16.144 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:16.626 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:16.671 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:16.673 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:16.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:16.674 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:17.096 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:08:17.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:17.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:17.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:17.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:17.565 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:08:18.034 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:08:18.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:18.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:18.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:18.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:18.502 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:08:18.972 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:08:19.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:19.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:19.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:19.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:19.449 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:08:19.928 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:08:20.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:20.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:20.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:20.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:20.408 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:08:20.885 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:08:21.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:21.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:21.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:21.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:21.363 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:08:21.841 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:08:22.319 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:08:22.797 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:08:23.276 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:08:23.755 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:08:24.225 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:08:24.693 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:08:25.162 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:08:25.630 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:08:25.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:25.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:25.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:25.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:25.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:25.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:25.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:25.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:25.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:25.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:25.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:25.699 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:08:25.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2057 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:25.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2057 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:25.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2057 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:25.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2057 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:25.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2057 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:25.699 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2057 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:30.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:30.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:30.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:30.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:30.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:30.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:30.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:30.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:30.712 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:30.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:30.712 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:30.715 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:30.715 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:30.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:30.716 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:30.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:30.716 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:30.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:30.716 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:30.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:30.719 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:30.719 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:30.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:30.720 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:30.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:30.720 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:30.720 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:30.720 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:30.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:30.723 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:30.723 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:30.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:30.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:30.728 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:30.728 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:30.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:31.210 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:31.246 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:31.246 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:31.246 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:31.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:31.678 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:08:31.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:31.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:31.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:31.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:32.146 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:08:32.615 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:08:32.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:32.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:32.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:32.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:33.094 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:08:33.575 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:08:33.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:33.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:33.736 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:33.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:34.052 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:08:34.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:34.264 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:34.264 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:34.264 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:08:39.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:39.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:39.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:39.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:39.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:39.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:39.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:39.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:39.277 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:39.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:39.277 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:39.277 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:39.277 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:39.278 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:39.278 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:39.278 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:39.278 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:39.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:39.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:39.279 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:39.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:39.280 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:39.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:39.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:39.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:39.280 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:39.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:39.281 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:39.281 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:39.281 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:39.286 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:39.768 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:39.809 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:39.812 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:39.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:39.814 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:39.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:08:39.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:08:39.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:08:39.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:08:39.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:08:39.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:08:39.851 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:08:39.851 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:08:39.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:39.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:08:39.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:08:39.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:08:39.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:08:40.246 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:08:40.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:40.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:08:40.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:08:40.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:08:40.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:40.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:40.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:40.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:40.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:40.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:40.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:40.263 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:08:45.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:45.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:45.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:45.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:45.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:45.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:45.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:45.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:45.277 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:45.278 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:45.278 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:45.282 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:45.282 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:45.283 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:45.283 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:45.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:45.283 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:45.283 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:45.283 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:45.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:45.286 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:45.286 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:45.286 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:45.286 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:45.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:45.286 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:45.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:45.287 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:45.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:45.289 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:45.289 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:45.289 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:45.289 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:45.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:45.289 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:45.289 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:45.289 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:45.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:45.292 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.293 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:45.293 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:45.293 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:45.294 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:45.298 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:45.780 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:45.827 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:45.829 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:45.831 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:45.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:45.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:45.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:45.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:45.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:45.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:45.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:45.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:45.851 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:45.851 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:45.851 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:08:45.851 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:45.851 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.851 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.851 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.852 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:45.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:50.851 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:50.851 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:50.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:50.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:50.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:50.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:50.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:50.860 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:50.860 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:50.861 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:50.861 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:50.864 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:50.864 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:50.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:50.865 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:50.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:50.865 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:50.866 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:50.866 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:50.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:50.867 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:50.867 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:50.867 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:50.869 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:50.869 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:50.869 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:50.869 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:50.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:50.870 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:50.870 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:50.870 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:50.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:50.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:50.873 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:50.873 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:50.873 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:50.878 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:51.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:51.406 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:51.408 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:51.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:51.410 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:51.840 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:08:51.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:51.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:51.878 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:51.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:52.321 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:08:52.803 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:08:52.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:52.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:52.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:52.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:53.282 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:08:53.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:53.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:53.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:53.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:53.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:53.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:53.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:53.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:53.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:53.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:53.436 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:08:53.436 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.437 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.438 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.438 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:53.438 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=545 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:08:58.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:08:58.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:08:58.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:58.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:58.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:58.440 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:58.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:08:58.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:58.446 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:58.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:08:58.446 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:58.449 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:08:58.449 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:08:58.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:58.451 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:08:58.452 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:08:58.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:58.452 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:58.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:08:58.452 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:08:58.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:08:58.452 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:08:58.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:58.454 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:08:58.454 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:08:58.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:08:58.458 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:08:58.458 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:08:58.458 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:08:58.463 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:08:58.945 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:08:58.988 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:08:58.991 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:08:58.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:08:58.993 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:08:58.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:08:58.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:08:58.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:08:58.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:08:58.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:08:58.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:08:58.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:08:58.997 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:08:59.422 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:08:59.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:08:59.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:08:59.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:08:59.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:08:59.899 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:00.376 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:00.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:00.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:00.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:00.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:00.853 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:01.330 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:09:01.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:01.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:01.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:01.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:01.807 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:09:01.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:01.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:01.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:01.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:01.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:01.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:01.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:01.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:01.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:01.834 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:01.834 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:01.834 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:01.834 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:06.834 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:06.834 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:06.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:06.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:06.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:06.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:06.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:06.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:06.845 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:06.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:06.845 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:06.847 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:06.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:06.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:06.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:06.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:06.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:06.850 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:06.850 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:06.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:06.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:06.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:06.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:06.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:06.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:06.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:06.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:06.852 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:06.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:06.853 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:06.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:06.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:06.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:06.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:06.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:06.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:06.854 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:06.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:06.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:06.857 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:06.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:06.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:07.334 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:07.383 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:07.384 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:07.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:07.387 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:07.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:07.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:07.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:09:07.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:09:07.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:09:07.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:09:07.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:09:07.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:09:07.811 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:07.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:07.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:07.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:07.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:08.288 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:08.763 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:08.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:08.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:08.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:08.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:09.241 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:09.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:09.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:09.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:09.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:09.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:09.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:09.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:09.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:09.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:09.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:09.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:09.494 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:09.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:14.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:14.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:14.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:14.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:14.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:14.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:14.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:14.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:14.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:14.514 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:14.514 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:14.515 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:14.516 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:14.516 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:14.516 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:14.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:14.516 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:14.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:14.517 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:14.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:14.517 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:14.518 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:14.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:14.518 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:14.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:14.518 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:14.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:14.518 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:14.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:14.519 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:14.519 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:14.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:14.521 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:14.521 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:14.521 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:14.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:14.526 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:15.009 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:15.047 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:15.049 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:15.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:15.051 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:15.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:15.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:15.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:09:15.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:09:15.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:09:15.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:09:15.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:09:15.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:09:15.487 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:15.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:15.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:15.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:15.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:15.964 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:16.441 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:16.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:16.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:16.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:16.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:16.917 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:17.393 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:09:17.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:17.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:17.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:17.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:17.871 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:09:17.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:17.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:17.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:17.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:17.893 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:22.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:22.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:22.894 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:22.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:22.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:22.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:22.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:22.898 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:22.898 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:22.898 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:22.898 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:22.899 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:22.899 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:22.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:22.900 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:22.900 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:22.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:22.901 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:22.901 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:22.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:22.903 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:22.903 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:22.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:22.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:22.908 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:23.376 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:23.428 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:23.430 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:23.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:23.433 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:23.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:23.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:23.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:09:23.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:09:23.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:09:23.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:09:23.444 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:09:23.444 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:09:23.853 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:23.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:23.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:23.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:23.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:24.330 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:24.808 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:24.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:24.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:24.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:24.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:25.285 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:25.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:25.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:25.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:25.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:25.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:25.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:25.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:25.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:25.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:25.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:25.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:25.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:25.551 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:25.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.552 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.552 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.552 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.552 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:25.552 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:30.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:30.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:30.555 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:30.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:30.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:30.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:30.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:30.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:30.566 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:30.567 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:30.567 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:30.569 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:30.569 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:30.569 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:30.569 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:30.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:30.570 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:30.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:30.570 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:30.571 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:30.571 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:30.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:30.573 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:30.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:30.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:30.576 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:30.576 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:30.576 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:30.581 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:31.063 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:31.101 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:31.102 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:31.102 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:31.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:31.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:31.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:31.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:09:31.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:09:31.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:09:31.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:09:31.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:09:31.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:09:31.540 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:31.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:31.579 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:31.579 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:31.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:32.016 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:32.493 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:32.579 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:32.579 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:32.579 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:32.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:32.970 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:33.447 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:09:33.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:33.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:33.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:33.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:33.925 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:09:34.402 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:09:34.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:34.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:34.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:34.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:34.880 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:09:34.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:34.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:34.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:34.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:34.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:34.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:34.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:34.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:34.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:34.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:34.909 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:34.909 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:34.909 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:34.909 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:39.909 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:39.909 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:39.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:39.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:39.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:39.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:39.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:39.925 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:39.925 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:39.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:39.926 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:39.931 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:39.931 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:39.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:39.932 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:39.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:39.932 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:39.933 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:39.933 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:39.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:39.934 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:39.934 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:39.934 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:39.934 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:39.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:39.935 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:39.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:39.935 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:39.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:39.937 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:39.937 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:39.937 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:39.937 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:39.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:39.938 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:39.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:39.938 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:39.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.941 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:39.941 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:39.942 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:39.942 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:39.947 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:40.430 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:40.478 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:40.480 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:40.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:40.483 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:40.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:40.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:40.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:09:40.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:09:40.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:09:40.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:09:40.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:09:40.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:09:40.908 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:40.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:40.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:40.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:40.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:41.386 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:41.863 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:41.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:41.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:41.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:41.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:42.341 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:42.811 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:09:42.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:42.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:42.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:42.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:43.284 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:09:43.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:43.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:43.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:43.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:43.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:43.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:43.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:43.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:43.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:43.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:43.550 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:43.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:43.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:43.550 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:43.550 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:43.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:43.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:43.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:43.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:43.551 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:48.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:48.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:48.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:48.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:48.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:48.553 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:48.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:48.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:48.563 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:48.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:48.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:48.566 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:48.567 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:48.567 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:48.567 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:48.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:48.567 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:48.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:48.568 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:48.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:48.570 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:48.570 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:48.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:48.570 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:48.570 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:48.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:48.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:48.570 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:48.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:48.573 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:48.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:48.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.576 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:48.576 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:48.576 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:48.576 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:48.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:48.581 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:49.064 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:49.103 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:49.105 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:49.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:49.108 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:49.542 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:49.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:49.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:49.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:49.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:50.023 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:50.494 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:50.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:50.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:50.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:50.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:50.964 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:51.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:51.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:51.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:51.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:51.127 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:51.127 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:51.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:51.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:51.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:51.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:51.128 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:09:51.128 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:51.128 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:51.128 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:51.129 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:51.129 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:51.129 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:51.129 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=548 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:09:56.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:56.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:56.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:56.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:56.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:56.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:56.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:56.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:56.130 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:56.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:09:56.130 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:56.131 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:09:56.131 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:09:56.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:56.132 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:09:56.133 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:09:56.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:56.133 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:56.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:56.133 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:09:56.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:09:56.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:09:56.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:56.134 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:09:56.134 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:09:56.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:09:56.137 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:09:56.137 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:09:56.137 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.142 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:09:56.619 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:09:56.666 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:09:56.669 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:09:56.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:56.671 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:09:56.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:09:56.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:09:56.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:09:56.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:09:56.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:57.089 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:09:57.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:57.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:57.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:57.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:57.564 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:09:58.036 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:09:58.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:58.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:58.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:58.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:58.504 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:09:58.971 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:09:59.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:59.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:59.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:59.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:59.439 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:09:59.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:09:59.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:09:59.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:09:59.703 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:04.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:04.703 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:04.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:04.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:04.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:04.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:04.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:04.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:04.708 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:04.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:04.708 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:04.708 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:04.709 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:04.709 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:04.709 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:04.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:04.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:04.710 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:04.710 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:04.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:04.712 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:04.712 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:04.712 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:04.717 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:05.193 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:05.225 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:05.225 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:05.225 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:05.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:05.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:10:05.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:10:05.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:10:05.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:05.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:05.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:05.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:05.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:05.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:05.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:05.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:05.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:05.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:05.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:05.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:05.240 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:05.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:05.240 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:10.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:10.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:10.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:10.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:10.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:10.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:10.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:10.260 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:10.260 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:10.260 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:10.260 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:10.262 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:10.262 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:10.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:10.264 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:10.264 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:10.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:10.266 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:10.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:10.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.268 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:10.268 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:10.268 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:10.269 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.273 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:10.752 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:10.798 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:10.801 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:10.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:10.803 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:10.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:10:10.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:10:10.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:10:10.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:10.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:11.223 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:10:11.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:11.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:11.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:11.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:11.699 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:10:12.175 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:10:12.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:12.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:12.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:12.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:12.652 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:10:13.125 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:10:13.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:13.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:13.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:13.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:13.593 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:10:13.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:13.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:13.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:13.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:13.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:13.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:13.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:13.853 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:13.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:13.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:13.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:13.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:13.853 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:13.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:13.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:13.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:13.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:13.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:13.853 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:13.854 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:18.854 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:18.854 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:18.855 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:18.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:18.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:18.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:18.873 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:18.874 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:18.875 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:18.875 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:18.875 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:18.877 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:18.878 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:18.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:18.878 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:18.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:18.879 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:18.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:18.880 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:18.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:18.880 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:18.881 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:18.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:18.881 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:18.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:18.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:18.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:18.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:18.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:18.883 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:18.883 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:18.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:18.883 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:18.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:18.883 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:18.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:18.884 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:18.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:18.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:18.887 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:18.887 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:18.887 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:18.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:19.369 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:19.417 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:19.417 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:19.418 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:19.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:19.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:10:19.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:10:19.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:10:19.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:19.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:19.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:19.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:19.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:19.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:19.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:19.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:19.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:19.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:19.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:19.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:19.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:19.465 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:19.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:19.465 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.465 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.465 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.465 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.466 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.466 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.466 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:19.466 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:24.464 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:24.464 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:24.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:24.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:24.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:24.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:24.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:24.480 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:24.480 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:24.481 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:24.481 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:24.487 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:24.487 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:24.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:24.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:24.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:24.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:24.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:24.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:24.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:24.492 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:24.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:24.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:24.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:24.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:24.493 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:24.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:24.494 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:24.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:24.497 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:24.497 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:24.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:24.497 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:24.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:24.497 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:24.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:24.498 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:24.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:24.501 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:24.501 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:24.501 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:24.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:24.506 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:24.989 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:25.030 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:25.032 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:25.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:25.035 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:25.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:25.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:25.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:25.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:25.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:25.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:25.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:25.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:25.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:25.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:25.048 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:25.048 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:25.048 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:25.048 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:25.048 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:25.048 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:25.048 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:25.049 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:30.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:30.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:30.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:30.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:30.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:30.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:30.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:30.060 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:30.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:30.061 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:30.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:30.063 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:30.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:30.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:30.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:30.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:30.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:30.065 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:30.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:30.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:30.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:30.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:30.067 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:30.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:30.067 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:30.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:30.067 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:30.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:30.069 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:30.069 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:30.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:30.069 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:30.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:30.069 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:30.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:30.069 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:30.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:30.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:30.073 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:30.073 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:30.073 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:30.078 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:30.559 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:30.604 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:30.606 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:30.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:30.609 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:30.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:30.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:30.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:30.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:30.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:30.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:30.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:30.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:30.626 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:30.626 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:30.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:30.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.626 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:30.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:35.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:35.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:35.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:35.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:35.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:35.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:35.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:35.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:35.636 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:35.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:35.637 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:35.639 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:35.639 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:35.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:35.639 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:35.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:35.640 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:35.640 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:35.640 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:35.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:35.641 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:35.641 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:35.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:35.643 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:35.643 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:35.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:35.645 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:35.646 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:35.646 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:35.646 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:35.651 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:36.136 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:36.172 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:36.174 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:36.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:36.176 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:36.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:36.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:36.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:36.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:36.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:36.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:36.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:36.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:36.185 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:36.185 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:36.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:41.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:41.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:41.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:41.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:41.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:41.193 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:41.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:41.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:41.198 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:41.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:41.198 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:41.201 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:41.202 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:41.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:41.202 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:41.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:41.203 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:41.203 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:41.203 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:41.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:41.204 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:41.204 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:41.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:41.204 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:41.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:41.205 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:41.205 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:41.205 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:41.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:41.206 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:41.206 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:41.206 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:41.206 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:41.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:41.206 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:41.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:41.207 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:41.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.209 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:41.209 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:41.210 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:41.210 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:41.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:41.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:41.214 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:41.699 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:41.742 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:41.744 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:41.746 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:41.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:41.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:41.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:41.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:41.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:41.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:41.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:41.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:41.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:41.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:41.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:41.763 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.763 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:41.764 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:46.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:46.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:46.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:46.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:46.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:46.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:46.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:46.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:46.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:46.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:46.773 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:46.775 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:46.775 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:46.775 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:46.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:46.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:46.776 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:46.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:46.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:46.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:46.777 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:46.777 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:46.777 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:46.777 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:46.778 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:46.778 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:46.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:46.778 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:46.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:46.779 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:46.779 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:46.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:46.780 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:46.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:46.780 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:46.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:46.780 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:46.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:46.783 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:46.783 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:46.783 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:46.788 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:47.270 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:47.309 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:47.311 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:47.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:47.313 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:47.739 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:10:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:47.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:47.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:47.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:48.208 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:10:48.682 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:10:48.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:48.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:48.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:48.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:49.159 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:10:49.640 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:10:49.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:49.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:49.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:49.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:50.118 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:10:50.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:10:50.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:10:50.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:10:50.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:10:50.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:10:50.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:10:50.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:10:50.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:10:50.595 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:10:50.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:50.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:50.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:50.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:51.074 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:10:51.552 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:10:51.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:51.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:51.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:51.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:52.030 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:10:52.508 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:10:52.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:10:52.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:10:52.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:52.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:52.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:52.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:52.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:52.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:52.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:52.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:52.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:52.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:52.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:52.639 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:52.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1254 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:52.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1254 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:52.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:52.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:57.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:57.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:57.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:57.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:57.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:57.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:57.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:57.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:57.654 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:57.655 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:10:57.655 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:10:57.658 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:10:57.658 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:10:57.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:57.658 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:57.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:57.659 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:10:57.659 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:10:57.659 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:10:57.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:57.660 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:10:57.661 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:10:57.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:57.661 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:57.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:57.661 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:10:57.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:10:57.661 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:10:57.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:57.662 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:10:57.663 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:10:57.663 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:57.663 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:10:57.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:57.663 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:10:57.663 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:10:57.663 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:10:57.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:57.665 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:10:57.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:10:57.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:10:57.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:10:57.665 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:10:57.666 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:10:57.666 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:10:57.666 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:10:57.671 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:10:58.152 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:10:58.201 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:10:58.203 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:10:58.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:10:58.205 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:10:58.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:10:58.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:10:58.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:10:58.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:10:58.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:10:58.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:10:58.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:10:58.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:10:58.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:10:58.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:10:58.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:10:58.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:10:58.244 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:10:58.244 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:10:58.244 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:58.244 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:58.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:58.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:58.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:10:58.245 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:03.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:03.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:03.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:03.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:03.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:03.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:03.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:03.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:03.250 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:03.251 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:03.251 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:03.253 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:03.253 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:03.253 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:03.253 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:03.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:03.254 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:03.254 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:03.254 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:03.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:03.256 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:03.256 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:03.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:03.256 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:03.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:03.257 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:03.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:03.257 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:03.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:03.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:03.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:03.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:03.262 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:03.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:03.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.263 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:03.263 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:03.263 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:03.263 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:03.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.268 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:03.752 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:03.780 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:03.781 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:03.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:03.781 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:03.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:03.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:03.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:03.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:03.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:03.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:03.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:03.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:03.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:03.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:03.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:03.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:03.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:03.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:03.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:03.796 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:08.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:08.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:08.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:08.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:08.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:08.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:08.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:08.810 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:08.810 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:08.810 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:08.810 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:08.812 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:08.812 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:08.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:08.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:08.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:08.814 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:08.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:08.814 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:08.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:08.816 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:08.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:08.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:08.816 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:08.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:08.817 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:08.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:08.817 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:08.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:08.819 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:08.819 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:08.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:08.819 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:08.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:08.820 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:08.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:08.820 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:08.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:08.825 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:08.825 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:08.825 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:08.830 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:09.311 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:09.356 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:09.357 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:09.358 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:09.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:09.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:09.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:09.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:09.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:09.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:09.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:09.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:09.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:09.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:09.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:09.401 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:09.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:09.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:09.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:09.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:09.402 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:14.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:14.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:14.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:14.409 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:14.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:14.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:14.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:14.419 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:14.419 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:14.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:14.420 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:14.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:14.424 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:14.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:14.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:14.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:14.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:14.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:14.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:14.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:14.428 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:14.428 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:14.428 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:14.428 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:14.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:14.429 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:14.429 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:14.430 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:14.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:14.431 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:14.431 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:14.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:14.434 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.435 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:14.435 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:14.435 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:14.436 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.440 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:14.924 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:14.965 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:14.967 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:14.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:14.969 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:14.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:14.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:14.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:15.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:15.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:15.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:15.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:15.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:15.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:15.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:15.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:15.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:15.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:15.011 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:15.011 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:20.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:20.012 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:20.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:20.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:20.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:20.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:20.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:20.023 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:20.023 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:20.024 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:20.024 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:20.027 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:20.027 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:20.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:20.028 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:20.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:20.028 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:20.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:20.028 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:20.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:20.031 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:20.031 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:20.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:20.033 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:20.033 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:20.033 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:20.033 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:20.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:20.034 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:20.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:20.034 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:20.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:20.036 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:20.037 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:20.037 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:20.037 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:20.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:20.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:20.042 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:20.524 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:20.569 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:20.571 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:20.573 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:20.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:20.575 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 03:11:20.575 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 200
2026-03-02 03:11:20.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 03:11:20.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:21.002 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:11:21.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:21.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:21.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:21.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:21.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:21.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:21.480 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:11:21.958 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:11:22.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:22.217 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 03:11:22.217 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 0
2026-03-02 03:11:22.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 03:11:22.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:22.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:22.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:22.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:22.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:22.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:22.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:22.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:22.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:22.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:22.226 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:22.226 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:22.226 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:22.226 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:22.226 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:22.226 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=468 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:22.226 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=468 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:22.226 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=468 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:22.226 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=468 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:22.226 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=468 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:22.226 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=468 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:27.229 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:27.229 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:27.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:27.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:27.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:27.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:27.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:27.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:27.241 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:27.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:27.242 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:27.247 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:27.247 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:27.248 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:27.248 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:27.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:27.249 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:27.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:27.249 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:27.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:27.251 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:27.251 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:27.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:27.252 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:27.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:27.252 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:27.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:27.252 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:27.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:27.254 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:27.254 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:27.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:27.257 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.258 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:27.258 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:27.258 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:27.259 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:27.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:27.263 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:27.747 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:27.789 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:27.791 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:27.793 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:27.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:27.795 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 03:11:27.795 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 200
2026-03-02 03:11:27.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 03:11:28.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:28.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:28.224 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:11:28.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:28.423 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:28.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:28.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:28.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:28.704 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:11:28.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.182 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:11:29.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.427 [DEBUG] fake_trx.py:382 (BTS@172.18.40.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-02 03:11:29.427 [INFO] fake_trx.py:385 (BTS@172.18.40.20:5700) Artificial TRXC delay set to 0
2026-03-02 03:11:29.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-02 03:11:29.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:29.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:29.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:29.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:29.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:29.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:29.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:29.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:29.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:29.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:29.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:29.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:29.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:29.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:29.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:29.436 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:34.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:34.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:34.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:34.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:34.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:34.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:34.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:34.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:34.449 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:34.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:34.449 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:34.454 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:34.454 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:34.454 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:34.454 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:34.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:34.455 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:34.455 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:34.455 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:34.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:34.458 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:34.458 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:34.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:34.458 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:34.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:34.459 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:34.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:34.459 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:34.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:34.461 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:34.461 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:34.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:34.462 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:34.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:34.462 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:34.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:34.462 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:34.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:34.465 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:34.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:34.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:34.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:34.465 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:34.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:34.466 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:34.466 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:34.466 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:34.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:34.471 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:34.953 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:35.001 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:35.005 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:35.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:35.008 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:35.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:35.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:35.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:35.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:35.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:35.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:35.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:35.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:35.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:35.045 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:35.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:35.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:35.045 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:35.045 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:35.046 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:35.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:35.046 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.046 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:40.046 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:40.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:40.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:40.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:40.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:40.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:40.067 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:40.067 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:40.068 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:40.068 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:40.071 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:40.071 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:40.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:40.071 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:40.071 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:40.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:40.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:40.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:40.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:40.074 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:40.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:40.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:40.076 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:40.076 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:40.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:40.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:40.076 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:40.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:40.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:40.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:40.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:40.080 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:40.080 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:40.080 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:40.084 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:40.569 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:40.605 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:40.607 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:40.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:40.610 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:40.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:40.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:40.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:40.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:40.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:40.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:40.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:40.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:40.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:40.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:40.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:40.663 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:40.663 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:40.663 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:11:40.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:40.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:40.663 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:11:45.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:11:45.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:11:45.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:45.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:45.666 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:45.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:45.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:11:45.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:45.680 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:45.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:11:45.680 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:11:45.684 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:11:45.684 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:11:45.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:45.685 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:45.685 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:11:45.685 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:11:45.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:11:45.686 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:11:45.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:45.686 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:11:45.687 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:11:45.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:45.687 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:45.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:11:45.687 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:11:45.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:11:45.687 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:11:45.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:45.689 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:11:45.689 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:11:45.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:11:45.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:11:45.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:11:45.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:11:45.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:11:45.697 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:11:46.171 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:11:46.207 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:11:46.208 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:11:46.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:46.208 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:11:46.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:46.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:46.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:46.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:46.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:46.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:46.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:46.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:46.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:46.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:46.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:46.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:46.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:46.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:46.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:46.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:46.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:46.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:46.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:46.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:46.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:46.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:46.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:46.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:46.639 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:11:46.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:46.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:46.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:46.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:47.113 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:11:47.591 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:11:47.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:47.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:47.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:47.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:48.068 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:11:48.546 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:11:48.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:48.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:48.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:48.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:49.022 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:11:49.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:49.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:49.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:49.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:49.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:49.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:49.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:49.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:49.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:49.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:49.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:49.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:49.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:49.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:49.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:49.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:49.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:49.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:49.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:49.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:49.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:49.462 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:49.462 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:49.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:49.499 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:11:49.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:49.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:49.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:49.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:49.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:49.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:49.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:49.976 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:11:50.454 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:11:50.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:11:50.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:11:50.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:11:50.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:11:50.932 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:11:51.410 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:11:51.888 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:11:52.366 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:11:52.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:52.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:52.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:52.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:52.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:52.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:52.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:52.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:52.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:52.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:52.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:52.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:52.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:52.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:52.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:52.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:52.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:52.842 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:11:53.320 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:11:53.797 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:11:54.273 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:11:54.751 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:11:55.228 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:11:55.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:55.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:55.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:55.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:55.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:55.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:55.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:55.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:55.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:55.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:55.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:55.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:55.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:55.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:55.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:55.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:55.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:55.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:55.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:55.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:55.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:55.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:55.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:55.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:55.705 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:11:55.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:55.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:55.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:55.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.182 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:11:56.660 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:11:56.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:56.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:56.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:56.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:56.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:56.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:56.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:56.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:56.885 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:56.885 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:56.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:56.894 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:11:56.894 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:11:56.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:56.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:56.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:56.967 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:11:56.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:11:56.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:11:56.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:11:56.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:56.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:11:56.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:11:56.987 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:11:56.987 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:11:57.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:11:57.044 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:11:57.045 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:11:57.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:57.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:11:57.133 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:11:57.603 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:11:58.073 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:11:58.544 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:11:59.020 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:11:59.499 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:11:59.970 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:12:00.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:00.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:00.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:00.051 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:00.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:00.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:00.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:00.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:00.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:00.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:00.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:00.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:00.117 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:00.117 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:00.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:00.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:00.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:00.179 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:00.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:00.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:00.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:00.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:00.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:00.200 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:00.200 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:00.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:00.255 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:00.255 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:00.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:00.443 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:12:00.917 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:12:01.386 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:12:01.855 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:12:02.329 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:12:02.807 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:12:03.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:03.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:03.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:03.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:03.263 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:03.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:03.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:03.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:03.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:03.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:03.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:03.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:03.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:03.286 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:12:03.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:03.342 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:03.342 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:03.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:03.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:03.764 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:12:04.243 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:12:04.720 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:12:05.199 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:12:05.672 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:12:06.141 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:12:06.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:06.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:06.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:06.350 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:06.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:06.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:06.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:06.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:06.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:06.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:06.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:06.374 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:06.374 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:06.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:06.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:06.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:06.469 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:06.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:06.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:06.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:06.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:06.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:06.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:06.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:06.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:06.523 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:06.523 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:06.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:06.611 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:12:07.089 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:12:07.561 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:12:07.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:07.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:07.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:07.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:07.743 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:07.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:07.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:07.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:07.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:07.762 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:07.762 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:07.762 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:07.762 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:07.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:07.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:07.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:07.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:07.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:08.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:08.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:08.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:08.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:08.037 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:12:08.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:08.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:08.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:08.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:08.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:08.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:08.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:08.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:08.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:08.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:08.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:08.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:08.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:08.510 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:12:08.988 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:12:09.466 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:12:09.944 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:12:10.421 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:12:10.898 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:12:11.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:11.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:11.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:11.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:11.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:11.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:11.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:11.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:11.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:11.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:11.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:11.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:11.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:11.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:11.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:11.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:11.372 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:12:11.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:11.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:11.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:11.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:11.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:11.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:11.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:11.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:11.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:11.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:11.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:11.849 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:12:12.326 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:12:12.804 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:12:13.282 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:12:13.760 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:12:14.238 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:12:14.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:14.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:14.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:14.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:14.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:14.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:14.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:14.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:14.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:14.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:14.451 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:14.451 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:14.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:14.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:14.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:14.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:14.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:14.715 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:12:15.188 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:12:15.663 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:12:16.140 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:12:16.617 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:12:17.093 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:12:17.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:17.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:17.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:17.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:17.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:17.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:17.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:17.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:17.509 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:17.509 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:17.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:17.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:17.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:17.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:17.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:17.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:17.568 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:12:17.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:17.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:17.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:17.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:17.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:17.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:17.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:17.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:17.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:17.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:17.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:17.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.045 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:12:18.522 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:12:18.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:18.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:18.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:18.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:18.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:18.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:18.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:18.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:18.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:18.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:18.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:18.624 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:18.625 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:18.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:18.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:18.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:18.681 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:18.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:18.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:18.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:18.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:18.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:18.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:18.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:18.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:18.706 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:18.706 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:18.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:18.997 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:12:19.475 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:12:19.953 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:12:20.430 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:12:20.908 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:12:21.385 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:12:21.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:21.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:21.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:21.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:21.714 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:21.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:21.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:21.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:21.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:21.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:21.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:21.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:21.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:21.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:21.758 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:21.758 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:21.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:21.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:21.860 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:12:22.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:22.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:22.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:22.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:22.241 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:22.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:22.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:22.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:22.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:22.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:22.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:22.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:22.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:22.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:22.275 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:22.276 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:22.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:22.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:22.330 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:12:22.808 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 03:12:23.284 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 03:12:23.758 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 03:12:24.236 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 03:12:24.714 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 03:12:25.192 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 03:12:25.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:25.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:25.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:25.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:25.282 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:25.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:25.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:25.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:25.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:25.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:25.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:25.304 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:25.304 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:25.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:25.340 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:25.340 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:25.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:25.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:25.670 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 03:12:26.148 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 03:12:26.626 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 03:12:27.105 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 03:12:27.583 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 03:12:28.061 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 03:12:28.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:28.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:28.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:28.348 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:28.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:28.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:28.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:28.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:28.364 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:28.364 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:28.364 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:28.392 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:28.392 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:28.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:28.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:28.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:28.456 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:28.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:28.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:28.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:28.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:28.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:28.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:28.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:28.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:28.480 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:28.480 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:28.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:28.538 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 03:12:29.016 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 03:12:29.493 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 03:12:29.971 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 03:12:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:30.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:30.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:30.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:30.432 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:30.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:30.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:30.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:30.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:30.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:30.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:30.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:30.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:30.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:30.446 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:30.447 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9590 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:30.447 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9591 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:35.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:35.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:35.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:35.449 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:35.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:35.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:35.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:35.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:35.457 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:35.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:35.457 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:12:35.460 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:12:35.460 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:12:35.461 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:35.461 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:35.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:35.462 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:12:35.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:35.462 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:12:35.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:35.465 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:12:35.465 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:12:35.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:35.465 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:35.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:35.465 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:12:35.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:35.466 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:12:35.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:35.468 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:35.468 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:12:35.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:12:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:12:35.472 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:12:35.472 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:12:35.472 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:12:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:35.477 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:12:35.959 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:12:35.991 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:12:35.991 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:12:35.992 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:12:35.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:35.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:35.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:35.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:36.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:36.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:36.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:36.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:36.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:36.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:36.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:36.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:36.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:36.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:36.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:36.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.100 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:36.100 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:36.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.198 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:36.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:36.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:36.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:36.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:36.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:36.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:36.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:36.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:36.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:36.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:36.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:36.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:36.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.377 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:36.377 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:36.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.428 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:12:36.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:36.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:36.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:36.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:36.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:36.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:36.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:36.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:36.510 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:36.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:36.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:36.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:36.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:36.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:36.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:36.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:36.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:36.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:36.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:36.521 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:36.521 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=226 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:41.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:41.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:41.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:41.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:41.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:41.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:41.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:41.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:41.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:41.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:41.524 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:41.525 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:41.525 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:12:41.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:41.526 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:12:41.526 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:12:41.526 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:41.526 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:41.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:41.527 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:12:41.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:41.527 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:12:41.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:41.528 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:41.528 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:12:41.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:12:41.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:12:41.530 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:12:41.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:41.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:41.535 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:12:42.011 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:12:42.053 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:12:42.054 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:12:42.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:42.056 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:12:42.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:42.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:42.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:42.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:42.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:42.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:42.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:42.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:42.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:42.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:42.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:42.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:42.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:42.487 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:12:42.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:42.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:42.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:42.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:42.965 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:12:42.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:42.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:42.988 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:42.988 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:43.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:43.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:43.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:43.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:43.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:43.003 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:43.003 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:43.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:43.010 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:43.010 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:43.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.434 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:12:43.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:43.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:43.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:43.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:43.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:43.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:43.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:43.703 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:43.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:43.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:43.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:43.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:43.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:43.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:43.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:43.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:43.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:43.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:43.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:43.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:43.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:43.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:43.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:43.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:43.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:43.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:43.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:43.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:43.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:43.902 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:43.902 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:43.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:43.903 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:12:44.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:44.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:44.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:44.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:44.301 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:44.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:44.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:44.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:44.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:44.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:44.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:44.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:44.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:44.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:44.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:44.313 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:12:44.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.313 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:44.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:49.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:49.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:49.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:49.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:49.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:49.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:49.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:49.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:49.326 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:49.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:49.327 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:12:49.331 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:12:49.331 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:12:49.332 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:49.332 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:49.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:49.333 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:12:49.333 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:49.333 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:12:49.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:49.334 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:12:49.334 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:12:49.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:49.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:49.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:49.335 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:12:49.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:49.335 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:12:49.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:49.336 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:12:49.336 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:12:49.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:49.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:49.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:49.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:12:49.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:49.337 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:12:49.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.340 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:12:49.340 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:12:49.340 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:12:49.340 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:49.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:12:49.828 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:12:49.873 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:12:49.876 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:12:49.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:49.878 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:12:49.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:49.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:49.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:49.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:49.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:49.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:49.897 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:49.897 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:49.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:49.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:49.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:49.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:49.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:50.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:50.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:50.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:50.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:50.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:50.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:50.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:50.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:50.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:50.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:50.166 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:50.166 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:50.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.304 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:12:50.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:50.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:50.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:50.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:50.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:50.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:50.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:50.451 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:50.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:50.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:50.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:50.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:50.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:50.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:50.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:50.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:50.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:50.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:50.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:50.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:50.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:50.780 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:12:50.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:50.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:50.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:50.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:50.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:50.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:50.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:50.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:50.838 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:50.838 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:50.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:50.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:51.257 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:12:51.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:51.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:51.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:51.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:51.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:51.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:51.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:51.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:51.650 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:51.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:51.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:51.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:51.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:51.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:51.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:51.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:51.663 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:51.663 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:51.663 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:12:51.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:51.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:51.665 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:56.663 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:56.663 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:56.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:56.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:56.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:56.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:56.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:56.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:56.677 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:56.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:12:56.677 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:12:56.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:12:56.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:12:56.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:56.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:56.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:56.683 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:12:56.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:12:56.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:12:56.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:56.685 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:12:56.685 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:12:56.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:56.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:56.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:56.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:12:56.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:12:56.685 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:12:56.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:56.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:12:56.688 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:12:56.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:56.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:12:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:12:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:12:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:12:56.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:12:56.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:12:56.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:12:56.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:12:56.697 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:12:57.176 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:12:57.224 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:12:57.226 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:12:57.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:57.229 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:12:57.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:57.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:57.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:57.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:57.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:57.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:57.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:57.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:57.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:57.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:57.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:57.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:57.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:57.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:57.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:57.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:57.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:57.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:57.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:57.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:57.514 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:57.514 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:12:57.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.651 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:12:57.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:57.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:57.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:57.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:57.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:57.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:57.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:57.788 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:57.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:57.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:57.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:57.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:57.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:57.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:57.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:57.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:57.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:57.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:57.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:57.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:58.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:58.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:58.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:58.120 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:12:58.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:58.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:58.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:12:58.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:58.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:12:58.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:12:58.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:12:58.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:12:58.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:58.169 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:12:58.169 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:12:58.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:58.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:58.594 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:12:58.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:58.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:58.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:58.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:58.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:12:58.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:12:58.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:12:58.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:12:58.987 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:12:58.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:12:58.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:12:58.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:12:58.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:12:59.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:12:59.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:12:59.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:12:59.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:12:59.001 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:12:59.001 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:12:59.001 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:12:59.002 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:59.002 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:59.002 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:59.002 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:59.002 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:12:59.002 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:13:04.003 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:13:04.003 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:13:04.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:13:04.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:13:04.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:13:04.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:13:04.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:13:04.015 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:13:04.015 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:04.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:13:04.016 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:13:04.017 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:13:04.018 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:13:04.018 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:13:04.018 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:04.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:13:04.018 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:13:04.018 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:13:04.018 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:13:04.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:13:04.020 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:13:04.020 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:13:04.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:13:04.022 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:13:04.022 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:13:04.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.024 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:13:04.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:13:04.024 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:13:04.025 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:04.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:13:04.512 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:13:04.546 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:13:04.547 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:13:04.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:04.548 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:13:04.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:04.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:04.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:04.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:04.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:04.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:04.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:04.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:04.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:04.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:04.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:04.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:04.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:04.989 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:13:05.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:05.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:05.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:05.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:05.466 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:13:05.942 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:13:06.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:06.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:06.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:06.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:06.420 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:13:06.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:06.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:06.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:06.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:06.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:06.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:06.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:06.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:06.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:06.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:06.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:06.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:06.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:06.520 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:13:06.520 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:13:06.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:06.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:06.898 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:13:07.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:07.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:07.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:07.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:07.376 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:13:07.851 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:13:08.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:08.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:08.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:08.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:08.320 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:13:08.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:08.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:08.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:08.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:08.649 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:13:08.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:08.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:08.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:08.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:08.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:08.669 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:08.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:08.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:08.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:08.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:08.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:08.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:08.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:08.790 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:13:09.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:09.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:09.031 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:09.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:09.268 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:13:09.746 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:13:10.223 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:13:10.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:10.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:10.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:10.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:10.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:10.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:10.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:10.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:10.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:10.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:10.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:10.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:10.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:10.323 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:13:10.323 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:13:10.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:10.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:10.700 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:13:11.196 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:13:11.674 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:13:12.151 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:13:12.628 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:13:13.106 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:13:13.583 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:13:14.061 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:13:14.540 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:13:15.018 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:13:15.497 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:13:15.975 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:13:16.453 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:13:16.931 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:13:17.406 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:13:17.878 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:13:18.355 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:13:18.833 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:13:19.309 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:13:19.787 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:13:20.265 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:13:20.743 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:13:21.221 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:13:21.699 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:13:22.178 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:13:22.649 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:13:23.127 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:13:23.600 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:13:24.078 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:13:24.557 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:13:25.035 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:13:25.514 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:13:25.992 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:13:26.470 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:13:26.948 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:13:27.418 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:13:27.897 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:13:28.375 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:13:28.852 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:13:29.330 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:13:29.802 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:13:30.278 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:13:30.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:30.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:30.290 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:13:30.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:30.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:30.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:30.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:30.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:13:30.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:13:30.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:13:30.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:13:30.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:13:30.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:13:30.293 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:13:35.295 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:13:35.295 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:13:35.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:13:35.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:13:35.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:13:35.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:13:35.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:13:35.311 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:13:35.311 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:35.311 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:13:35.311 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:13:35.312 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:13:35.313 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:13:35.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:13:35.313 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:35.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:13:35.313 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:13:35.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:13:35.313 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:13:35.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:35.315 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:13:35.315 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:13:35.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:13:35.315 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:35.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:13:35.316 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:13:35.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:13:35.316 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:13:35.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:13:35.317 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:13:35.317 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:13:35.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.319 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:13:35.319 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:13:35.319 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:13:35.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:13:35.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:13:35.804 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:13:35.843 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:13:35.844 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:13:35.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:35.847 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:13:35.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:35.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:35.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:35.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:35.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:35.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:35.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:35.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:35.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:35.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:35.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:35.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:35.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:36.282 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:13:36.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:36.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:36.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:36.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:36.759 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:13:37.235 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:13:37.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:37.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:37.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:37.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:37.713 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:13:37.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:37.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:37.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:37.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:37.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:37.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:37.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:37.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:37.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:37.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:37.784 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:37.784 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:37.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:37.812 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:13:37.812 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:13:37.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:37.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:38.191 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:13:38.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:38.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:38.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:38.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:38.669 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:13:39.144 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:13:39.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:39.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:39.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:39.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:39.613 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:13:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:39.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:39.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:39.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:39.942 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:13:39.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:39.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:39.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:39.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:39.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:39.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:39.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:39.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:39.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:39.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:39.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:39.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:39.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:40.083 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:13:40.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:13:40.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:13:40.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:13:40.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:13:40.561 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:13:41.036 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:13:41.514 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:13:41.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:41.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:41.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:41.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:41.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:13:41.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:13:41.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:13:41.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:41.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:13:41.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:13:41.577 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:13:41.577 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:13:41.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:13:41.616 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:13:41.616 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:13:41.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:41.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:13:41.991 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:13:42.468 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:13:42.947 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:13:43.425 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:13:43.899 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:13:44.377 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:13:44.855 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:13:45.330 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:13:45.807 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:13:46.285 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:13:46.757 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:13:47.235 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:13:47.708 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:13:48.180 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:13:48.658 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:13:49.136 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:13:49.611 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:13:50.084 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:13:50.563 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:13:51.041 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:13:51.519 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:13:51.998 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:13:52.473 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:13:52.941 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:13:53.415 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:13:53.893 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:13:54.366 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:13:54.844 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:13:55.316 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:13:55.793 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:13:56.270 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:13:56.749 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:13:57.226 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:13:57.703 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:13:58.182 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:13:58.659 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:13:59.137 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:13:59.616 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:14:00.094 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:14:00.572 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:14:01.051 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:14:01.529 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:14:01.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:01.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:01.579 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:01.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:01.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:01.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:01.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:01.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:01.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:01.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:01.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:01.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:01.584 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:14:01.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:01.584 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5623 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:06.583 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:06.583 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:06.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:06.585 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:06.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:06.588 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:14:06.588 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:06.588 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:14:06.588 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:14:06.589 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:14:06.589 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:14:06.589 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:14:06.590 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:14:06.590 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:14:06.590 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:06.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:06.591 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:14:06.591 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:14:06.591 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:14:06.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:14:06.592 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:14:06.592 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:14:06.592 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:06.597 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:14:07.066 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:14:07.106 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:14:07.107 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:14:07.107 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:14:07.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:07.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:07.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:07.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:07.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:07.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:07.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:07.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:07.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:07.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:07.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:07.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:07.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:07.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:07.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:07.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:07.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:07.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:07.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:07.330 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:07.330 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:07.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:07.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:07.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:07.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:07.535 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:14:07.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:07.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:07.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:07.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:08.003 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:14:08.470 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:14:08.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:08.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:08.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:08.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:08.939 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:14:09.407 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:14:09.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:09.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:09.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:09.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:09.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:09.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:09.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:09.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:09.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:09.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:09.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:09.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:09.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:09.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:09.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:09.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:09.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:09.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:09.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:09.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:09.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:09.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:09.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:09.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:09.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:09.675 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:09.675 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:09.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:09.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:09.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:09.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:09.874 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:14:10.343 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:14:10.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:10.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:10.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:10.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:10.814 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:14:11.282 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:14:11.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:11.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:11.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:11.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:11.750 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:14:11.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:11.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:11.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:11.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:11.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:11.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:11.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:11.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:11.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:11.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:11.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:11.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:11.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:11.884 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:11.884 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:11.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:11.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:12.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:12.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:12.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:12.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:12.155 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:12.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:12.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:12.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:12.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:12.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:12.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:12.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:12.163 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:12.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:12.217 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:12.217 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:12.217 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:14:12.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:12.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:12.684 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:14:13.151 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:14:13.623 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:14:14.092 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:14:14.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:14.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:14.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:14.469 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:14.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:14.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:14.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:14.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:14.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:14.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:14.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:14.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:14.511 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:14.511 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:14.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.563 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:14:14.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:14.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:14.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:14.744 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:14.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:14.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:14.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:14.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:14.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:14.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:14.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:14.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:14.796 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:14.796 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:14.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:14.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:15.030 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:14:15.499 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:14:15.970 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:14:16.440 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:14:16.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:16.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:16.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:16.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:16.858 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:16.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:16.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:16.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:16.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:16.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:16.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:16.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:16.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:16.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:16.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:16.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:16.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:16.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:16.909 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:14:17.377 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:14:17.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:17.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:17.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:17.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:17.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:17.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:17.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:17.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:17.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:17.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:17.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:17.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:17.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:17.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:17.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:17.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:17.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:17.849 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:14:18.325 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:14:18.803 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:14:19.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:19.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:19.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:19.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:19.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:19.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:19.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:19.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:19.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:19.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:19.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:19.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:19.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:19.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:19.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:19.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:19.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:19.280 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:14:19.758 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:14:19.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:19.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:19.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:19.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:19.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:19.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:19.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:19.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:19.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:19.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:19.939 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:19.939 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:19.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:20.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:20.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:20.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:20.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:20.235 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:14:20.712 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:14:21.189 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:14:21.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:21.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:21.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:21.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:21.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:21.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:21.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:21.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:21.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:21.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:21.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:21.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:21.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:21.659 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:21.659 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:14:21.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:21.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:21.665 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:14:22.144 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:14:22.619 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:14:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:22.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:22.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:22.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:22.938 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:22.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:22.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:22.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:22.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:22.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:22.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:22.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:22.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:22.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:22.999 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:22.999 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:14:22.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:23.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:23.094 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:14:23.571 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:14:24.047 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:14:24.526 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:14:25.004 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:14:25.478 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:14:25.947 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:14:26.417 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:14:26.886 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:14:27.354 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:14:27.822 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:14:28.294 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:14:28.768 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:14:29.242 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:14:29.716 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:14:30.184 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:14:30.659 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:14:31.134 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:14:31.604 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:14:32.078 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:14:32.552 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:14:33.026 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:14:33.501 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:14:33.973 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:14:34.449 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:14:34.925 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:14:35.400 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:14:35.875 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:14:36.348 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:14:36.819 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:14:37.287 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:14:37.756 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:14:38.230 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:14:38.702 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:14:39.173 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:14:39.641 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:14:40.109 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:14:40.582 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:14:41.057 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:14:41.531 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:14:42.001 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:14:42.476 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:14:42.951 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:14:42.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:42.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:42.961 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:42.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:42.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:42.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:42.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:42.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:42.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:42.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:42.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:42.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:42.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:42.962 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:14:42.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:42.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=7859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:47.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:47.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:47.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:47.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:47.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:47.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:47.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:47.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:14:47.968 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:47.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:14:47.968 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:14:47.969 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:14:47.969 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:14:47.969 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:14:47.970 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:14:47.970 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:14:47.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:14:47.971 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:47.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:47.971 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:14:47.971 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:14:47.971 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:14:47.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:14:47.972 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:14:47.972 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.972 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:47.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:14:48.458 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:14:48.497 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:14:48.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.499 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:14:48.501 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:14:48.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:48.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:48.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:48.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:48.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:48.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:48.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.698 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:48.698 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:48.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.741 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:48.741 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:48.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.817 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:48.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:48.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:48.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:48.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.887 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:48.887 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:48.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.928 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:14:48.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:48.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.968 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:48.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:48.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:48.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:48.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:48.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:48.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:48.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:48.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:48.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:48.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:48.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:48.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:49.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:49.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:49.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:49.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:49.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:49.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:49.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:49.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:49.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:49.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:49.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:49.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:49.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:49.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:49.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.400 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:14:49.401 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:49.401 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:14:49.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.481 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:49.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:49.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:49.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:49.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:49.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:49.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.538 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:49.538 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:14:49.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:49.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:49.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:49.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:49.724 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:49.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:49.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:49.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:49.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:49.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:49.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:49.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:49.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:49.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:49.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:49.736 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:49.736 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:54.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:54.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:54.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:54.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:54.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:54.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:54.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:54.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:14:54.749 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:54.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:14:54.749 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:14:54.753 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:14:54.754 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:14:54.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:14:54.754 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:54.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:54.755 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:14:54.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:14:54.756 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:14:54.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:54.757 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:14:54.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:14:54.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:14:54.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:54.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:54.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:14:54.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:14:54.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:14:54.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:54.760 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:14:54.760 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:14:54.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:14:54.761 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:14:54.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:54.761 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:14:54.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:14:54.761 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:14:54.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:14:54.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:14:54.765 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:14:54.765 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:14:54.765 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:14:54.770 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:14:55.251 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:14:55.283 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:14:55.283 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:14:55.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:55.284 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:14:55.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:55.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:55.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:55.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:55.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:55.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:55.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:55.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:55.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:55.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:55.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:55.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:55.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:55.728 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:14:55.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:55.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:55.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:55.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:56.206 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:14:56.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:56.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:56.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:56.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:56.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:56.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:56.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:56.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:56.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:56.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:56.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:56.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:56.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:56.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.683 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:14:56.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:56.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:56.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:56.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:56.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:56.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:56.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:56.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:56.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:56.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:56.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:56.729 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:56.729 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:56.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:56.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:56.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:56.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:56.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:57.152 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:14:57.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:57.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:57.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:57.424 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:57.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:57.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:57.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:57.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:57.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:57.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:57.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:57.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:57.486 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:57.486 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:14:57.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.621 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:14:57.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:57.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:57.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:57.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:57.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:57.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:57.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:57.911 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:57.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:57.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:57.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:57.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:57.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:57.932 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:57.932 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:57.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:57.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:57.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:57.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:57.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:58.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:58.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:58.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:58.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:58.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:58.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:58.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:58.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:58.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:58.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:58.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:58.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:58.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.092 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:14:58.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:58.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:58.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:58.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:58.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:58.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:58.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:58.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:58.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:58.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:58.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:58.567 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:14:58.569 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:58.570 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:14:58.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:58.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:58.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:58.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:58.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:58.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:58.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:58.964 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:58.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:58.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:58.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:14:58.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:58.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:14:58.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:14:58.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:14:58.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:14:59.039 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:14:59.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:59.049 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:14:59.050 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:14:59.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:59.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:59.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:14:59.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:14:59.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:14:59.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:14:59.434 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:14:59.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:14:59.439 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:14:59.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:14:59.439 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.439 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.439 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.440 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.440 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.440 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.440 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:14:59.440 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1007 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:04.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:04.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:04.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:04.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:04.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:04.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:04.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:04.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:04.453 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:04.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:04.453 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:04.456 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:04.456 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:04.456 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:04.456 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:04.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:04.457 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:04.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:04.457 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:04.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:04.459 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:04.459 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:04.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:04.459 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:04.460 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:04.460 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:04.460 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:04.460 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:04.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:04.462 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:04.462 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:04.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:04.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:04.466 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:04.466 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:04.466 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:04.471 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:04.951 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:04.982 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:04.983 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:04.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:04.984 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:04.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:04.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:04.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:04.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:04.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:04.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:04.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:04.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:05.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:05.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:05.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.272 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:05.272 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.278 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:05.279 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:05.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.372 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:05.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:05.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:05.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.420 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:05.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.428 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:05.428 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:05.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:05.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:05.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:05.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:05.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.488 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:05.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:05.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:05.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:05.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:05.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.897 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:05.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:05.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:05.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:05.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:05.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:05.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:05.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:05.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:05.955 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:05.955 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:05.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:05.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:06.375 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:06.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:06.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:06.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:06.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:06.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:06.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:06.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:06.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:06.534 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:06.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:06.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:06.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:06.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:06.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:06.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:06.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:06.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:06.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:06.559 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:06.559 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:06.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:06.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:06.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:06.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:06.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:06.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:06.769 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:06.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:06.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:06.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:06.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:06.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:06.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:06.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:06.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:06.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:06.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:06.780 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:06.780 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:11.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:11.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:11.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:11.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:11.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:11.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:11.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:11.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:11.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:11.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:11.794 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:11.797 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:11.797 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:11.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:11.797 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:11.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:11.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:11.798 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:11.798 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:11.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:11.800 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:11.801 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:11.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:11.801 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:11.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:11.801 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:11.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:11.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:11.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:11.803 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:11.804 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:11.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:11.804 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:11.804 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:11.804 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:11.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:11.804 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:11.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:11.807 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:11.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.808 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:11.808 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:11.808 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:11.809 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:11.813 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:12.298 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:12.345 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:12.347 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:12.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:12.349 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:12.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:12.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:12.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:12.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:12.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:12.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:12.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:12.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:12.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:12.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:12.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:12.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:12.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:12.768 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:12.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:12.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:12.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:12.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:13.241 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:13.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:13.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:13.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:13.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:13.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:13.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:13.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:13.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:13.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:13.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:13.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:13.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:13.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:13.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:13.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:13.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:13.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:13.717 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:13.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:13.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:13.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:13.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:14.195 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:15:14.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:14.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:14.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:14.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:14.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:14.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:14.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:14.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:14.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:14.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:14.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:14.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:14.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:14.295 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:14.295 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:14.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:14.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:14.670 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:15:14.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:14.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:14.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:14.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:15.148 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:15:15.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:15.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:15.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:15.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:15.450 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:15.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:15.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:15.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:15.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:15.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:15.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:15.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:15.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:15.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:15.525 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:15.525 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:15.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:15.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:15.626 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:15:15.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:15.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:15.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:15.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:16.104 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:15:16.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:16.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:16.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:16.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:16.425 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:16.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:16.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:16.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:16.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:16.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:16.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:16.445 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:16.445 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:16.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:16.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:16.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:16.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:16.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:16.581 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:15:16.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:16.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:16.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:16.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:17.058 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:15:17.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:17.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:17.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:17.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:17.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:17.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:17.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:17.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:17.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:17.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:17.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:17.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:17.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:17.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:17.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:17.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:17.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:17.534 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:15:18.008 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:15:18.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:18.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:18.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:18.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:18.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:18.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:18.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:18.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:18.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:18.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:18.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:18.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:18.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:18.106 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:18.106 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:18.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:18.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:18.486 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:15:18.962 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:15:19.429 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:15:19.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:19.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:19.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:19.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:19.888 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:19.905 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:15:19.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:19.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:19.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:19.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:19.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:19.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:19.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:19.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:19.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:19.961 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:19.961 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:19.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:19.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:20.383 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:15:20.860 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:15:21.336 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:15:21.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:21.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:21.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:21.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:21.796 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:21.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:21.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:21.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:21.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:21.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:21.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:21.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:21.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:21.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:21.809 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:21.809 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2143 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:21.809 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2144 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:26.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:26.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:26.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:26.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:26.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:26.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:26.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:26.821 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:26.821 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:26.821 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:26.821 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:26.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:26.824 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:26.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:26.825 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:26.825 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:26.825 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:26.825 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:26.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:26.828 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:26.828 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:26.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:26.830 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:26.830 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:26.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:26.831 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:26.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:26.831 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:26.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:26.831 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:26.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:26.833 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:26.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:26.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:26.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:26.833 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:26.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:26.834 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:26.834 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:26.834 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:26.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:26.839 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:27.319 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:27.350 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:27.350 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:27.351 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:27.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:27.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:27.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:27.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:27.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:27.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:27.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:27.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:27.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:27.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:27.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:27.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:27.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:27.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:27.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:27.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:27.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:27.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:27.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:27.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:27.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:27.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:27.611 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:27.611 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:27.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:27.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:27.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:27.783 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:27.796 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:27.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:27.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:27.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:27.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:27.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:27.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:27.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:27.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:27.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:27.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:27.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:27.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:27.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:27.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:27.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:27.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:28.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:28.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:28.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:28.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:28.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:28.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:28.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:28.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:28.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:28.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:28.050 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:28.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:28.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:28.085 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:28.085 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:28.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:28.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:28.272 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:28.751 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:28.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:28.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:28.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:28.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:28.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:28.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:28.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:28.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:28.910 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:28.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:28.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:28.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:28.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:28.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:28.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:28.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:28.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:28.918 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:28.918 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:28.918 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:28.918 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:33.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:33.921 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:33.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:33.926 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:33.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:33.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:33.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:33.935 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:33.936 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:33.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:33.936 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:33.938 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:33.939 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:33.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:33.939 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:33.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:33.940 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:33.940 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:33.940 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:33.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:33.941 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:33.941 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:33.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:33.943 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:33.943 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:33.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:33.943 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:33.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:33.943 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:33.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:33.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:33.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:33.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:33.947 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:33.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:33.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:33.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:34.435 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:34.469 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:34.470 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:34.471 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:34.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:34.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:34.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:34.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:34.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:34.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:34.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:34.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:34.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:34.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:34.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:34.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:34.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:34.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:34.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:34.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:34.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:34.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:34.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:34.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:34.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:34.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:34.727 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:34.727 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:34.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:34.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:34.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:34.898 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:34.912 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:34.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:34.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:34.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:34.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:34.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:34.921 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:34.921 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:34.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:34.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:34.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:34.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:34.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:34.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:34.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:34.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:34.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:35.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:35.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:35.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:35.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:35.144 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=256 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:35.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:35.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:35.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:35.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:35.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:35.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:35.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:35.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:35.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:35.205 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:35.205 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:35.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:35.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:35.384 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:35.862 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:35.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:35.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:35.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:35.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:36.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:36.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:36.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:36.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:36.021 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:36.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:36.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:36.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:36.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:36.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:36.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:36.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:36.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:36.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:36.027 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:15:36.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:41.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:41.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:41.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:41.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:41.033 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:41.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:41.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:41.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:41.041 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:41.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:41.041 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:41.044 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:41.044 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:41.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:41.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:41.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:41.046 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:41.046 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:41.046 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:41.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:41.048 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:41.048 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:41.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:41.048 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:41.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:41.049 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:41.049 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:41.049 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:41.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:41.051 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:41.051 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:41.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:41.051 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:41.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:41.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:41.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:41.051 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:41.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:41.056 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:41.056 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:41.056 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:41.061 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:41.542 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:41.586 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:41.587 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:41.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:41.589 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:41.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:41.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:41.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:41.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:41.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:41.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:41.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:41.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:41.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:41.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:41.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:41.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:41.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:41.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:41.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:41.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:41.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:41.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:41.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:41.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:41.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:41.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:41.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:41.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:41.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:41.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:41.835 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:41.835 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:41.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:41.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:42.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:42.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:42.006 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:42.019 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:42.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:42.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:42.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:42.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:42.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:42.025 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:42.025 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:42.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:42.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:42.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:42.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:42.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:42.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:42.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:42.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:42.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:42.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:42.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:42.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:42.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:42.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:42.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:42.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:42.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:42.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:42.312 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:42.312 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:42.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:42.495 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:42.964 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:43.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:43.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:43.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:43.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:43.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:43.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:43.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:43.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:43.121 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:43.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:43.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:43.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:43.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:43.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:43.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:43.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:43.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:43.133 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:43.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:43.134 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:15:43.134 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:43.134 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:43.134 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:43.134 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:43.134 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:43.135 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:48.129 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:48.129 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:48.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:48.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:48.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:48.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:48.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:48.133 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:48.133 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:48.133 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:48.133 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:48.134 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:48.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:48.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:48.135 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:48.135 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:48.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:48.136 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:48.136 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:48.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:48.137 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:48.137 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:48.137 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:48.142 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:48.624 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:48.653 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:48.654 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:48.654 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:48.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:48.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:48.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:48.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:48.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:48.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:48.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:48.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:48.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:48.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:48.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:48.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:48.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:48.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:48.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:48.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:48.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:48.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:48.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:48.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:48.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:48.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:48.813 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:48.813 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:48.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:48.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:48.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:48.968 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:48.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:48.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:48.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:48.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:48.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:48.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:48.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:48.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:48.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:48.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:48.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:48.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:49.093 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:49.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:49.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:49.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:49.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:49.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:49.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:49.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:49.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:49.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:49.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:49.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:49.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:49.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:49.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:49.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:49.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:49.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:49.382 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:49.382 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:49.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:49.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:49.571 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:50.048 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:50.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:50.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:50.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:50.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:50.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:50.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:50.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:50.209 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:50.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:50.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:50.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:50.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:50.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:50.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:50.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:50.221 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:50.221 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:50.221 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:50.221 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:50.222 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:15:55.223 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:55.223 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:55.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:55.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:55.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:55.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:55.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:55.238 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:55.238 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:55.238 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:15:55.238 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:15:55.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:15:55.241 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:15:55.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:55.241 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:55.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:55.241 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:15:55.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:15:55.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:15:55.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:55.243 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:15:55.243 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:15:55.243 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:55.243 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:55.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:55.243 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:15:55.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:15:55.244 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:15:55.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:55.244 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:15:55.244 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:15:55.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:55.245 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:15:55.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:55.245 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:15:55.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:15:55.245 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:15:55.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:55.246 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:15:55.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:15:55.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:15:55.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:15:55.246 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:15:55.247 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:15:55.247 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:15:55.247 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:15:55.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:15:55.252 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:15:55.731 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:15:55.772 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:15:55.775 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:15:55.777 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:15:55.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:55.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:55.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:55.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:55.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:55.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:55.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:55.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:55.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:55.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:55.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:55.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:55.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:55.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:56.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:56.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:56.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:56.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:56.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:56.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:56.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:56.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:56.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:56.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:56.207 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:15:56.214 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:56.214 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:15:56.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:56.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:56.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:56.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:56.676 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:15:56.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:56.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:56.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:56.690 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:56.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:56.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:56.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:56.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:56.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:56.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:56.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:56.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:56.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:56.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:56.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:56.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:57.150 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:15:57.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:57.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:57.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:57.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:57.628 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:15:57.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:57.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:57.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:57.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:57.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:57.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:57.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:15:57.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:57.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:15:57.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:15:57.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:15:57.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:15:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:57.813 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:15:57.813 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:15:57.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:57.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:58.103 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:15:58.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:58.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:58.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:58.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:58.579 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:15:59.057 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:15:59.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:59.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:59.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:59.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:59.535 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:15:59.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:15:59.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:15:59.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:15:59.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:15:59.857 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:15:59.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:15:59.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:15:59.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:15:59.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:15:59.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:15:59.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:15:59.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:15:59.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:15:59.865 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:15:59.865 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:15:59.865 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:04.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:04.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:04.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:04.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:04.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:04.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:04.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:04.884 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:04.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:04.884 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:04.888 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:04.888 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:04.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:04.888 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:04.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:04.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:04.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:04.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:04.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:04.892 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:04.892 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:04.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:04.892 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:04.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:04.892 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:04.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:04.893 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:04.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:04.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:04.895 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:04.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:04.895 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:04.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:04.896 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:04.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:04.896 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:04.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:04.899 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:04.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:04.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:04.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:04.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.900 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:04.900 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:04.900 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:04.901 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:04.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:05.388 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:05.435 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:05.437 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:05.438 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:05.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:05.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:05.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:05.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:05.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.456 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:05.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:05.456 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:05.456 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:05.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:05.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:05.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:05.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:05.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:05.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:05.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:05.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:05.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:05.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:05.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:05.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:05.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:05.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:05.865 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:16:05.869 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:16:05.869 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:16:05.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:05.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:05.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:05.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:05.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:06.344 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:16:06.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:06.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:06.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:06.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:06.362 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:16:06.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:06.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:06.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:06.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:06.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:06.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:06.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:06.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:06.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:06.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:06.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:06.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:06.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:06.820 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:16:06.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:06.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:06.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:06.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:07.299 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:16:07.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:07.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:07.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:07.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:07.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:07.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:07.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:07.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:07.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:07.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:07.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:07.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:07.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:07.544 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:16:07.544 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:16:07.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:07.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:07.773 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:16:07.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:07.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:07.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:07.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:08.252 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:16:08.726 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:16:08.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:08.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:08.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:08.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:09.203 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:16:09.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:09.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:09.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:09.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:09.524 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:16:09.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:09.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:09.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:09.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:09.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:09.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:09.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:09.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:09.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:09.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:09.533 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:14.539 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:14.539 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:14.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:14.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:14.539 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:14.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:14.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:14.549 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:14.549 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:14.550 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:14.550 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:14.554 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:14.554 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:14.555 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:14.555 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:14.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:14.556 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:14.557 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:14.557 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:14.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:14.558 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:14.558 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:14.558 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:14.558 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:14.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:14.559 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:14.559 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:14.559 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:14.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:14.561 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:14.561 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:14.561 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:14.561 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:14.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:14.561 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:14.561 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:14.561 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:14.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.565 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:14.565 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:14.565 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:14.566 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:14.570 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:15.051 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:15.090 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:15.091 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:15.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:15.092 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:15.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:15.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:15.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:15.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:15.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:15.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:15.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:15.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:15.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:15.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:15.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:15.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:15.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:15.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:15.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:15.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:15.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:15.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:15.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:15.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:15.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:15.521 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:16:15.521 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:16:15.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:15.526 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:16:15.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:15.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:15.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:15.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:15.996 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:16:16.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:16.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:16.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:16.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:16.009 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:16:16.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:16.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:16.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:16.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:16.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:16.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:16.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:16.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:16.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:16.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:16.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:16.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:16.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:16.469 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:16:16.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:16.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:16.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:16.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:16.947 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:16:17.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:17.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:17.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:17.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:17.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:17.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:17.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:17.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:17.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:17.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:17.110 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:17.110 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:17.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:17.133 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:16:17.134 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:16:17.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:17.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:17.423 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:16:17.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:17.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:17.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:17.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:17.901 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:16:18.378 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:16:18.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:18.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:18.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:18.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:18.856 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:16:19.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:19.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:19.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:19.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:19.179 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:16:19.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:19.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:19.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:19.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:19.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:19.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:19.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:19.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:19.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:19.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:19.191 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.192 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:19.193 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:24.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:24.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:24.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:24.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:24.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:24.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:24.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:24.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:24.205 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:24.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:24.206 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:24.209 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:24.210 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:24.210 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:24.210 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:24.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:24.211 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:24.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:24.212 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:24.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:24.213 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:24.213 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:24.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:24.213 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:24.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:24.213 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:24.214 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:24.214 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:24.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:24.215 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:24.215 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:24.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:24.216 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:24.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:24.216 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:24.216 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:24.216 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:24.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:24.220 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:24.220 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:24.220 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:24.225 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:24.705 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:24.747 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:24.748 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:24.750 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:24.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:24.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:24.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:24.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:24.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:24.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:24.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:24.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:24.771 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:24.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:24.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:24.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:24.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:24.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:25.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:25.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:25.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:25.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:25.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:25.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:25.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:25.144 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:25.144 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:25.178 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:16:25.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:25.186 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:16:25.186 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:16:25.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:25.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:25.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:25.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:25.657 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:16:25.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:25.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:25.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:25.665 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:16:25.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:25.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:25.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:25.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:25.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:25.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:25.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:25.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:25.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:25.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:25.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:25.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:26.133 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:16:26.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:26.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:26.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:26.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:26.611 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:16:26.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:26.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:26.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:26.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:26.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:26.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:26.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:26.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:26.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:26.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:26.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:26.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:26.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:26.849 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:16:26.849 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:16:26.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:26.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:27.088 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:16:27.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:27.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:27.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:27.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:27.566 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:16:28.042 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:16:28.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:28.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:28.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:28.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:28.514 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:16:28.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:28.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:28.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:28.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:28.835 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:16:28.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:28.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:28.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:28.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:28.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:28.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:28.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:28.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:28.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:28.840 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:28.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:33.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:33.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:33.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:33.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:33.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:33.848 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:33.855 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:33.857 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:33.857 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:33.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:33.858 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:33.861 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:33.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:33.862 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:33.862 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:33.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:33.863 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:33.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:33.864 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:33.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:33.864 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:33.865 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:33.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:33.865 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:33.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:33.865 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:33.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:33.865 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:33.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:33.867 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:33.867 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:33.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:33.871 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:33.871 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:33.871 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:33.876 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:34.360 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:34.402 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:34.404 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:34.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:34.406 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:34.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:34.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:34.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:34.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:34.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:34.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:34.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:34.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:34.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:34.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:34.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:34.448 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:34.448 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:34.448 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:34.448 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:34.448 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:34.448 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:34.448 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:34.449 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:34.449 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:34.449 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:39.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:39.449 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:39.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:39.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:39.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:39.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:39.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:39.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:39.461 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:39.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:39.461 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:39.465 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:39.465 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:39.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:39.466 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:39.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:39.466 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:39.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:39.466 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:39.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:39.469 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:39.469 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:39.469 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:39.469 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:39.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:39.470 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:39.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:39.470 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:39.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:39.472 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:39.473 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:39.473 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:39.473 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:39.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:39.473 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:39.473 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:39.473 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:39.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:39.476 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:39.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:39.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:39.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:39.476 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.477 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:39.477 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:39.477 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:39.477 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:39.482 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:39.965 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:40.005 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:40.006 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:40.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:40.009 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:40.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:40.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:40.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:40.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:40.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:40.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:40.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:40.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:40.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:40.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:40.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:40.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:40.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:40.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:40.063 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:40.063 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:40.063 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:40.063 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:40.063 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:40.064 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:40.064 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:40.064 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:40.064 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:40.064 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:45.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:45.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:45.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:45.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:45.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:45.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:45.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:45.073 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:45.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:45.074 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:45.075 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:45.075 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:45.076 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:45.076 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:45.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:45.076 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:45.076 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:45.076 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:45.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:45.077 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:45.077 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:45.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:45.077 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:45.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:45.078 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:45.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:45.078 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:45.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:45.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:45.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:45.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:45.081 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:45.081 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:45.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:45.082 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:45.082 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:45.087 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:45.570 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:45.613 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:45.615 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:45.617 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:45.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:45.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:45.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:45.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:45.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:45.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:45.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:45.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:45.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:45.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:45.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:45.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:45.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:45.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:45.648 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:45.648 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:16:50.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:50.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:50.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:50.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:50.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:50.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:50.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:50.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:50.650 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:50.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:50.650 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:50.651 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:50.651 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:50.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:50.652 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:50.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:50.652 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:50.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:50.652 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:50.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:50.653 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:50.653 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:50.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:50.654 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:50.654 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:50.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:50.656 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:50.656 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:50.656 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:50.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:50.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:50.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:50.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:50.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:50.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:50.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:50.658 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:16:55.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:16:55.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:16:55.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:55.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:55.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:55.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:55.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:16:55.672 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:55.672 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:55.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:16:55.673 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:16:55.675 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:16:55.675 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:16:55.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:55.676 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:55.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:16:55.676 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:16:55.677 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:16:55.677 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:16:55.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:55.678 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:16:55.678 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:16:55.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:55.678 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:55.678 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:16:55.679 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:16:55.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:16:55.679 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:16:55.679 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:55.681 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:16:55.681 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:16:55.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.684 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:16:55.685 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:16:55.685 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:16:55.685 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:16:55.690 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:16:56.172 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:16:56.215 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:16:56.217 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:16:56.219 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:16:56.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:56.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:56.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:56.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:56.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:56.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:56.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:56.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:56.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:56.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:56.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:56.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:56.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:56.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:56.649 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:16:56.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:56.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:56.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:56.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:57.126 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:16:57.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:57.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:57.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:57.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:57.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:57.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:57.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:57.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:57.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:57.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:57.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:57.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:57.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:57.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:57.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:57.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:57.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:57.602 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:16:57.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:57.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:57.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:57.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:58.080 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:16:58.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:58.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:58.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:58.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:58.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:58.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:58.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:58.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:58.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:58.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:58.217 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:58.217 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:58.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:58.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:58.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:58.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:58.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:58.551 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:16:58.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:58.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:58.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:58.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:59.023 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:16:59.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:59.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:59.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:59.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:59.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:16:59.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:16:59.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:16:59.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:59.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:59.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:59.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:16:59.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:16:59.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:16:59.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:16:59.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:16:59.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:59.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:16:59.498 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:16:59.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:16:59.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:16:59.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:16:59.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:16:59.976 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:17:00.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:00.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:00.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:00.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:00.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:00.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:00.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:00.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:00.169 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:00.169 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:00.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:00.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:00.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:00.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.448 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:17:00.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:00.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:00.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:00.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:00.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:00.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:00.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:00.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:00.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:00.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:00.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:00.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:00.787 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:00.787 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:00.831 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:00.832 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:17:00.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:00.924 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:17:01.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:01.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:01.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:01.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:01.397 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:01.400 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:17:01.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:01.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:01.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:01.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:01.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:01.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:01.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:01.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:01.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:01.456 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:01.456 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-02 03:17:01.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:01.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:01.877 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:17:02.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:02.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:02.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:02.009 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:02.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:02.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:02.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:02.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:02.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:02.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:02.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:02.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:02.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:02.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:02.070 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:02.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.352 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:17:02.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:02.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:02.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:02.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:02.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:02.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:02.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:02.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:02.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:02.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:02.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:02.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:02.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:02.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:02.830 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:17:03.307 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:17:03.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:03.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:03.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:03.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:03.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:03.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:03.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:03.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:03.344 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:03.344 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:03.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:03.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:03.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:03.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:03.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.783 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:17:03.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:03.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:03.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:03.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:03.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:03.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:03.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:03.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:03.930 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:03.930 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:03.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:03.981 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:03.981 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:17:03.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:03.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:04.254 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:17:04.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:04.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:04.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:04.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:04.565 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:04.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:04.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:04.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:04.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:04.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:04.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:04.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:04.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:04.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:04.640 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:04.641 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:17:04.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:04.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:04.725 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:17:05.192 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:17:05.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:05.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:05.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:05.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:05.238 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:05.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:05.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:05.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:05.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:05.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:05.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:05.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:05.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:05.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:05.287 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:05.287 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:05.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:05.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:05.665 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:17:06.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:06.141 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:17:06.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:06.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:06.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:06.145 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:06.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:06.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:06.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:06.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:06.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:06.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:06.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:06.163 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:06.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:06.195 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:06.195 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:06.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:06.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:06.614 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:17:07.091 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:17:07.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:07.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:07.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:07.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:07.123 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:07.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:07.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:07.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:07.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:07.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:07.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:07.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:07.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:07.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:07.194 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:07.194 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:07.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:07.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:07.569 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:17:08.047 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:17:08.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:08.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:08.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:08.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:08.097 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:08.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:08.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:08.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:08.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:08.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:08.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:08.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:08.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:08.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:08.146 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:08.146 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:08.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:08.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:08.524 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:17:09.002 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:17:09.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:09.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:09.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:09.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:09.069 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:09.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:09.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:09.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:09.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:09.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:09.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:09.080 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:09.080 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:09.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:09.096 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:09.096 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:09.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:09.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:09.479 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:17:09.958 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:17:10.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:10.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:10.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:10.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:10.045 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:10.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:10.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:10.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:10.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:10.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:10.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:10.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:10.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:10.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:10.107 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:10.107 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:10.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:10.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:10.437 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:17:10.915 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:17:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:11.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:11.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:11.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:11.020 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:11.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:11.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:11.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:11.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:11.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:11.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:11.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:11.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:11.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:11.055 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:11.055 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:11.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:11.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:11.386 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:17:11.865 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:17:12.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:12.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:12.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:12.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:12.013 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:12.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:12.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:12.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:12.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:12.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:12.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:12.035 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:12.035 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:12.050 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:17:12.050 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:17:12.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:12.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:12.337 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:17:12.811 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:17:12.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:12.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:12.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:12.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:12.952 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:17:12.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:12.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:12.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:12.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:12.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:12.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:12.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:17:12.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:17:12.962 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:17:12.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:12.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:12.962 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3706 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:17.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:17:17.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:17:17.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:17.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:17.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:17.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:17.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:17.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:17:17.969 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:17.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:17:17.969 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:17:17.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:17:17.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:17:17.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:17:17.971 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:17.972 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:17.972 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:17:17.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:17:17.972 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:17:17.973 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:17:17.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:17:17.973 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:17:17.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:17:17.975 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:17:17.975 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:17:17.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.978 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:17:17.978 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:17:17.978 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:17:17.978 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:17.983 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:17:18.463 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:17:18.498 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:17:18.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:18.499 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:17:18.502 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:17:18.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:18.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:18.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:18.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:18.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:18.530 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:18.530 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:18.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:18.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:18.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:18.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:18.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:18.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:18.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:18.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:18.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:18.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:18.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:18.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:18.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:18.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:18.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:18.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:18.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:18.940 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:17:18.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:18.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:18.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:18.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:19.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:19.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:19.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:19.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:19.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:19.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:19.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:19.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:19.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:19.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:19.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:19.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:19.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:19.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:19.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:19.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:19.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:19.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:19.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:17:19.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:19.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:19.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:17:19.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:17:19.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:19.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:17:19.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:17:19.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.417 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:17:19.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:17:19.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:17:19.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:17:19.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:17:19.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:19.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:17:19.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:17:19.599 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:17:19.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=347 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:19.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=347 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:19.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=347 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:19.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=347 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:19.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=347 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:19.600 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:24.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:17:24.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:17:24.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:24.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:24.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:24.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:24.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:24.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:17:24.621 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:24.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:17:24.621 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:17:24.626 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:17:24.626 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:17:24.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:17:24.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:24.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:24.627 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:17:24.627 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:17:24.627 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:17:24.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:24.630 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:17:24.630 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:17:24.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:17:24.630 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:24.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:24.631 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:17:24.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:17:24.631 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:17:24.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:24.633 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:17:24.633 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:17:24.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:17:24.634 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:24.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:24.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:17:24.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:17:24.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:17:24.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:24.637 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:17:24.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:17:24.638 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:17:24.639 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:24.643 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:17:25.127 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:17:25.605 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:17:26.080 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:17:26.548 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:17:27.017 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:17:27.485 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:17:27.957 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:17:28.438 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:17:28.910 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:17:29.380 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:17:29.856 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:17:30.334 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:17:30.812 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:17:31.290 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:17:31.768 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:17:32.245 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:17:32.726 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:17:33.207 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:17:33.684 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:17:34.160 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:17:34.628 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:17:35.102 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:17:35.578 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:17:36.046 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:17:36.515 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:17:36.986 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:17:37.467 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:17:37.945 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:17:38.422 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:17:38.901 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:17:39.382 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:17:39.857 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:17:40.326 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:17:40.804 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:17:41.283 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:17:41.760 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:17:42.236 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:17:42.717 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:17:43.191 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:17:43.659 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:17:44.135 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:17:44.614 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:17:45.095 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:17:45.576 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:17:46.056 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:17:46.530 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:17:46.999 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:17:47.471 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:17:47.942 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:17:48.410 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:17:48.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:48.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:48.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:48.663 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:48.663 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:17:48.663 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:17:48.663 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:48.664 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5156 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:17:53.666 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:17:53.666 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:17:53.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:53.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:53.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:53.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:53.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:17:53.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:17:53.677 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:53.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:17:53.677 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:17:53.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:17:53.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:17:53.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:17:53.681 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:53.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:17:53.681 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:17:53.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:17:53.682 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:17:53.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:17:53.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:17:53.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:17:53.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:17:53.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:53.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:17:53.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:17:53.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:17:53.685 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:17:53.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:17:53.687 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:17:53.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:17:53.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:17:53.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:17:53.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:17:53.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:17:53.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:17:53.688 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:17:53.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:17:53.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:17:53.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:17:53.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:17:53.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:17:53.693 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:17:53.697 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:17:54.179 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:17:54.647 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:17:55.116 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:17:55.585 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:17:56.054 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:17:56.529 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:17:57.010 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:17:57.488 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:17:57.957 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:17:58.427 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:17:58.908 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:17:59.379 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:17:59.847 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:18:00.316 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:18:00.785 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:18:01.253 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:18:01.729 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:18:02.210 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:18:02.692 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:18:03.170 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:18:03.647 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:18:04.116 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:18:04.584 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:18:05.053 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:18:05.523 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:18:06.005 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:18:06.486 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:18:06.967 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:18:07.448 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:18:07.929 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:18:08.410 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:18:08.884 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:18:09.353 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:18:09.829 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:18:10.306 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:18:10.783 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:18:11.264 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:18:11.743 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:18:12.220 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:18:12.698 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:18:13.176 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:18:13.656 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:18:14.135 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:18:14.617 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:18:15.098 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:18:15.566 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:18:16.037 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:18:16.515 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:18:16.987 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:18:17.460 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:18:17.933 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:18:18.402 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:18:18.872 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:18:19.344 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:18:19.812 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:18:20.288 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:18:20.766 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:18:21.243 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:18:21.718 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:18:22.195 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:18:22.673 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:18:23.148 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:18:23.624 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:18:24.103 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:18:24.583 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:18:25.062 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:18:25.543 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:18:26.024 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:18:26.505 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:18:26.983 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:18:27.461 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:18:27.939 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:18:28.412 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:18:28.883 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:18:29.352 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:18:29.826 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:18:30.302 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:18:30.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:30.780 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 03:18:31.250 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 03:18:31.719 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 03:18:31.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:32.188 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 03:18:32.656 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 03:18:32.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:33.126 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 03:18:33.605 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 03:18:33.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:34.086 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 03:18:34.557 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 03:18:34.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:35.025 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 03:18:35.497 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 03:18:35.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:35.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:18:35.722 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:18:35.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:18:35.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:18:35.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:18:35.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:18:35.724 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:18:35.724 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9027 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:35.724 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9027 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:35.724 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=9027 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:40.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:18:40.726 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:18:40.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:18:40.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:18:40.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:18:40.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:18:40.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:18:40.733 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:18:40.733 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:18:40.733 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:18:40.734 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:18:40.735 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:18:40.735 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:18:40.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:18:40.735 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:18:40.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:18:40.736 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:18:40.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:18:40.736 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:18:40.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:40.737 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:18:40.737 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:18:40.738 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:18:40.738 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:18:40.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:18:40.738 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:18:40.738 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:18:40.738 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:18:40.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:40.739 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:18:40.739 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:18:40.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:18:40.739 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:18:40.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:18:40.739 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:18:40.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:18:40.739 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:18:40.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:40.741 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:18:40.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:18:40.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:18:40.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:18:40.741 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:18:40.742 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:18:40.742 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:18:40.742 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:18:40.747 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:18:41.229 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:18:41.269 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:18:41.271 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:18:41.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:41.274 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:18:41.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:41.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:41.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:18:41.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:41.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:18:41.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:18:41.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:18:41.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:18:41.321 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:18:41.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:41.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:18:41.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:18:41.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:41.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:41.705 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:18:41.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:41.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:41.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:41.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:42.184 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:18:42.200 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:18:42.661 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:18:42.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:42.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:42.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:42.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:43.139 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:18:43.617 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:18:43.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:43.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:43.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:43.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:44.092 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:18:44.570 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:18:44.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:44.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:44.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:44.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:45.048 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:18:45.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:45.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:45.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:45.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:45.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:45.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:45.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:18:45.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:45.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:18:45.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:18:45.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:18:45.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:18:45.184 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:18:45.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:45.190 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:18:45.190 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:18:45.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:45.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:45.521 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:18:45.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:45.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:45.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:45.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:46.000 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:18:46.478 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:18:46.957 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:18:47.435 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:18:47.913 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:18:48.391 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:18:48.868 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:18:49.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:49.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:49.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:49.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:49.260 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:18:49.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:49.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:49.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:18:49.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:49.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:18:49.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:18:49.275 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:18:49.275 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:18:49.285 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:18:49.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:49.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:18:49.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:18:49.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:49.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:49.345 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:18:49.782 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:18:49.822 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:18:50.298 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:18:50.770 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:18:51.248 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:18:51.725 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:18:52.202 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:18:52.676 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:18:53.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:53.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:53.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:53.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:53.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:53.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:53.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:18:53.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:53.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:18:53.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:18:53.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:18:53.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:18:53.140 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:18:53.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:53.143 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:18:53.143 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:18:53.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:53.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:53.151 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:18:53.623 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:18:54.101 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:18:54.579 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:18:54.970 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:18:55.063 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:18:55.542 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:18:55.932 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:18:56.020 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:18:56.492 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:18:56.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:18:56.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:18:56.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:18:56.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:18:56.886 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:18:56.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:18:56.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:18:56.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:18:56.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:18:56.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:18:56.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:18:56.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:18:56.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:18:56.899 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:18:56.899 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:18:56.899 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:18:56.899 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3455 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3455 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3455 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3455 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:18:56.900 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3456 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:01.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:19:01.903 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:19:01.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:01.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:01.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:01.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:01.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:01.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:19:01.913 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:01.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:19:01.914 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:19:01.918 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:19:01.918 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:19:01.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:19:01.919 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:01.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:01.919 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:19:01.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:19:01.919 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:19:01.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:01.922 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:19:01.922 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:19:01.923 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:19:01.923 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:01.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:01.924 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:19:01.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:19:01.924 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:19:01.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:01.925 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:19:01.925 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:19:01.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:19:01.926 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:01.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:01.926 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:19:01.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:19:01.926 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:19:01.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:19:01.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:19:01.930 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:19:01.930 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:19:01.930 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:01.935 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:19:02.418 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:19:02.457 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:19:02.459 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:02.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:02.462 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:19:02.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:02.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:02.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:02.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:02.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:02.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:02.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:02.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:02.509 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:02.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:02.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:02.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:02.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:02.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:02.894 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:19:02.896 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:02.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:02.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:02.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:02.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:03.371 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:19:03.387 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:03.389 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:19:03.849 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:19:03.874 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:03.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:03.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:03.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:03.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:04.327 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:19:04.360 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:04.803 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:19:04.847 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:04.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:04.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:04.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:04.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:05.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:19:05.334 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:05.758 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:19:05.820 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:05.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:05.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:06.236 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:19:06.306 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:06.714 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:19:06.794 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:06.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:06.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:06.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:06.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:07.192 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:19:07.282 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:07.670 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:19:07.769 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:08.148 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:19:08.256 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:08.626 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:19:08.743 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:09.103 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:19:09.230 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:09.576 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:19:09.708 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:10.049 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:19:10.190 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:10.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:10.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:10.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:10.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:10.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:10.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:10.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:10.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:10.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:10.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:10.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:10.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:10.281 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:10.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:10.295 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:19:10.295 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:19:10.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:10.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:10.527 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:19:10.923 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:11.005 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:19:11.409 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:11.483 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:19:11.895 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:11.960 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:19:12.382 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:12.429 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:19:12.857 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:12.898 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:19:13.338 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:13.376 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:19:13.826 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:13.854 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:19:14.313 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:14.327 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:19:14.791 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:14.796 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:19:15.265 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:19:15.268 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:15.734 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:19:15.748 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:16.204 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:19:16.228 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:16.676 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:19:16.708 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:17.147 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:19:17.188 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:17.616 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:19:17.668 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:18.087 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:19:18.148 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:18.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:18.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:18.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:18.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:18.155 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:19:18.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:18.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:18.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:18.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:18.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:18.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:18.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:18.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:18.175 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:18.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:18.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:18.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:18.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:18.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:18.522 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:18.563 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:19:18.997 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:18.998 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:19:19.039 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:19:19.475 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:19.512 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:19:19.946 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:19.990 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:19:20.425 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:20.467 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:19:20.903 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:20.944 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:19:21.380 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:21.421 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:19:21.856 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:21.898 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:19:22.334 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:22.377 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:19:22.812 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:22.855 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:19:23.290 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:23.332 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:19:23.768 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:23.809 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:19:24.244 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:24.286 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:19:24.722 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:24.764 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:19:25.199 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:25.241 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:19:25.676 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:25.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:25.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:25.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:25.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:25.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:25.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:25.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:25.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:25.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:25.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:25.687 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:25.687 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:25.709 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:25.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:25.713 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:19:25.713 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:19:25.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:25.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:25.714 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:19:26.103 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:26.184 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:19:26.573 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:26.661 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:19:27.050 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:27.050 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:19:27.137 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:19:27.528 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:27.615 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:19:28.005 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:28.084 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:19:28.472 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:28.558 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:19:28.947 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:28.950 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:19:29.036 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:19:29.426 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:29.515 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:19:29.905 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:29.908 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:19:29.993 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:19:30.383 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:30.471 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:19:30.860 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:30.862 [DEBUG] fake_trx.py:269 (MS@172.18.40.22:6700) Recv SETTA cmd
2026-03-02 03:19:30.950 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:19:31.339 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:31.428 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:19:31.819 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:31.906 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:19:32.296 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:32.380 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:19:32.765 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:32.857 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:19:33.246 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:33.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:33.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:33.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:33.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:33.255 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:19:33.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:33.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:33.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:33.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:33.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:33.269 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:33.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:33.269 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:19:33.269 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:19:33.269 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:19:33.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:33.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:33.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=6721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:38.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:19:38.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:19:38.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:38.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:38.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:38.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:38.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:38.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:19:38.274 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:38.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:19:38.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:19:38.275 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:19:38.275 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:19:38.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:38.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:19:38.276 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:19:38.276 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:19:38.276 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:38.276 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:19:38.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:38.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:19:38.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:19:38.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:19:38.278 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:19:38.278 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:19:38.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:38.279 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:19:38.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:19:38.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:19:38.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:19:38.279 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:19:38.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:19:38.280 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:19:38.280 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:19:38.280 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:38.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:38.284 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:19:38.762 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:19:38.803 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:19:38.805 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:38.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:38.807 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:19:38.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:38.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:38.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:38.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:38.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:38.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:38.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:38.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:38.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:38.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:38.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:38.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:38.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:39.237 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:19:39.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:39.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:39.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:39.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:39.715 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:19:40.193 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:19:40.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:40.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:40.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:40.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:40.670 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:19:40.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:40.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:40.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:40.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:40.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:40.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:40.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:40.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:40.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:40.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:40.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:40.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:41.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:41.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:41.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:41.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:41.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:41.145 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:19:41.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:41.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:41.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:41.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:41.623 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:19:42.101 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:19:42.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:42.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:42.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:42.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:42.579 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:19:43.056 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:19:43.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:43.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:43.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:43.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:43.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:43.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:43.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:43.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:43.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:43.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:43.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:43.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:43.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:43.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:43.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:43.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:43.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:43.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:43.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:43.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:43.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:43.531 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:19:44.009 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:19:44.487 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:19:44.960 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:19:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:45.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:45.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:45.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:45.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:45.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:45.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:45.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:45.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:45.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:45.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:45.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:45.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:19:45.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:19:45.312 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1506 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:50.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:19:50.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:19:50.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:50.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:50.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:50.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:50.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:50.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:19:50.322 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:50.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:19:50.322 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:19:50.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:19:50.323 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:19:50.323 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:19:50.323 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:50.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:50.323 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:19:50.323 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:19:50.323 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:19:50.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:50.324 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:19:50.324 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:19:50.324 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:19:50.324 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:50.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:50.325 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:19:50.325 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:19:50.325 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:19:50.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:19:50.327 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:19:50.327 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:19:50.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:19:50.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:19:50.331 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:19:50.331 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:19:50.331 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:19:50.336 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:19:50.817 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:19:50.851 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:19:50.853 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:19:50.854 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:19:50.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:50.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:50.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:50.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:50.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:50.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:50.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:50.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:50.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:50.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:50.922 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:19:50.922 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:19:50.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:50.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:51.294 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:19:51.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:51.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:51.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:51.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:51.772 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:19:52.251 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:19:52.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:52.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:52.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:52.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:52.729 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:19:53.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:53.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:53.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:53.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:53.029 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:19:53.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:53.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:53.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:19:53.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:53.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:19:53.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:19:53.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:19:53.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:19:53.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:53.061 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:19:53.061 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:19:53.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:53.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:53.205 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:19:53.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:53.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:53.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:53.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:53.674 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:19:54.144 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:19:54.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:54.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:54.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:54.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:54.612 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:19:55.085 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:19:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:19:55.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:19:55.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:19:55.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:19:55.168 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:19:55.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:19:55.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:19:55.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:19:55.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:19:55.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:19:55.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:19:55.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:19:55.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:19:55.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:19:55.182 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:19:55.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:19:55.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:55.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:55.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:55.182 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:55.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:55.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:19:55.183 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1042 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:00.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:00.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:00.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:00.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:00.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:00.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:00.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:00.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:00.192 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:00.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:00.193 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:00.195 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:00.195 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:00.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:00.196 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:00.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:00.197 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:00.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:00.197 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:00.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:00.198 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:00.198 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:00.198 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:00.198 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:00.199 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:00.199 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:00.199 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:00.199 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:00.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:00.200 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:00.200 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:00.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:00.201 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:00.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:00.201 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:00.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:00.201 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:00.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:00.204 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:00.204 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:00.204 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:00.209 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:00.689 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:00.719 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:00.719 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:00.719 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:00.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:00.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:00.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:00.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:00.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:00.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:00.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:00.728 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:00.728 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:00.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:00.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:00.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:00.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:00.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:01.157 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:01.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:01.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:01.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:01.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:01.632 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:02.109 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:20:02.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:02.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:02.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:02.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:02.584 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:20:02.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:02.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:02.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:02.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:02.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:02.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:02.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:02.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:02.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:02.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:02.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:02.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:02.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:02.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:02.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:02.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:02.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:03.059 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:20:03.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:03.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:03.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:03.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:03.538 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:20:04.015 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:20:04.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:04.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:04.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:04.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:04.493 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:20:04.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:04.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:04.971 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:20:04.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:04.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:04.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:04.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:04.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:04.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:04.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:04.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:04.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:04.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:05.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:05.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:05.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:05.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:05.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:05.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:05.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:05.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:05.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:05.448 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:20:05.926 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:20:06.404 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:20:06.881 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:20:07.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:07.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:07.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:07.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:07.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:07.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:07.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:07.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:07.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:07.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:07.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:07.139 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:07.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:07.139 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:07.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:07.139 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:12.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:12.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:12.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:12.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:12.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:12.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:12.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:12.156 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:12.157 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:12.157 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:12.157 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:12.159 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:12.159 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:12.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:12.159 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:12.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:12.160 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:12.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:12.160 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:12.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:12.161 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:12.161 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:12.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:12.163 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:12.163 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:12.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:12.166 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:12.166 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:12.166 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:12.170 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:12.654 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:12.694 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:12.696 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:12.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:12.697 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:12.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:12.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:12.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:12.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:12.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:12.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:12.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:12.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:12.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:12.759 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:20:12.759 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:20:12.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:12.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:13.132 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:13.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:13.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:13.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:13.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:13.610 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:14.082 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:20:14.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:14.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:14.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:14.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:14.553 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:20:14.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:14.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:14.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:14.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:14.853 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:20:14.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:14.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:14.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:14.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:14.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:14.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:14.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:14.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:14.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:14.879 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:20:14.879 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:20:14.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:14.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:15.024 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:20:15.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:15.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:15.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:15.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:15.494 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:20:15.970 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:20:16.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:16.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:16.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:16.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:16.448 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:20:16.927 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:20:16.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:16.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:16.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:16.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:16.972 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:20:16.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:16.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:16.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:16.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:16.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:16.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:16.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:16.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:16.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:16.983 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:16.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:16.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1033 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:16.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1033 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:16.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:16.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:16.983 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:21.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:21.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:21.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:21.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:21.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:21.991 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:22.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:22.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:22.008 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:22.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:22.009 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:22.012 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:22.013 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:22.013 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:22.013 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:22.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:22.013 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:22.013 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:22.013 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:22.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:22.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:22.016 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:22.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:22.018 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:22.018 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:22.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:22.018 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:22.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:22.018 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:22.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:22.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:22.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:22.021 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:22.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:22.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:22.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:22.021 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:22.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:22.022 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:22.022 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:22.022 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:22.027 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:22.511 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:22.557 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:22.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:22.560 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:22.563 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:22.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:22.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:22.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:22.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:22.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:22.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:22.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:22.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:22.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:22.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:22.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:22.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:22.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:22.988 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:23.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:23.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:23.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:23.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:23.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:23.943 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:20:24.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:24.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:24.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:24.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:24.421 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:20:24.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:24.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:24.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:24.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:24.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:24.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:24.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:24.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:24.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:24.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:24.774 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:24.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.775 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=587 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=588 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=588 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=588 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=588 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=588 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:24.776 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=588 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:29.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:29.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:29.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:29.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:29.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:29.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:29.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:29.787 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:29.787 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:29.787 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:29.787 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:29.790 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:29.790 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:29.791 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:29.791 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:29.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:29.791 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:29.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:29.792 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:29.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:29.793 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:29.793 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:29.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:29.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:29.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:29.794 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:29.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:29.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:29.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:29.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:29.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:29.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:29.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:29.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:29.795 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:29.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:29.795 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:29.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:29.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:29.799 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:29.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:29.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:30.286 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:30.331 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:30.333 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:30.334 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:30.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:30.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:30.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:30.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:30.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:30.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:30.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:30.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:30.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:30.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:30.392 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:20:30.392 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:20:30.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:30.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:30.762 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:30.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:30.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:30.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:30.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:31.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:31.705 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:20:31.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:31.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:31.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:31.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:32.177 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:20:32.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:32.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:32.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:32.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:32.596 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:20:32.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:32.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:32.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:32.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:32.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:32.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:32.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:32.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:32.609 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:32.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:32.609 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:32.609 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:32.610 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:32.610 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:32.610 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:32.610 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:32.610 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:37.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:37.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:37.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:37.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:37.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:37.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:37.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:37.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:37.619 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:37.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:37.619 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:37.622 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:37.622 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:37.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:37.623 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:37.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:37.623 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:37.624 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:37.624 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:37.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:37.625 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:37.625 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:37.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:37.625 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:37.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:37.625 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:37.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:37.625 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:37.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:37.627 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:37.627 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:37.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:37.627 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:37.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:37.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:37.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:37.628 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:37.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:37.630 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:37.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:37.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:37.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:37.630 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:37.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:37.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:37.631 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:37.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:37.636 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:38.119 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:38.165 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:38.166 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:38.167 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:38.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:38.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:38.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:38.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:38.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:38.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:38.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:38.222 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:38.222 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:38.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:38.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:38.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:38.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:38.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:38.595 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:38.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:38.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:38.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:38.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:38.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:38.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:38.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:38.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:38.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:38.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:38.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:38.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:38.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:38.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:38.673 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:38.673 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:38.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:38.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:38.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:38.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:38.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:39.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:39.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:39.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:39.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:39.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:39.072 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:39.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:39.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:39.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:39.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:39.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:39.074 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:39.074 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:39.074 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:39.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:39.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:44.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:44.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:44.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:44.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:44.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:44.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:44.089 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:44.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:44.090 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:44.090 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:44.090 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:44.092 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:44.092 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:44.092 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:44.092 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:44.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:44.093 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:44.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:44.093 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:44.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:44.095 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:44.095 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:44.096 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:44.096 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:44.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:44.096 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:44.096 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:44.096 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:44.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:44.098 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:44.098 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:44.098 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:44.099 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:44.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:44.099 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:44.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:44.099 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:44.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:44.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:44.103 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:44.103 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:44.103 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:44.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:44.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:44.108 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:44.587 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:44.629 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:44.630 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:44.630 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:44.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:44.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:44.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:44.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:44.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:44.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:44.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:44.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:44.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:44.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:44.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:44.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:44.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:44.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:45.063 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:45.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:45.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:45.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:45.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:45.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:45.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:45.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:45.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:45.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:45.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:45.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:45.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:45.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:45.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:45.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:45.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:45.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:45.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:45.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:45.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:45.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:45.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:45.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:45.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:45.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:45.539 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:45.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:45.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:45.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:45.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:45.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:45.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:45.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:45.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:45.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:45.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:45.549 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:45.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.549 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.550 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.550 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.550 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:45.550 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=310 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:20:50.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:50.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:50.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:50.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:50.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:50.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:50.560 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:50.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:50.562 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:50.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:50.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:50.569 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:50.570 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:50.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:50.570 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:50.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:50.571 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:50.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:50.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:50.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:50.574 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:50.574 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:50.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:50.575 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:50.575 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:50.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:50.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:50.575 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:50.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:50.581 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:50.581 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:50.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:50.581 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:50.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:50.582 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:50.582 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:50.582 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:50.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:50.586 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:50.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:50.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:50.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:50.587 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:50.587 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:50.587 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:50.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:50.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:50.592 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:51.071 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:51.119 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:51.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:51.122 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:51.126 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:51.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:51.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:51.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:51.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:51.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:51.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:51.201 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:51.201 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:51.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:51.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:51.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:51.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:51.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:51.549 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:51.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:51.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:51.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:51.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:51.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:51.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:51.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:51.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:51.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:51.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:51.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:51.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:51.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:51.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:51.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:51.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:51.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:51.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:51.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:51.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:52.025 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:52.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:52.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:52.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:52.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:52.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:52.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:52.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:52.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:52.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:52.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:52.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:52.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:52.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:52.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:52.080 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:20:57.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:20:57.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:20:57.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:57.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:57.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:57.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:57.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:20:57.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:57.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:57.094 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:20:57.094 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:20:57.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:20:57.098 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:20:57.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:57.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:20:57.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:20:57.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:20:57.099 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:20:57.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:57.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:20:57.101 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:20:57.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:57.102 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:57.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:20:57.103 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:20:57.103 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:20:57.103 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:20:57.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:57.104 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:20:57.104 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:20:57.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:57.104 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:20:57.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:20:57.105 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:20:57.105 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:20:57.105 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:20:57.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:20:57.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:20:57.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:20:57.109 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:20:57.109 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:20:57.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:20:57.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:20:57.114 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:20:57.593 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:20:57.644 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:20:57.646 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:20:57.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:57.650 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:20:57.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:20:57.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:20:57.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:20:57.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:57.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:20:57.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:20:57.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:20:57.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:20:57.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:20:57.740 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:20:57.740 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:20:57.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:57.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:20:58.070 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:20:58.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:58.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:58.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:58.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:58.547 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:20:59.025 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:20:59.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:20:59.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:20:59.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:20:59.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:20:59.503 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:20:59.980 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:21:00.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:00.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:00.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:00.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:00.451 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:21:00.921 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:21:01.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:01.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:01.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:01.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:01.390 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:21:01.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:01.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:01.745 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:21:01.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:01.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:01.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:01.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:01.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:01.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:01.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:01.750 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:01.750 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:01.750 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:01.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:01.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=998 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:06.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:06.753 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:06.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:06.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:06.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:06.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:06.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:06.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:06.769 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:06.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:06.769 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:06.771 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:06.771 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:06.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:06.771 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:06.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:06.772 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:06.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:06.772 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:06.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:06.773 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:06.773 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:06.774 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:06.774 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:06.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:06.774 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:06.774 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:06.774 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:06.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:06.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:06.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:06.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:06.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:06.777 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:06.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:06.777 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:06.777 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:06.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:06.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:06.781 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:06.781 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:06.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:06.786 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:07.266 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:07.302 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:07.303 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:07.304 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:07.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:07.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:07.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:07.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:07.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:07.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:07.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:07.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:07.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:07.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:07.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:07.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:07.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:07.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:07.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:07.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:07.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:07.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:07.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:07.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:07.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:07.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:07.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:07.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:07.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.740 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:07.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:07.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:07.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:07.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:07.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:07.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:07.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:07.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:07.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:07.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:07.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:07.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:07.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:07.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:07.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:07.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:07.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:07.919 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:07.920 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:07.920 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:07.920 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:07.920 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:07.920 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:07.920 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=245 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:12.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:12.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:12.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:12.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:12.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:12.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:12.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:12.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:12.926 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:12.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:12.926 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:12.928 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:12.928 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:12.928 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:12.928 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:12.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:12.929 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:12.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:12.929 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:12.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:12.931 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:12.931 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:12.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:12.933 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:12.933 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:12.933 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:12.933 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:12.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:12.934 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:12.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:12.934 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:12.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:12.936 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:12.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:12.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:12.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.937 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:12.937 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:12.937 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:12.937 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:12.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:12.942 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:13.423 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:13.471 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:13.473 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:13.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:13.476 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:13.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:13.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:13.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:13.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:13.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:13.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:13.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:13.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:13.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:13.616 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:21:13.616 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:21:13.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:13.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:13.900 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:13.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:13.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:13.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:13.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:14.378 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:21:14.856 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:21:14.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:14.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:14.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:14.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:15.334 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:21:15.813 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:21:15.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:15.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:15.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:15.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:16.291 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:21:16.769 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:21:16.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:16.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:16.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:16.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:17.248 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:21:17.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:17.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:17.621 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:21:17.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:17.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:17.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:17.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:17.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:17.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:17.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:17.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:17.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:17.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:17.627 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:17.627 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:22.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:22.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:22.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:22.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:22.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:22.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:22.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:22.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:22.640 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:22.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:22.641 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:22.643 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:22.643 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:22.643 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:22.644 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:22.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:22.644 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:22.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:22.645 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:22.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:22.646 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:22.646 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:22.647 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:22.647 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:22.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:22.647 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:22.647 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:22.647 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:22.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:22.648 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:22.648 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:22.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:22.649 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:22.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:22.649 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:22.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:22.649 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:22.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:22.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:22.653 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:22.653 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:22.653 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:22.658 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:23.142 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:23.181 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:23.183 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:23.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:23.186 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:23.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:23.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:23.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:23.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:23.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:23.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:23.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:23.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:23.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:23.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:23.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:23.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:23.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:23.619 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:23.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:23.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:23.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:23.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:24.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:24.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:24.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:24.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:24.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:24.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:24.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:24.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:24.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:24.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:24.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:24.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:24.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:24.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:24.014 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:29.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:29.017 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:29.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:29.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:29.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:29.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:29.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:29.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:29.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:29.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:29.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:29.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:29.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:29.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:29.038 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:29.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:29.039 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:29.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:29.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:29.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:29.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:29.041 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:29.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:29.041 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:29.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:29.042 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:29.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:29.043 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:29.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:29.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:29.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:29.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:29.044 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:29.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:29.044 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:29.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:29.044 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:29.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:29.047 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:29.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:29.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:29.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:29.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:29.048 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:29.049 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:29.053 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:29.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:29.579 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:29.581 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:29.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:29.582 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:29.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:29.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:29.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:29.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:29.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:29.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:29.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:29.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:29.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:29.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:29.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:29.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:29.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:30.012 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:30.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:30.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:30.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:30.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:30.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:30.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:30.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:30.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:30.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:30.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:30.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:30.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:30.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:30.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:30.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:30.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:30.416 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:30.416 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:30.416 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.417 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.418 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.418 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.418 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:30.418 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:35.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:35.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:35.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:35.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:35.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:35.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:35.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:35.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:35.429 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:35.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:35.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:35.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:35.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:35.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:35.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:35.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:35.436 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:35.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:35.436 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:35.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:35.438 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:35.438 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:35.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:35.438 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:35.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:35.438 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:35.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:35.439 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:35.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:35.441 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:35.441 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:35.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:35.444 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:35.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:35.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:35.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:35.444 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.445 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:35.445 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:35.445 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:35.445 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:35.450 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:35.931 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:35.982 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:35.984 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:35.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:35.986 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:36.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:36.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:36.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:36.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:36.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:36.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:36.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:36.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:36.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:36.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:36.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:36.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:36.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:36.407 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:36.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:36.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:36.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:36.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:36.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:36.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:36.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:36.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:36.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:36.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:36.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:36.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:36.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:36.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:36.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:36.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:36.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:36.815 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:36.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:36.816 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:36.816 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:36.816 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:36.816 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:36.816 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:36.816 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:36.817 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:41.814 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:41.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:41.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:41.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:41.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:41.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:41.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:41.830 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:41.830 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:41.830 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:41.830 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:41.832 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:41.832 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:41.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:41.834 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:41.834 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:41.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:41.835 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:41.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:41.835 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:41.835 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:41.835 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:41.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:41.837 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:41.837 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:41.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:41.839 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:41.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:41.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:41.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:41.839 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:41.840 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:41.840 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:41.840 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:41.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:41.845 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:42.330 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:42.364 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:42.365 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:42.366 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:42.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:42.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:42.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:42.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:42.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:42.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:42.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:42.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:42.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:42.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:42.478 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:21:42.479 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:21:42.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:42.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:42.808 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:42.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:42.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:42.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:42.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:43.286 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:21:43.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:43.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:43.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:43.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:43.344 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:21:43.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:43.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:43.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:43.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:43.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:43.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:43.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:43.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:43.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:43.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:43.355 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:43.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:43.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:43.355 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:43.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:43.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:43.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:43.356 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:48.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:48.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:48.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:48.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:48.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:48.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:48.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:48.369 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:48.369 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:48.369 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:48.369 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:48.371 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:48.371 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:48.371 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:48.371 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:48.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:48.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:48.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:48.372 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:48.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:48.373 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:48.373 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:48.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:48.375 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:48.375 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:48.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:48.377 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:48.378 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:48.378 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:48.378 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:48.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:48.383 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:48.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:48.908 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:48.910 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:48.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:48.912 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:48.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:48.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:48.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:48.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:48.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:48.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:48.977 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:48.978 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:49.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:49.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:49.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:49.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:49.341 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:49.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:49.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:49.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:49.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:49.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:49.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:49.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:49.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:49.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:49.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:49.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:49.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:49.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:49.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:49.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:49.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:49.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:49.750 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:49.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:49.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.750 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:49.751 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:54.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:54.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:54.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:54.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:54.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:54.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:54.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:54.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:54.767 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:54.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:21:54.767 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:54.769 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:21:54.769 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:21:54.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:54.771 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:21:54.771 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:21:54.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:54.773 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:21:54.773 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:21:54.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:54.775 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:21:54.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:21:54.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:21:54.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:21:54.776 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:21:54.776 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:21:54.776 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:21:54.781 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:21:55.264 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:21:55.305 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:21:55.307 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:21:55.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:55.309 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:21:55.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:55.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:55.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:21:55.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:55.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:21:55.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:21:55.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:21:55.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:21:55.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:55.412 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:21:55.412 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:21:55.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:55.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:55.742 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:21:55.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:55.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:55.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:55.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:56.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:21:56.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:21:56.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:21:56.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:21:56.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:21:56.280 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:21:56.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:21:56.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:21:56.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:21:56.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:21:56.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:21:56.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:21:56.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:21:56.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:21:56.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:21:56.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:21:56.293 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:21:56.293 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:56.293 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:56.293 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:56.293 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:56.294 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:21:56.294 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:01.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:01.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:01.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:01.296 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:01.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:01.296 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:01.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:01.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:01.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:01.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:01.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:22:01.307 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:22:01.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:22:01.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:01.308 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:01.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:01.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:22:01.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:01.309 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:22:01.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:01.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:22:01.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:22:01.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:01.312 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:01.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:01.312 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:22:01.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:01.312 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:22:01.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:01.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:22:01.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:22:01.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:01.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:01.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:01.315 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:22:01.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:01.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:22:01.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:22:01.319 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:22:01.319 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:22:01.319 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:01.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:22:01.808 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:22:01.839 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:22:01.840 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:22:01.841 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:22:01.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:01.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:01.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:01.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:22:01.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:01.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:01.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:01.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:22:01.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:22:02.285 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:22:02.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:02.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:02.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:02.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:02.762 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:22:02.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:03.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:03.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:03.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:03.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:03.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:03.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:22:03.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:03.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:03.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:03.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:22:03.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:22:03.237 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:22:03.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:03.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:03.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:03.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:03.714 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:22:04.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:22:04.193 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:22:04.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:22:04.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:04.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:04.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:04.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:04.240 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:04.241 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:09.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:09.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:09.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:09.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:09.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:09.248 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:09.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:09.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:09.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:09.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:09.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:22:09.258 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:22:09.258 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:22:09.258 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:09.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:09.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:09.259 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:22:09.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:09.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:22:09.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:09.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:22:09.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:22:09.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:09.262 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:09.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:09.262 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:22:09.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:09.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:22:09.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:09.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:22:09.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:22:09.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:09.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:09.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:09.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:22:09.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:09.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:22:09.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:09.269 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:22:09.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:22:09.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:22:09.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:22:09.269 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.270 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:22:09.270 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:22:09.270 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:22:09.271 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:09.275 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:22:09.759 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:22:09.794 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:22:09.795 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:22:09.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:09.796 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:22:09.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:09.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:09.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:22:09.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:09.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:09.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:09.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:22:09.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:22:10.235 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:22:10.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:10.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:10.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:10.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:10.712 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:22:11.189 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:22:11.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:11.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:11.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:11.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:11.667 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:22:12.144 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:22:12.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:12.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:12.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:12.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:12.622 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:22:13.100 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:22:13.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:13.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:13.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:13.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:13.578 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:22:14.056 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:22:14.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:14.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:14.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:14.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:14.533 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:22:14.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:22:14.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:14.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:14.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:14.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:15.002 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:22:15.471 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:22:15.939 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:22:16.408 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:22:16.879 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:22:17.348 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:22:17.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:17.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:17.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:17.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:17.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:17.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:17.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:17.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:17.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:17.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:17.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:17.521 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:22:17.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:22.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:22.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:22.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:22.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:22.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:22.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:22.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:22.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:22.526 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:22.526 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:22.526 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:22.526 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:22:22.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:22.527 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:22.527 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:22:22.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:22.528 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:22.528 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:22:22.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:22:22.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:22:22.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:22:22.530 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:22:22.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:22.535 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:22:23.016 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:22:23.052 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:22:23.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:23.055 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:22:23.057 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:22:23.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:23.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:23.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:22:23.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:23.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:23.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:23.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:22:23.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:22:23.491 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:22:23.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:23.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:23.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:23.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:23.969 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:22:24.447 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:22:24.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:24.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:24.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:24.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:24.924 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:22:25.403 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:22:25.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:25.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:25.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:25.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:25.880 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:22:26.358 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:22:26.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:26.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:26.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:26.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:26.835 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:22:27.312 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:22:27.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:27.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:27.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:27.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:27.786 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:22:28.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:22:28.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:28.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:28.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:28.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:28.264 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:22:28.738 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:22:29.207 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:22:29.677 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:22:30.145 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:22:30.614 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:22:31.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:31.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:31.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:31.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:31.015 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:22:36.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:36.017 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:36.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:36.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:36.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:36.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:36.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:36.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:36.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:36.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:36.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:22:36.038 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:22:36.038 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:22:36.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:36.039 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:36.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:36.039 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:22:36.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:36.039 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:22:36.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:36.042 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:22:36.042 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:22:36.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:36.042 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:36.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:36.043 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:22:36.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:36.043 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:22:36.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:36.045 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:22:36.045 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:22:36.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:36.045 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:36.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:36.045 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:22:36.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:36.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:22:36.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:22:36.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:22:36.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:22:36.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:22:36.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:36.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:22:36.540 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:22:36.575 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:22:36.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:36.578 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:22:36.578 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:22:36.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:36.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:36.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:22:36.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:36.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:36.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:36.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:22:36.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:22:37.017 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:22:37.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:37.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:37.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:37.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:37.494 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:22:37.972 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:22:38.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:38.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:38.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:38.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:38.449 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:22:38.926 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:22:39.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:39.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:39.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:39.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:39.404 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:22:39.882 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:22:40.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:40.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:40.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:40.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:40.354 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:22:40.831 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:22:41.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:41.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:41.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:41.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:41.309 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:22:41.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:22:41.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:41.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:41.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:41.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:41.786 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:22:42.261 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:22:42.730 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:22:43.199 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:22:43.670 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:22:44.147 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:22:44.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:44.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:44.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:44.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:44.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:44.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:44.311 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:22:44.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1771 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:44.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1771 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:44.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1771 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:44.311 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1771 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:22:49.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:49.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:49.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:49.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:49.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:49.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:49.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:49.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:49.339 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:49.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:22:49.340 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:22:49.345 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:22:49.345 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:22:49.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:49.346 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:49.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:49.346 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:22:49.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:22:49.346 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:22:49.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:49.350 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:22:49.350 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:22:49.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:49.350 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:49.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:49.351 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:22:49.351 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:22:49.351 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:22:49.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:49.354 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:22:49.354 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:22:49.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:49.354 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:22:49.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:22:49.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:22:49.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:22:49.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:22:49.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:49.358 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:22:49.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:22:49.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:22:49.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:22:49.358 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:22:49.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:22:49.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:22:49.360 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:22:49.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:22:49.838 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:22:49.879 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:22:49.879 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:22:49.880 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:22:49.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:22:49.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:49.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:49.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:22:49.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:49.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:49.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:49.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:22:49.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:22:50.310 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:22:50.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:50.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:50.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:50.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:50.788 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:22:51.265 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:22:51.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:51.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:51.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:51.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:51.743 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:22:52.220 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:22:52.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:52.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:52.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:52.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:52.697 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:22:53.175 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:22:53.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:53.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:53.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:53.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:53.652 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:22:54.130 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:22:54.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:54.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:54.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:54.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:54.607 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:22:54.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:22:54.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:22:54.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:22:54.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:54.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:22:55.085 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:22:55.562 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:22:56.038 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:22:56.506 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:22:56.976 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:22:57.447 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:22:57.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:22:57.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:22:57.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:22:57.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:22:57.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:22:57.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:22:57.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:22:57.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:22:57.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:22:57.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:22:57.840 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:22:57.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:22:57.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:02.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:02.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:02.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:02.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:02.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:02.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:02.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:02.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:02.855 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:02.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:02.855 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:23:02.858 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:23:02.859 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:23:02.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:02.859 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:02.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:02.859 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:23:02.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:02.859 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:23:02.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:02.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:02.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:23:02.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:02.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:23:02.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:23:02.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:02.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:02.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:02.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:23:02.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:02.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:23:02.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:23:02.868 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:23:02.868 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:23:02.868 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:02.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:02.873 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:23:03.356 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:23:03.397 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:23:03.400 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:23:03.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:23:03.402 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:23:03.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:23:03.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:23:03.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:23:03.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:23:03.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:23:03.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:23:03.431 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:23:03.431 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:23:03.831 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:23:03.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:03.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:03.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:03.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:04.308 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:23:04.786 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:23:04.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:04.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:04.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:04.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:05.261 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:23:05.739 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:23:05.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:05.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:05.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:05.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:06.216 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:23:06.694 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:23:06.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:06.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:06.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:06.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:07.172 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:23:07.649 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:23:07.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:07.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:07.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:07.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:08.127 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:23:08.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD NOHANDOVER
2026-03-02 03:23:08.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:23:08.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:23:08.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:23:08.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:23:08.598 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:23:09.069 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:23:09.538 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:23:10.006 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:23:10.475 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:23:10.944 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:23:11.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:23:11.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:23:11.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:11.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:11.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:11.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:11.124 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:11.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:11.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:11.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:11.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:11.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:11.124 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (TRX3@172.18.40.20:5700/3) RX TRXD message (ver=1 fn=1775 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:11.124 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1775 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:16.125 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:16.125 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:16.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:16.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:16.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:16.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:16.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:16.140 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:16.140 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:16.141 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:16.141 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:23:16.144 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:23:16.145 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:23:16.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:16.145 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:16.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:16.146 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:23:16.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:16.147 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:23:16.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:16.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:23:16.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:23:16.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:16.149 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:16.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:16.149 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:23:16.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:16.149 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:23:16.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:16.151 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:23:16.152 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:23:16.152 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:16.152 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:16.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:16.152 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:23:16.152 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:16.152 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:23:16.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:16.155 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:23:16.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.156 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:23:16.156 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:23:16.156 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:23:16.157 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:16.161 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:23:16.643 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:23:16.673 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:23:16.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:23:16.674 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:23:16.675 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:23:17.111 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:23:17.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:17.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:17.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:17.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:17.580 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:23:18.048 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:23:18.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:18.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:18.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:18.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:18.520 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:23:19.001 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:23:19.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:19.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:19.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:19.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:19.482 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:23:19.952 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:23:20.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:20.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:20.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:20.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:20.420 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:23:20.893 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:23:21.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:21.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:21.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:21.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:21.375 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:23:21.858 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:23:22.339 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:23:22.820 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:23:23.302 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:23:23.779 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:23:24.257 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:23:24.735 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:23:25.206 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:23:25.674 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:23:26.143 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:23:26.614 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:23:26.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:26.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:26.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:26.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:26.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:26.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:26.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:26.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:26.687 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:23:26.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:26.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:26.687 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:31.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:31.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:31.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:31.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:31.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:31.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:31.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:31.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:31.691 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:31.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:31.691 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:31.692 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:31.692 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:23:31.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:31.693 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:31.693 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:31.693 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:31.693 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:23:31.694 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:31.694 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:23:31.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:23:31.695 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:23:31.695 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:23:31.695 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:31.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:31.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:31.696 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:23:36.700 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:36.700 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:36.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:36.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:36.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:36.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:36.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:36.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:36.711 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:36.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:36.712 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:23:36.714 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:23:36.715 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:23:36.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:36.715 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:36.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:36.716 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:23:36.717 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:36.717 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:23:36.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:36.717 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:23:36.718 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:23:36.718 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:36.718 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:36.718 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:36.718 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:23:36.718 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:36.718 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:23:36.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:36.720 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:23:36.720 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:23:36.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:36.720 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:36.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:36.720 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:23:36.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:36.721 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:23:36.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:36.723 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:23:36.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:23:36.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:23:36.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:23:36.723 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:23:36.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:23:36.724 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:23:36.724 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:23:36.724 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:36.729 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:23:37.212 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:23:37.258 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:23:37.260 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:23:37.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:23:37.262 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:23:37.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:23:37.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:23:37.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:23:37.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:23:37.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:23:37.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:23:37.266 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:23:37.266 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:23:37.689 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:23:37.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:37.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:37.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:37.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:38.163 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:23:38.639 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:23:38.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:38.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:38.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:38.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:39.117 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:23:39.595 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:23:39.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:39.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:39.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:39.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:40.072 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:23:40.550 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:23:40.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:40.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:40.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:40.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:41.028 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:23:41.506 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:23:41.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:41.731 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:41.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:41.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:41.983 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:23:42.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:23:42.939 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:23:43.417 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:23:43.894 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:23:44.372 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:23:44.849 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:23:45.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:23:45.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:23:45.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:45.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:45.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:45.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:45.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:45.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:45.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:45.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:45.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:45.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:45.312 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:45.312 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:23:50.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:50.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:50.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:50.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:50.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:50.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:50.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:50.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:50.327 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:50.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:50.327 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:23:50.329 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:23:50.329 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:23:50.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:50.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:50.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:50.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:23:50.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:50.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:23:50.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:50.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:23:50.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:23:50.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:50.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:50.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:50.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:23:50.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:50.333 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:23:50.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:50.334 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:23:50.334 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:23:50.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:50.334 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:50.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:50.335 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:23:50.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:50.335 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:23:50.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:50.337 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:23:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:23:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:23:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:23:50.337 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:23:50.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:23:50.338 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:23:50.338 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:23:50.338 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:23:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:50.340 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:50.340 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:50.340 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:23:55.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:23:55.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:23:55.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:55.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:55.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:55.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:55.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:23:55.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:55.357 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:55.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:23:55.357 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:23:55.360 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:23:55.360 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:23:55.361 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:55.361 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:55.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:23:55.362 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:23:55.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:23:55.363 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:23:55.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:55.364 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:23:55.364 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:23:55.364 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:55.365 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:55.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:23:55.365 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:23:55.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:23:55.365 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:23:55.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:55.367 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:23:55.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:23:55.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:55.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:23:55.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:23:55.368 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:23:55.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:23:55.368 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:23:55.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:55.371 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.372 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:23:55.372 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:23:55.372 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:23:55.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:23:55.377 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:23:55.861 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:23:55.902 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:23:55.904 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:23:55.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:23:55.905 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:23:55.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:23:55.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:23:55.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:23:55.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:23:55.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:23:55.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:23:55.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:23:55.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:23:56.336 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:23:56.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:56.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:56.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:56.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:56.811 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:23:57.289 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:23:57.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:57.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:57.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:57.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:57.767 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:23:58.240 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:23:58.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:58.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:58.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:58.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:58.718 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:23:59.191 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:23:59.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:23:59.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:23:59.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:23:59.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:23:59.669 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:24:00.145 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:24:00.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:00.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:00.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:00.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:00.622 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:24:01.098 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:24:01.589 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:24:02.061 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:24:02.538 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:24:03.014 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:24:03.493 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:24:03.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:24:03.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:24:03.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:03.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:03.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:03.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:03.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:03.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:03.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:03.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:03.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:03.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:03.963 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:24:03.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:03.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:03.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:03.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:03.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:03.963 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:08.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:08.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:08.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:08.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:08.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:08.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:08.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:08.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:08.973 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:08.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:08.974 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:24:08.976 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:24:08.977 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:24:08.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:08.977 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:08.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:08.978 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:24:08.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:08.978 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:24:08.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:08.979 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:24:08.979 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:24:08.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:08.979 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:08.980 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:08.980 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:24:08.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:08.980 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:24:08.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:08.981 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:24:08.981 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:24:08.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:08.981 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:08.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:08.981 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:24:08.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:08.981 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:24:08.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:08.983 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:24:08.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:24:08.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:24:08.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:24:08.983 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:24:08.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:24:08.984 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:24:08.984 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:24:08.984 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:08.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:08.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:08.985 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:24:13.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:13.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:13.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:14.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:14.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:14.008 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:14.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:14.008 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:24:14.012 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:24:14.012 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:24:14.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:14.013 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:14.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:14.013 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:24:14.013 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:14.013 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:24:14.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:14.015 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:24:14.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:24:14.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:14.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:14.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:14.017 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:24:14.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:14.017 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:24:14.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:14.018 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:24:14.018 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:24:14.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:14.018 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:14.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:14.019 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:24:14.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:14.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:24:14.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.022 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:24:14.022 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:24:14.022 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:24:14.023 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:14.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:14.027 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:24:14.510 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:24:14.553 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:24:14.554 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:24:14.556 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:24:14.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:24:14.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:24:14.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:24:14.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:24:14.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:24:14.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:24:14.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:24:14.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:24:14.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:24:14.985 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:24:15.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:15.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:15.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:15.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:15.462 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:24:15.939 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:24:16.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:16.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:16.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:16.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:16.416 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:24:16.893 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:24:17.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:17.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:17.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:17.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:17.369 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:24:17.846 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:24:18.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:18.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:18.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:18.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:18.323 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:24:18.801 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:24:19.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:19.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:19.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:19.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:19.278 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:24:19.755 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:24:20.232 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:24:20.710 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:24:21.186 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:24:21.663 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:24:22.140 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:24:22.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:24:22.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:24:22.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:22.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:22.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:22.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:22.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:22.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:22.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:22.612 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:22.612 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:22.612 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:24:22.612 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:22.612 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:27.612 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:27.612 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:27.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:27.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:27.617 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:27.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:27.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:27.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:27.624 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:27.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:27.625 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:24:27.627 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:24:27.628 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:24:27.628 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:27.628 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:27.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:27.629 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:24:27.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:27.629 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:24:27.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:27.631 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:24:27.631 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:24:27.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:27.631 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:27.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:27.631 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:24:27.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:27.632 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:24:27.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:27.634 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:24:27.634 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:24:27.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:27.634 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:27.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:27.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:24:27.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:27.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:24:27.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:24:27.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:24:27.638 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:24:27.639 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:27.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:27.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:27.641 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:24:32.644 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:32.644 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:32.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:32.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:32.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:32.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:32.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:32.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:32.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:32.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:32.661 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:24:32.663 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:24:32.663 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:24:32.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:32.663 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:32.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:32.664 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:24:32.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:32.664 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:24:32.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:32.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:32.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:24:32.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:32.666 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:24:32.666 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:24:32.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:32.667 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:32.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:32.667 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:24:32.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:32.667 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:24:32.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.669 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:24:32.669 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:24:32.669 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:24:32.670 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:32.674 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:24:33.156 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:24:33.184 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:24:33.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:24:33.185 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:24:33.186 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:24:33.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:24:33.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:24:33.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:24:33.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:24:33.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:24:33.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:24:33.187 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:24:33.187 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:24:33.629 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:24:33.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:33.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:33.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:33.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:34.107 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:24:34.581 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:24:34.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:34.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:34.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:34.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:35.059 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:24:35.536 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:24:35.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:35.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:35.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:35.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:36.014 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:24:36.490 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:24:36.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:36.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:36.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:36.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:36.967 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:24:37.445 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:24:37.676 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:37.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:37.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:37.679 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:37.922 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:24:38.399 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:24:38.876 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:24:39.353 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:24:39.830 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:24:40.307 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:24:40.785 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:24:41.202 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:24:41.202 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:24:41.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:41.205 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:41.205 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:41.205 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:41.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1827 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:24:46.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:46.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:46.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:46.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:46.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:46.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:46.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:46.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:46.211 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:46.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:46.211 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:46.212 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:46.212 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:24:46.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:46.213 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:46.213 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:46.213 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:24:46.214 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:24:46.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:46.214 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:46.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:46.214 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:24:46.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:46.214 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:24:46.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:24:46.215 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:24:46.215 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:24:46.215 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:46.216 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:46.216 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:46.216 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:24:51.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:24:51.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:24:51.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:51.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:51.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:51.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:51.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:24:51.235 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:51.235 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:51.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:24:51.236 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:24:51.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:24:51.240 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:24:51.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:51.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:51.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:24:51.241 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:24:51.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:24:51.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:24:51.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:51.245 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:24:51.245 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:24:51.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:51.246 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:51.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:24:51.246 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:24:51.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:24:51.246 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:24:51.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:51.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:24:51.249 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:24:51.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:51.249 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:24:51.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:24:51.249 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:24:51.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:24:51.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:24:51.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:51.252 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:24:51.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:24:51.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.253 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:24:51.253 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:24:51.253 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:24:51.254 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:24:51.258 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:24:51.740 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:24:51.785 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:24:51.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:24:51.787 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:24:51.790 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:24:51.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:24:51.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:24:51.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:24:51.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:24:51.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:24:51.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:24:51.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:24:51.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:24:52.218 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:24:52.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:52.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:52.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:52.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:52.692 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:24:53.167 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:24:53.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:53.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:53.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:53.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:53.644 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:24:54.117 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:24:54.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:54.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:54.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:54.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:54.595 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:24:55.067 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:24:55.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:55.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:55.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:55.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:55.545 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:24:56.021 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:24:56.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:24:56.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:24:56.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:24:56.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:24:56.498 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:24:56.976 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:24:57.452 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:24:57.930 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:24:58.407 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:24:58.884 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:24:59.361 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:24:59.838 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:25:00.316 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:25:00.790 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:25:01.268 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:25:01.744 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:25:02.221 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:25:02.699 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:25:03.176 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:25:03.654 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:25:04.131 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:25:04.609 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:25:05.085 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:25:05.563 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:25:05.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:25:05.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:05.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:05.838 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:05.838 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:25:10.841 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:10.841 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:10.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:10.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:10.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:10.845 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:10.851 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:10.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:10.852 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:10.852 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:10.852 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:25:10.856 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:25:10.857 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:25:10.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:10.857 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:10.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:10.858 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:25:10.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:10.859 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:25:10.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:10.860 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:25:10.861 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:25:10.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:10.861 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:10.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:10.861 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:25:10.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:10.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:25:10.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:10.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:25:10.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:25:10.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:10.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:10.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:10.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:25:10.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:10.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:25:10.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:25:10.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:25:10.869 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:25:10.869 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:25:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:10.871 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:10.871 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:10.871 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:25:15.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:15.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:15.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:15.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:15.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:15.873 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:15.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:15.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:15.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:15.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:15.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:15.878 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:15.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:15.878 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:15.879 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:15.879 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:25:15.879 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:15.879 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:15.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:15.880 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:25:15.880 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:15.880 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:25:15.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:25:15.881 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:25:15.881 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:25:15.881 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:15.886 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:25:16.369 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:25:16.403 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:25:16.405 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:25:16.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:25:16.407 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:25:16.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:25:16.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:25:16.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:25:16.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:25:16.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:25:16.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:25:16.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:25:16.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:25:16.846 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:25:16.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:16.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:16.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:16.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:17.322 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:25:17.800 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:25:17.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:17.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:17.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:17.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:18.275 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:25:18.752 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:25:18.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:18.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:18.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:18.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:19.229 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:25:19.706 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:25:19.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:19.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:19.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:19.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:20.184 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:25:20.660 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:25:20.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:20.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:21.138 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:25:21.630 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:25:22.108 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:25:22.585 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:25:23.058 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:25:23.532 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:25:24.008 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:25:24.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:25:24.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:24.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:24.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:24.466 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:24.467 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:25:29.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:29.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:29.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:29.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:29.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:29.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:29.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:29.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:29.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:29.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:29.472 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:29.473 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:29.473 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:25:29.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:29.475 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:29.475 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:25:29.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:29.476 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:29.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:25:29.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:29.478 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:25:29.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:25:29.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:25:29.478 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:25:29.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:25:29.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:25:29.479 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:25:29.479 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:25:29.479 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:29.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:29.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:29.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:29.480 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:25:34.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:34.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:34.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:34.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:34.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:34.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:34.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:34.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:34.494 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:34.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:34.494 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:25:34.498 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:25:34.498 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:25:34.499 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:34.499 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:34.499 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:34.500 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:25:34.500 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:34.501 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:25:34.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:34.502 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:25:34.503 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:25:34.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:34.503 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:34.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:34.504 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:25:34.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:34.504 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:25:34.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:34.507 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:25:34.507 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:25:34.508 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:34.508 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:34.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:34.508 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:25:34.508 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:34.508 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:25:34.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:25:34.513 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:25:34.513 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:25:34.513 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:34.518 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:25:34.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:25:35.045 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:25:35.047 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:25:35.049 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:25:35.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:25:35.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:25:35.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:25:35.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:25:35.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:25:35.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:25:35.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:25:35.052 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:25:35.052 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:25:35.476 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:25:35.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:35.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:35.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:35.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:35.950 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:25:36.427 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:25:36.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:36.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:36.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:36.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:36.904 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:25:37.381 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:25:37.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:37.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:37.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:37.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:37.859 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:25:38.334 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:25:38.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:38.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:38.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:38.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:38.810 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:25:39.287 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:25:39.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:39.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:39.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:39.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:39.762 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:25:40.239 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:25:40.712 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:25:41.190 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:25:41.666 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:25:42.144 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:25:42.621 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:25:43.098 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:25:43.576 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:25:44.052 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:25:44.530 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:25:45.007 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:25:45.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:25:45.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:25:45.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:45.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:45.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:45.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:45.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:45.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:45.103 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:45.103 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:45.103 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:25:50.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:50.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:50.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:50.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:50.105 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:50.105 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:50.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:50.113 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:50.113 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:50.114 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:50.114 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:25:50.118 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:25:50.119 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:25:50.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:50.119 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:50.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:50.119 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:25:50.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:50.119 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:25:50.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:50.123 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:25:50.123 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:25:50.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:50.124 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:50.124 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:25:50.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:50.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:50.124 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:25:50.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:50.128 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:25:50.128 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:25:50.128 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:50.128 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:50.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:50.129 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:25:50.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:50.129 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:25:50.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:25:50.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:25:50.134 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:25:50.134 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:25:50.134 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:50.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:50.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:50.136 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:25:55.139 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:25:55.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:25:55.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:55.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:55.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:55.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:55.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:25:55.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:55.154 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:55.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:25:55.154 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:25:55.157 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:25:55.158 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:25:55.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:55.158 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:55.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:25:55.159 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:25:55.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:25:55.160 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:25:55.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:55.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:25:55.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:25:55.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:55.161 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:55.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:25:55.162 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:25:55.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:25:55.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:25:55.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:55.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:25:55.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:25:55.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:55.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:25:55.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:25:55.164 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:25:55.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:25:55.165 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:25:55.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:25:55.169 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:25:55.169 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:25:55.169 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:25:55.174 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:25:55.656 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:25:55.696 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:25:55.698 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:25:55.700 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:25:55.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:25:55.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:25:55.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:25:55.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:25:55.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:25:55.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:25:55.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:25:55.703 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:25:55.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:25:56.132 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:25:56.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:56.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:56.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:56.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:56.609 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:25:57.085 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:25:57.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:57.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:57.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:57.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:57.562 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:25:58.036 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:25:58.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:58.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:58.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:58.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:58.515 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:25:58.991 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:25:59.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:25:59.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:25:59.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:25:59.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:25:59.467 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:25:59.944 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:26:00.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:00.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:00.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:00.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:00.421 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:26:00.899 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:26:01.375 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:26:01.862 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:26:02.339 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:26:02.817 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:26:03.292 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:26:03.769 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:26:04.247 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:26:04.723 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:26:05.201 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:26:05.679 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:26:06.152 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:26:06.629 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:26:06.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:26:06.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:26:06.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:06.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:06.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:06.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:06.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:06.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:06.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:06.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:06.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:06.759 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:26:06.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:06.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:11.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:11.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:11.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:11.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:11.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:11.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:11.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:11.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:11.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:11.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:11.774 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:26:11.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:26:11.778 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:26:11.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:11.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:11.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:11.780 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:26:11.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:11.780 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:26:11.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:11.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:26:11.782 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:26:11.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:11.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:11.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:11.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:26:11.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:11.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:26:11.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:11.784 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:26:11.784 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:26:11.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:11.785 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:11.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:11.785 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:26:11.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:11.785 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:26:11.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:26:11.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:26:11.789 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:26:11.789 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:26:11.789 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:26:11.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:11.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:11.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:11.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:11.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:11.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:11.792 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:26:16.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:16.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:16.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:16.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:16.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:16.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:16.804 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:16.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:16.806 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:16.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:16.806 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:26:16.812 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:26:16.812 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:26:16.812 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:16.812 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:16.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:16.813 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:26:16.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:16.813 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:26:16.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:16.816 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:26:16.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:26:16.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:16.817 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:16.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:16.817 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:26:16.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:16.817 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:26:16.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:16.820 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:26:16.820 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:26:16.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:16.820 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:16.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:16.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:26:16.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:16.821 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:26:16.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:26:16.826 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:26:16.826 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:26:16.826 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:16.831 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:26:17.313 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:26:17.365 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:26:17.367 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:26:17.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:26:17.369 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:26:17.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:26:17.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:26:17.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:26:17.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:26:17.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:26:17.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:26:17.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:26:17.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:26:17.789 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:26:17.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:17.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:17.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:17.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:18.266 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:26:18.744 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:26:18.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:18.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:18.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:18.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:19.218 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:26:19.696 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:26:19.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:19.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:19.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:19.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:20.170 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:26:20.648 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:26:20.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:20.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:20.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:20.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:21.125 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:26:21.600 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:26:21.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:21.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:21.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:21.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:22.078 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:26:22.550 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:26:23.028 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:26:23.504 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:26:23.981 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:26:24.458 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:26:24.936 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:26:25.413 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:26:25.892 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:26:26.369 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:26:26.846 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:26:27.324 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:26:27.798 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:26:28.276 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:26:28.753 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:26:29.230 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:26:29.707 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:26:30.184 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:26:30.661 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:26:31.137 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:26:31.615 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:26:32.093 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:26:32.569 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:26:33.046 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:26:33.523 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:26:34.001 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:26:34.476 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:26:34.954 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:26:35.430 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:26:35.907 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:26:36.384 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:26:36.859 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:26:37.337 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:26:37.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:26:37.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:26:37.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:37.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:37.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:37.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:37.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:37.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:37.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:37.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:37.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:37.419 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:26:37.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:37.420 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4406 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:37.420 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4406 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:42.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:42.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:42.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:42.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:42.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:42.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:42.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:42.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:42.431 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:42.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:42.431 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:26:42.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:26:42.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:26:42.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:42.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:42.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:42.436 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:26:42.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:42.436 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:26:42.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:42.437 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:26:42.438 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:26:42.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:42.438 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:42.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:42.438 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:26:42.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:42.439 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:26:42.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:42.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:42.442 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:42.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:26:42.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:26:42.448 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:26:42.448 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:42.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:42.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:42.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:42.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:42.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:42.451 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:42.451 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:42.451 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:26:47.454 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:47.454 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:47.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:47.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:47.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:47.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:47.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:47.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:47.501 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:47.502 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:26:47.502 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:26:47.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:26:47.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:26:47.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:47.508 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:47.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:47.509 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:26:47.509 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:26:47.510 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:26:47.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:47.512 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:26:47.512 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:26:47.513 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:47.513 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:47.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:47.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:26:47.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:26:47.515 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:26:47.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:47.517 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:26:47.517 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:26:47.517 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:47.518 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:26:47.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:47.518 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:26:47.518 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:26:47.518 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:26:47.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:47.522 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:26:47.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:26:47.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:26:47.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:26:47.522 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.523 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:26:47.524 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:26:47.524 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:26:47.524 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:26:47.528 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:26:48.013 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:26:48.061 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:26:48.062 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:26:48.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:26:48.064 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:26:48.493 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:26:48.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:48.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:48.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:48.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:48.972 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:26:49.450 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:26:49.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:49.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:49.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:49.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:49.928 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:26:50.406 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:26:50.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:50.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:50.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:50.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:50.884 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:26:51.362 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:26:51.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:51.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:51.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:51.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:51.840 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:26:52.318 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:26:52.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:52.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:52.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:52.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:52.796 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:26:53.274 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:26:53.746 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:26:54.222 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:26:54.703 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:26:55.185 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:26:55.663 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:26:56.145 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:26:56.626 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:26:57.106 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:26:57.588 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:26:58.066 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:26:58.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:26:58.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:26:58.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:26:58.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:26:58.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:26:58.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:26:58.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:26:58.078 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:26:58.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:26:58.078 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:26:58.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:26:58.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:58.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:58.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:58.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:58.079 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:58.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:26:58.080 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2248 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:03.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:03.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:03.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:03.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:03.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:03.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:03.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:03.092 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:03.092 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:03.092 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:03.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:27:03.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:27:03.097 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:27:03.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:03.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:03.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:03.099 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:27:03.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:03.099 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:27:03.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:03.101 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:03.101 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:27:03.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:03.103 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:27:03.104 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:27:03.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:03.104 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:03.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:03.104 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:27:03.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:03.104 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:27:03.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:27:03.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:27:03.108 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:27:03.108 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:27:03.108 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:03.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:03.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:03.110 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:27:08.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:08.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:08.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:08.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:08.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:08.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:08.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:08.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:08.145 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:08.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:08.146 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:27:08.150 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:27:08.150 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:27:08.151 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:08.151 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:08.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:08.152 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:27:08.153 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:08.153 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:27:08.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:08.155 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:27:08.155 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:27:08.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:08.155 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:08.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:08.156 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:27:08.156 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:08.156 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:27:08.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:08.159 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:27:08.159 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:27:08.159 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:08.159 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:08.160 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:08.160 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:27:08.160 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:08.160 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:27:08.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:27:08.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:27:08.165 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:27:08.165 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:27:08.165 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:08.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:08.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:08.170 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:27:08.650 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:27:08.705 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:27:08.708 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:27:08.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:27:08.710 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:27:09.125 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:27:09.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:09.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:09.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:09.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:09.602 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:27:10.080 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:27:10.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:10.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:10.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:10.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:10.558 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:27:11.039 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:27:11.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:11.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:11.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:11.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:11.517 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:27:11.997 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:27:12.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:12.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:12.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:12.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:12.475 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:27:12.953 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:27:13.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:13.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:13.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:13.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:13.432 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:27:13.913 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:27:14.392 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:27:14.870 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:27:15.348 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:27:15.828 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:27:16.308 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:27:16.786 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:27:17.264 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:27:17.745 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:27:18.226 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:27:18.707 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:27:19.187 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:27:19.665 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:27:20.144 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:27:20.625 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:27:20.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:20.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:20.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:20.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:20.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:20.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:20.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:20.728 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:20.728 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:20.728 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:20.728 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:27:20.728 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2676 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:20.728 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2676 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:20.728 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2676 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:20.728 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2676 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:20.728 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2676 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:20.728 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2676 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:25.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:25.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:25.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:25.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:25.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:25.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:25.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:25.747 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:25.747 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:25.747 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:25.747 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:27:25.751 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:27:25.752 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:27:25.752 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:25.752 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:25.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:25.753 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:27:25.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:25.753 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:27:25.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:25.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:27:25.754 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:27:25.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:25.754 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:25.754 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:25.754 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:27:25.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:25.755 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:27:25.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:25.756 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:27:25.757 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:27:25.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:25.757 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:25.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:25.757 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:27:25.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:25.757 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:27:25.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.760 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:27:25.760 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:27:25.760 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:27:25.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.761 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:27:25.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:27:25.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:25.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:25.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:25.762 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:27:30.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:30.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:30.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:30.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:30.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:30.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:30.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:30.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:30.780 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:30.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:30.780 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:27:30.784 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:27:30.784 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:27:30.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:30.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:30.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:30.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:27:30.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:30.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:27:30.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:30.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:27:30.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:27:30.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:30.788 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:30.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:30.788 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:27:30.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:30.788 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:27:30.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:30.790 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:27:30.790 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:27:30.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:30.790 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:30.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:30.790 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:27:30.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:30.790 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:27:30.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:27:30.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:27:30.794 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:27:30.794 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:27:30.794 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:30.799 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:27:31.282 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:27:31.320 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:27:31.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:27:31.323 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:27:31.327 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:27:31.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:27:31.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:27:31.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:27:31.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:27:31.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:27:31.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:27:31.331 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:27:31.331 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:27:31.372 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:27:31.372 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:27:31.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:27:31.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:27:31.760 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:27:31.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:31.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:31.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:31.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:32.238 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:27:32.716 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:27:32.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:32.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:32.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:32.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:33.194 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:27:33.672 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:27:33.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:33.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:33.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:33.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:34.149 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:27:34.627 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:27:34.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:34.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:34.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:34.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:35.105 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:27:35.584 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:27:35.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:35.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:35.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:35.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:36.062 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:27:36.540 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:27:37.018 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:27:37.496 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:27:37.974 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:27:38.448 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:27:38.925 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:27:39.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:27:39.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:27:39.378 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:27:39.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:39.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:39.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:39.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:39.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:39.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:39.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:39.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:39.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:39.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:39.386 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:27:39.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:39.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:39.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:39.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:39.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:39.386 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:44.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:44.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:44.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:44.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:44.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:44.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:44.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:44.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:44.396 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:44.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:44.396 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:27:44.400 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:27:44.400 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:27:44.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:44.400 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:44.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:44.401 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:27:44.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:44.401 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:27:44.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:44.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:27:44.404 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:27:44.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:44.404 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:44.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:44.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:27:44.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:44.404 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:27:44.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:44.407 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:44.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:27:44.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:44.410 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:27:44.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:27:44.411 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:27:44.412 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:44.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:44.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:44.414 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:27:49.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:49.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:49.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:49.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:49.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:49.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:49.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:49.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:49.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:49.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:27:49.433 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:27:49.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:27:49.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:27:49.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:49.438 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:49.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:49.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:27:49.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:27:49.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:27:49.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:49.440 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:27:49.440 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:27:49.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:49.441 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:49.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:49.441 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:27:49.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:27:49.441 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:27:49.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:49.443 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:27:49.443 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:27:49.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:49.443 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:27:49.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:49.444 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:27:49.444 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:27:49.444 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:27:49.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:27:49.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:27:49.448 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:27:49.448 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:27:49.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:27:49.937 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:27:49.981 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:27:49.983 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:27:49.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:27:49.984 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:27:49.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:27:49.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:27:49.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:27:49.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:27:49.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:27:49.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:27:49.987 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:27:49.987 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:27:50.027 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:27:50.027 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:27:50.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:27:50.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:27:50.415 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:27:50.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:50.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:50.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:50.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:50.893 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:27:51.371 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:27:51.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:51.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:51.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:51.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:51.849 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:27:52.327 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:27:52.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:52.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:52.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:52.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:52.805 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:27:53.283 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:27:53.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:53.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:53.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:53.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:53.761 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:27:54.238 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:27:54.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:54.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:54.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:54.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:54.717 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:27:55.194 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:27:55.672 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:27:56.151 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:27:56.629 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:27:57.107 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:27:57.585 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:27:58.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:27:58.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:27:58.033 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:27:58.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:27:58.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:27:58.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:27:58.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:27:58.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:27:58.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:27:58.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:27:58.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:27:58.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:27:58.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:27:58.040 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:27:58.040 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:03.039 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:03.039 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:03.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:03.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:03.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:03.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:03.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:03.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:03.049 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:03.050 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:03.050 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:28:03.053 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:28:03.053 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:28:03.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:03.053 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:03.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:03.053 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:28:03.054 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:03.054 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:28:03.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:03.056 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:28:03.057 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:28:03.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:03.057 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:03.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:03.057 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:28:03.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:03.057 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:28:03.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:03.060 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:03.060 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:28:03.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:28:03.065 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:28:03.065 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:28:03.065 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:03.067 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:03.067 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:03.067 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:28:08.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:08.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:08.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:08.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:08.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:08.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:08.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:08.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:08.082 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:08.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:08.082 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:28:08.084 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:28:08.085 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:28:08.085 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:08.085 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:08.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:08.086 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:28:08.086 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:08.086 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:28:08.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:08.087 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:28:08.087 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:28:08.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:08.087 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:08.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:08.087 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:28:08.088 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:08.088 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:28:08.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:08.089 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:08.089 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:28:08.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.092 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:28:08.092 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:28:08.093 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:28:08.093 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:08.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:08.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:08.097 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:28:08.578 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:28:08.620 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:28:08.622 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:28:08.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:28:08.623 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:28:08.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:28:08.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:28:08.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:28:08.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:08.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:28:08.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:28:08.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:28:08.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:28:08.668 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:28:08.668 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:28:08.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:08.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:09.055 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:28:09.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:09.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:09.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:09.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:09.532 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:28:10.011 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:28:10.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:10.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:10.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:10.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:10.488 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:28:10.966 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:28:11.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:11.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:11.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:11.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:11.444 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:28:11.922 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:28:12.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:12.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:12.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:12.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:12.400 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:28:12.878 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:28:13.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:13.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:13.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:13.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:13.355 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:28:13.833 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:28:14.311 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:28:14.789 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:28:15.267 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:28:15.745 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:28:16.223 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:28:16.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:28:16.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:28:16.672 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:28:16.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:16.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:16.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:16.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:16.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:16.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:16.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:16.679 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:16.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:16.679 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:28:16.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:21.679 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:21.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:21.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:21.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:21.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:21.684 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:21.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:21.687 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:21.687 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:21.687 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:21.687 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:28:21.689 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:28:21.689 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:28:21.689 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:21.689 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:21.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:21.689 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:28:21.690 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:21.690 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:28:21.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:21.692 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:21.692 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:28:21.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:21.694 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:28:21.694 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:28:21.694 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:21.694 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:21.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:21.694 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:28:21.694 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:21.694 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:28:21.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:28:21.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:28:21.698 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:28:21.698 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:28:21.698 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:21.700 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:21.700 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:21.700 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:28:26.706 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:26.706 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:26.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:26.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:26.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:26.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:26.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:26.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:26.718 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:26.718 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:26.718 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:28:26.723 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:28:26.723 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:28:26.723 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:26.723 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:26.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:26.723 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:28:26.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:26.724 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:28:26.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:26.726 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:28:26.727 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:28:26.727 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:26.727 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:26.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:26.728 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:28:26.728 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:26.728 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:28:26.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:26.729 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:28:26.730 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:28:26.730 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:26.730 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:26.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:26.730 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:28:26.730 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:26.730 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:28:26.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:28:26.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:28:26.734 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:28:26.734 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:28:26.734 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:26.739 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:28:27.222 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:28:27.259 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:28:27.260 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:28:27.261 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:28:27.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:28:27.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:28:27.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:28:27.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:28:27.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:27.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:28:27.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:28:27.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:28:27.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:28:27.312 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:28:27.312 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:28:27.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:27.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:27.699 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:28:27.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:27.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:27.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:27.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:28.177 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:28:28.655 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:28:28.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:28.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:28.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:28.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:29.134 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:28:29.612 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:28:29.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:29.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:29.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:29.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:30.090 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:28:30.568 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:28:30.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:30.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:30.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:30.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:31.046 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:28:31.525 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:28:31.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:31.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:31.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:31.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:32.002 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:28:32.480 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:28:32.958 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:28:33.436 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:28:33.914 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:28:34.392 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:28:34.870 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:28:35.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:28:35.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:28:35.317 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:28:35.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:35.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:35.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:35.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:35.322 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:35.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:35.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:35.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:35.322 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:35.322 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:35.322 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:35.322 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1833 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:40.325 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:40.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:40.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:40.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:40.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:40.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:40.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:40.339 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:40.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:40.339 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:28:40.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:28:40.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:28:40.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:40.343 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:40.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:40.344 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:28:40.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:40.344 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:28:40.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:40.346 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:28:40.346 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:28:40.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:40.346 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:40.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:40.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:28:40.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:40.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:28:40.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:40.348 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:40.348 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:28:40.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.351 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:28:40.351 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:28:40.351 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:28:40.352 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:28:40.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:28:40.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:40.353 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:40.353 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:40.353 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:28:45.356 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:45.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:45.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:45.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:45.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:45.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:45.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:45.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:45.367 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:45.368 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:28:45.368 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:28:45.371 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:28:45.371 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:28:45.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:45.372 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:45.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:45.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:28:45.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:28:45.373 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:28:45.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:45.374 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:28:45.374 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:28:45.374 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:45.374 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:45.374 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:45.375 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:28:45.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:28:45.375 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:28:45.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:45.376 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:28:45.376 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:28:45.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:45.376 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:28:45.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:45.376 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:28:45.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:28:45.376 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:28:45.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.379 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:28:45.380 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:28:45.380 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:28:45.380 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:28:45.385 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:28:45.868 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:28:45.907 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:28:45.908 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:28:45.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:28:45.909 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:28:45.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:28:45.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:28:45.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:28:45.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:45.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:28:45.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:28:45.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:28:45.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:28:45.958 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:28:45.958 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:28:45.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:45.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:28:46.346 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:28:46.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:46.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:46.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:46.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:46.823 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:28:47.302 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:28:47.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:47.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:47.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:47.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:47.779 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:28:48.257 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:28:48.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:48.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:48.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:48.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:48.735 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:28:49.213 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:28:49.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:49.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:49.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:49.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:49.691 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:28:50.168 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:28:50.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:50.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:50.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:50.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:50.646 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:28:51.124 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:28:51.602 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:28:52.079 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:28:52.558 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:28:53.036 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:28:53.514 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:28:53.991 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:28:54.469 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:28:54.947 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:28:55.425 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:28:55.903 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:28:56.381 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:28:56.859 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:28:57.337 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:28:57.815 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:28:58.294 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:28:58.771 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:28:59.249 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:28:59.727 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:28:59.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:28:59.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:28:59.963 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:28:59.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:28:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:28:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:28:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:28:59.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:28:59.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:28:59.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:28:59.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:28:59.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:28:59.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:28:59.971 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:28:59.971 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:04.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:04.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:04.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:04.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:04.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:04.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:04.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:04.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:04.978 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:04.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:04.978 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:29:04.980 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:29:04.980 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:29:04.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:04.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:04.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:04.981 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:29:04.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:04.982 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:29:04.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:04.982 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:29:04.982 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:29:04.982 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:04.982 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:04.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:04.983 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:29:04.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:04.983 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:29:04.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:04.984 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:04.984 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:29:04.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:04.986 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:29:04.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:29:04.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:29:04.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:29:04.986 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:29:04.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:29:04.987 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:29:04.987 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:29:04.987 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:04.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:04.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:04.988 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:29:09.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:09.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:09.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:09.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:09.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:09.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:10.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:10.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:10.004 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:10.004 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:10.004 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:29:10.006 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:29:10.007 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:29:10.007 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:10.007 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:10.007 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:10.008 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:29:10.008 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:10.008 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:29:10.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:10.009 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:10.009 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:29:10.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:10.011 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:10.011 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:29:10.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:29:10.014 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:29:10.014 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:29:10.014 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:29:10.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:10.019 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:29:10.504 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:29:10.543 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:29:10.544 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:29:10.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:29:10.546 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:29:10.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:29:10.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:29:10.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:29:10.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:10.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:29:10.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:29:10.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:29:10.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:29:10.594 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:29:10.594 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:29:10.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:10.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:10.981 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:29:11.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:11.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:11.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:11.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:11.459 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:29:11.949 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:29:12.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:12.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:12.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:12.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:12.427 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:29:12.905 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:29:13.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:13.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:13.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:13.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:13.383 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:29:13.861 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:29:14.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:14.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:14.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:14.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:14.338 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:29:14.816 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:29:15.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:15.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:15.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:15.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:15.294 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:29:15.772 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:29:16.250 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:29:16.728 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:29:17.206 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:29:17.683 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:29:18.162 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:29:18.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:29:18.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:29:18.599 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:29:18.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:18.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:18.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:18.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:18.604 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:18.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:18.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:18.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:18.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:18.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:18.604 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:29:23.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:23.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:23.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:23.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:23.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:23.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:23.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:23.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:23.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:23.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:23.614 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:29:23.620 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:29:23.620 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:29:23.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:23.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:23.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:29:23.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:23.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:23.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:29:23.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:23.624 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:29:23.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:29:23.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:23.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:23.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:23.625 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:29:23.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:23.625 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:29:23.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:23.627 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:29:23.627 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:29:23.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:23.627 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:23.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:23.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:29:23.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:23.628 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:29:23.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:29:23.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:29:23.632 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:29:23.632 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:29:23.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:29:23.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:23.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:23.635 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:23.635 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:23.635 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:29:28.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:28.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:28.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:28.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:28.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:28.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:28.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:28.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:28.652 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:28.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:28.652 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:29:28.655 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:29:28.655 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:29:28.656 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:28.656 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:28.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:28.657 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:29:28.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:28.657 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:29:28.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:28.658 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:29:28.658 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:29:28.658 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:28.658 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:28.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:28.659 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:29:28.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:28.659 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:29:28.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:28.660 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:29:28.660 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:29:28.660 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:28.660 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:28.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:28.661 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:29:28.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:28.661 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:29:28.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:29:28.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:29:28.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:29:28.664 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:29:28.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:28.669 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:29:29.152 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:29:29.189 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:29:29.191 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:29:29.192 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:29:29.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:29:29.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:29:29.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:29:29.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:29:29.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:29.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:29:29.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:29:29.195 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:29:29.195 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:29:29.629 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:29:29.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:29.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:29.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:29.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:30.107 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:29:30.584 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:29:30.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:30.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:30.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:30.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:31.062 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:29:31.540 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:29:31.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:31.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:31.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:31.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:32.018 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:29:32.495 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:29:32.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:32.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:32.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:32.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:32.972 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:29:33.449 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:29:33.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:33.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:33.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:33.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:33.927 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:29:34.405 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:29:34.883 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:29:35.361 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:29:35.839 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:29:36.316 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:29:36.794 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:29:37.271 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:29:37.748 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:29:38.226 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:29:38.703 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:29:39.181 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:29:39.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:29:39.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:29:39.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:39.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:39.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:39.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:39.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:39.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:39.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:39.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:39.252 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:39.252 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:39.252 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:29:39.252 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:39.252 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:39.252 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:39.252 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:39.252 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:39.252 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:29:44.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:44.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:44.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:44.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:44.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:44.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:44.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:44.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:44.264 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:44.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:44.264 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:29:44.267 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:29:44.267 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:29:44.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:44.268 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:44.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:44.269 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:29:44.269 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:44.269 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:29:44.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:44.271 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:29:44.271 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:29:44.271 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:44.271 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:44.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:44.271 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:29:44.272 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:44.272 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:29:44.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:44.273 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:44.273 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:29:44.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:29:44.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:29:44.276 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:29:44.276 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:29:44.276 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:44.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:44.277 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:44.277 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:29:49.280 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:29:49.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:29:49.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:49.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:49.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:49.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:49.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:29:49.291 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:49.291 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:49.292 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:29:49.292 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:29:49.294 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:29:49.294 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:29:49.295 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:49.295 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:49.295 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:29:49.296 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:29:49.296 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:29:49.296 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:29:49.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:49.297 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:29:49.297 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:29:49.297 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:49.297 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:49.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:29:49.297 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:29:49.298 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:29:49.298 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:29:49.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:49.300 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:29:49.300 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:29:49.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:29:49.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:29:49.304 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:29:49.304 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:29:49.304 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:29:49.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:29:49.309 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:29:49.792 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:29:49.830 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:29:49.832 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:29:49.833 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:29:49.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:29:49.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:29:49.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:29:49.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:29:49.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:49.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:29:49.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:29:49.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:29:49.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:29:49.882 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:29:49.882 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-02 03:29:49.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:49.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:29:50.261 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:29:50.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:50.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:50.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:50.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:50.738 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:29:51.217 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:29:51.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:51.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:51.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:51.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:51.694 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:29:52.172 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:29:52.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:52.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:52.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:52.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:52.650 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:29:53.128 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:29:53.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:53.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:53.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:53.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:53.606 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:29:54.083 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:29:54.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:29:54.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:29:54.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:29:54.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:29:54.561 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:29:55.039 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:29:55.517 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:29:55.995 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:29:56.474 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:29:56.952 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:29:57.429 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:29:57.908 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:29:58.386 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:29:58.863 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:29:59.341 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:29:59.819 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:30:00.297 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:30:00.775 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:30:00.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:30:00.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:30:00.887 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:30:00.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:00.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:00.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:00.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:00.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:00.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:00.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:00.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:00.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:00.893 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:30:00.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:05.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:05.892 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:05.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:05.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:05.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:05.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:05.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:05.899 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:05.899 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:05.899 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:05.899 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:05.900 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:05.900 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:30:05.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:05.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:30:05.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:30:05.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:05.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:05.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:05.902 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:30:05.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:05.902 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:30:05.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:05.902 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:30:05.903 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:30:05.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:05.903 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:05.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:05.903 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:30:05.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:05.903 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:30:05.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:30:05.905 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:30:05.905 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:30:05.905 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:05.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:05.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:05.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:05.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:05.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:05.906 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:05.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:05.907 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:30:10.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:10.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:10.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:10.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:10.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:10.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:10.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:10.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:10.932 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:10.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:10.933 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:30:10.937 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:30:10.937 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:30:10.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:10.937 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:10.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:10.938 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:30:10.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:10.938 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:30:10.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:10.941 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:30:10.941 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:30:10.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:10.942 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:10.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:10.942 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:30:10.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:10.942 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:30:10.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:10.944 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:30:10.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:30:10.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:10.945 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:10.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:10.945 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:30:10.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:10.945 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:30:10.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:30:10.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:30:10.948 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:30:10.948 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:30:10.948 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:10.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:10.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:30:11.429 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:30:11.478 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:30:11.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:30:11.482 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:30:11.485 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:30:11.905 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:30:11.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:11.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:11.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:11.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:12.382 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:30:12.860 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:30:12.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:12.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:12.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:12.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:13.339 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:30:13.817 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:30:13.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:13.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:13.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:13.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:14.298 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:30:14.779 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:30:14.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:14.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:14.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:14.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:15.253 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:30:15.732 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:30:15.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:15.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:15.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:15.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:16.203 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:30:16.673 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:30:17.142 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:30:17.611 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:30:18.082 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:30:18.551 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:30:19.020 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:30:19.489 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:30:19.960 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:30:20.429 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:30:20.906 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:30:21.384 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:30:21.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:21.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:21.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:21.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:21.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:21.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:21.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:21.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:21.500 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:21.500 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:21.500 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:21.501 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:30:26.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:26.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:26.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:26.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:26.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:26.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:26.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:26.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:26.509 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:26.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:26.509 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:26.510 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:26.510 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:30:26.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:26.512 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:26.512 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:30:26.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:26.513 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:30:26.513 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:30:26.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:26.513 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:26.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:26.514 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:30:26.514 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:26.514 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:30:26.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:30:26.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:30:26.517 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:30:26.517 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:30:26.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:26.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:26.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:26.519 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:30:31.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:31.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:31.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:31.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:31.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:31.526 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:31.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:31.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:31.533 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:31.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:31.533 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:30:31.536 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:30:31.536 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:30:31.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:31.537 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:31.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:31.538 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:30:31.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:31.538 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:30:31.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:31.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:30:31.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:30:31.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:31.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:31.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:31.540 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:30:31.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:31.541 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:30:31.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:31.542 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:31.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:30:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:31.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:30:31.546 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:30:31.546 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:30:31.546 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:31.551 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:30:32.034 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:30:32.065 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:30:32.065 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:30:32.065 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:30:32.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:30:32.504 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:30:32.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:32.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:32.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:32.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:32.972 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:30:33.445 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:30:33.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:33.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:33.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:33.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:33.920 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:30:34.389 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:30:34.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:34.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:34.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:34.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:34.857 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:30:35.335 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:30:35.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:35.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:35.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:35.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:35.816 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:30:36.297 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:30:36.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:36.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:36.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:36.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:36.766 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:30:37.235 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:30:37.711 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:30:38.191 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:30:38.662 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:30:39.142 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:30:39.621 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:30:40.096 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:30:40.564 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:30:41.038 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:30:41.519 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:30:42.000 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:30:42.481 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:30:42.962 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:30:43.442 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:30:43.917 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:30:44.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:44.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:44.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:44.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:44.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:44.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:44.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:44.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:44.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:44.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:44.077 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:30:49.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:30:49.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:30:49.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:49.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:49.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:49.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:49.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:30:49.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:49.097 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:49.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:30:49.098 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:30:49.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:30:49.103 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:30:49.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:49.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:49.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:30:49.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:30:49.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:30:49.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:30:49.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:49.106 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:30:49.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:30:49.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:49.107 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:49.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:30:49.107 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:30:49.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:30:49.107 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:30:49.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:49.109 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:30:49.109 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:30:49.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:49.112 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:30:49.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:30:49.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:30:49.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:30:49.112 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:30:49.113 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:30:49.113 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:30:49.113 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:30:49.118 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:30:49.598 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:30:49.641 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:30:49.642 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:30:49.643 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:30:49.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:30:49.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:30:49.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:30:49.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:30:49.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:30:49.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:30:49.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:30:49.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:30:49.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:30:50.075 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:30:50.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:50.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:50.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:50.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:50.553 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:30:51.031 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:30:51.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:51.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:51.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:51.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:51.507 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:30:51.980 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:30:52.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:52.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:52.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:52.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:52.458 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:30:52.936 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:30:53.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:53.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:53.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:53.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:53.413 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:30:53.890 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:30:54.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:30:54.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:30:54.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:30:54.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:30:54.368 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:30:54.845 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:30:55.319 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:30:55.796 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:30:56.274 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:30:56.752 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:30:57.228 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:30:57.705 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:30:58.183 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:30:58.655 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:30:59.132 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:30:59.609 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:31:00.087 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:31:00.565 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:31:00.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:00.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:00.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:00.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:00.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:00.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:00.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:00.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:00.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:00.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:00.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:00.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:00.702 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2478 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:00.704 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2479 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:05.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:05.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:05.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:05.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:05.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:05.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:05.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:05.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:05.712 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:05.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:05.712 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:31:05.714 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:31:05.714 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:31:05.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:05.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:05.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:05.715 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:31:05.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:05.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:31:05.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:05.716 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:31:05.716 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:31:05.716 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:05.716 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:05.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:05.717 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:31:05.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:05.717 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:31:05.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:05.718 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:31:05.718 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:31:05.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:05.718 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:05.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:05.719 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:31:05.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:05.719 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:31:05.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:31:05.722 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:31:05.722 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:31:05.722 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:05.726 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:31:06.197 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:31:06.262 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:31:06.264 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:31:06.265 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:31:06.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:06.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:06.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:06.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:06.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:06.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:06.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:06.269 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:06.269 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:06.669 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:31:06.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:06.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:06.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:06.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:07.147 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:31:07.625 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:31:07.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:07.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:07.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:07.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:08.102 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:31:08.577 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:31:08.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:08.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:08.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:08.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:09.046 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:31:09.519 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:31:09.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:09.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:09.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:09.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:09.997 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:31:10.474 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:31:10.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:10.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:10.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:10.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:10.949 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:31:11.418 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:31:11.893 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:31:12.371 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:31:12.849 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:31:13.324 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:31:13.797 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:31:14.275 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:31:14.747 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:31:15.217 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:31:15.695 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:31:16.173 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:31:16.650 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:31:17.127 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:31:17.600 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:31:18.074 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:31:18.552 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:31:19.030 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:31:19.504 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:31:19.976 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:31:20.448 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:31:20.922 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:31:21.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:21.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:21.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:21.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:21.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:21.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:21.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:21.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:21.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:21.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:21.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:21.300 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:31:21.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:21.300 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:21.301 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:26.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:26.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:26.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:26.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:26.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:26.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:26.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:26.315 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:26.315 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:26.315 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:26.316 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:31:26.321 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:31:26.321 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:31:26.321 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:26.321 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:26.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:26.322 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:31:26.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:26.322 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:31:26.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:26.325 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:31:26.326 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:31:26.326 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:26.326 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:26.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:26.326 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:31:26.326 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:26.326 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:31:26.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:26.330 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:26.330 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:31:26.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:26.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:31:26.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.335 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:31:26.335 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:31:26.335 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:31:26.336 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:26.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:26.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:26.340 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:31:26.817 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:31:26.870 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:31:26.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:26.873 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:31:26.876 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:31:26.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:26.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:26.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:26.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:26.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:26.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:26.886 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:26.886 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:26.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:26.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:26.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:26.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:26.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:26.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:26.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:26.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:26.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:26.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:26.923 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:31:31.921 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:31.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:31.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:31.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:31.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:31.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:31.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:31.941 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:31.941 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:31.941 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:31.941 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:31:31.944 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:31:31.944 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:31:31.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:31.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:31.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:31.944 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:31:31.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:31.945 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:31:31.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:31.947 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:31:31.947 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:31:31.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:31.947 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:31.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:31.947 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:31:31.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:31.948 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:31:31.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:31.949 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:31:31.949 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:31:31.949 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:31.949 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:31.950 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:31.950 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:31:31.950 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:31.950 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:31:31.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.952 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:31:31.953 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:31:31.953 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:31:31.953 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:31.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:31.957 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:31:32.430 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:31:32.478 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:31:32.480 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:31:32.481 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:31:32.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:32.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:32.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:32.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:32.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:32.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:32.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:32.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:32.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:32.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:32.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:32.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:32.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:32.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:32.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:32.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:32.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:32.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:32.662 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:31:32.662 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:31:32.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:32.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.831 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:31:32.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:32.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:32.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:32.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:32.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:32.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:32.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:32.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:32.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:32.899 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:31:32.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:32.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:32.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:32.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:32.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:32.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:32.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:33.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:33.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:33.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:33.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:33.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:33.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:33.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:33.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:33.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:33.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:33.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:33.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:33.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:33.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:33.316 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:33.316 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:33.367 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:31:33.367 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:31:33.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:33.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:33.369 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:31:33.839 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:31:33.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:33.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:33.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:33.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:34.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:34.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:34.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:34.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:34.161 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:31:34.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:34.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:34.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:34.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:34.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:34.174 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:34.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:34.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:34.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:34.175 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:31:34.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:34.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.175 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=482 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.176 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.177 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:34.177 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=483 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:31:39.174 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:31:39.174 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:31:39.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:39.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:39.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:39.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:39.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:31:39.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:39.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:39.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:31:39.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:31:39.184 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:31:39.184 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:31:39.184 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:39.184 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:31:39.185 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:31:39.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:39.185 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:39.186 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:31:39.186 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:31:39.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:31:39.186 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:31:39.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:39.188 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:31:39.188 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:31:39.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:39.191 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:31:39.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:31:39.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:31:39.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:31:39.191 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:31:39.192 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:31:39.192 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:31:39.192 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:31:39.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:31:39.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:31:39.197 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:31:39.671 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:31:39.730 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:31:39.732 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:31:39.733 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:31:39.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:39.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:39.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:39.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:39.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:39.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:39.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:39.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:39.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:39.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:39.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:39.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:39.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:39.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:39.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:39.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:39.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:40.141 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:31:40.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:40.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:40.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:40.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:40.614 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:31:41.092 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:31:41.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:41.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:41.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:41.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:41.570 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:31:42.047 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:31:42.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:42.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:42.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:42.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:42.521 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:31:42.991 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:31:43.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:43.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:43.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:43.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:43.463 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:31:43.941 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:31:44.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:31:44.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:31:44.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:31:44.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:31:44.414 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:31:44.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:44.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:44.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:44.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:44.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:44.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:44.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:44.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:44.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:44.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:44.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:44.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:44.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:44.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:44.847 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:44.847 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:44.882 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:31:44.882 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:31:44.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:44.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:44.887 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:31:45.356 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:31:45.825 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:31:46.296 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:31:46.766 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:31:47.237 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:31:47.708 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:31:48.179 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:31:48.657 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:31:49.135 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:31:49.605 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:31:49.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:49.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:49.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:49.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:49.892 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:31:49.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:49.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:49.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:49.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:49.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:49.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:49.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:49.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:49.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:49.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:49.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:49.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:49.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:49.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:49.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:49.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:50.074 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:31:50.544 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:31:51.015 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:31:51.486 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:31:51.964 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:31:52.441 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:31:52.918 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:31:53.396 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:31:53.865 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:31:54.334 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:31:54.811 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:31:54.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:54.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:54.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:54.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:54.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:54.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:54.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:54.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:31:54.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:31:54.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:31:54.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:31:54.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:54.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:31:54.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:31:54.959 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:31:54.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:31:54.995 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:31:54.995 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:31:54.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:54.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:31:55.285 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:31:55.763 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:31:56.241 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:31:56.719 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:31:57.196 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:31:57.673 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:31:58.142 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:31:58.615 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:31:59.094 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:31:59.572 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:32:00.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:00.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:00.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:00.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:00.005 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:32:00.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:00.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:00.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:00.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:00.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:00.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:00.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:00.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:00.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:32:00.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:32:00.018 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:32:05.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:32:05.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:32:05.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:05.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:05.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:05.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:05.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:05.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:32:05.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:05.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:32:05.032 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:32:05.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:32:05.036 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:32:05.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:32:05.036 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:05.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:05.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:32:05.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:32:05.037 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:32:05.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:05.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:32:05.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:32:05.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:32:05.041 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:05.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:05.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:32:05.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:32:05.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:32:05.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:05.044 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:32:05.044 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:32:05.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:32:05.044 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:05.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:05.045 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:32:05.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:32:05.045 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:32:05.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:32:05.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:32:05.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:32:05.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:05.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:32:05.526 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:32:05.588 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:32:05.589 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:32:05.590 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:32:05.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:05.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:05.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:05.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:05.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:05.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:05.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:05.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:05.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:05.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:05.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:05.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:05.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:05.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:05.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:05.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:05.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:05.998 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:32:06.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:06.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:06.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:06.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:06.477 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:32:06.955 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:32:07.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:07.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:07.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:07.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:07.433 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:32:07.907 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:32:08.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:08.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:08.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:08.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:08.376 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:32:08.847 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:32:09.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:09.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:09.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:09.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:09.317 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:32:09.788 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:32:10.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:10.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:10.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:10.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:10.259 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:32:10.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:10.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:10.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:10.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:10.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:10.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:10.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:10.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:10.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:10.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:10.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:10.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:10.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:10.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:10.698 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:10.698 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:10.727 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:32:10.727 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:32:10.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:10.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:10.736 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:32:11.205 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:32:11.674 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:32:12.145 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:32:12.615 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:32:13.086 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:32:13.561 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:32:14.031 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:32:14.500 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:32:14.970 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:32:15.446 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:32:15.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:15.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:15.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:15.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:15.736 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:32:15.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:15.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:15.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:15.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:15.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:15.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:15.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:15.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:15.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:15.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:15.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:15.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:15.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:15.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:15.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:15.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:15.920 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:32:16.391 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:32:16.864 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:32:17.336 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:32:17.807 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:32:18.277 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:32:18.751 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:32:19.220 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:32:19.689 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:32:20.167 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:32:20.645 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:32:20.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:20.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:20.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:20.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:20.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:20.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:20.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:20.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:20.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:20.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:20.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:20.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:20.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:20.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:20.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:20.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:20.829 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:32:20.829 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:32:20.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:20.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:21.117 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:32:21.587 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:32:22.062 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:32:22.531 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:32:23.000 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:32:23.472 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:32:23.942 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:32:24.418 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:32:24.896 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:32:25.373 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:32:25.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:25.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:25.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:25.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:25.841 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:32:25.846 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:32:25.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:25.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:25.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:25.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:25.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:25.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:25.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:25.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:25.857 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:32:25.857 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:32:25.857 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:32:25.857 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:25.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:25.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:25.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:25.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:25.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:25.858 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4492 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:30.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:32:30.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:32:30.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:30.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:30.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:30.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:30.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:30.862 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:32:30.863 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:30.863 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:32:30.863 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:32:30.865 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:32:30.865 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:32:30.866 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:32:30.866 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:30.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:30.866 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:32:30.867 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:32:30.867 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:32:30.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:32:30.868 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:32:30.868 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:32:30.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:30.870 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:32:30.870 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:32:30.870 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:32:30.870 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:30.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:30.871 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:32:30.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:32:30.871 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:32:30.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:30.873 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:32:30.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:32:30.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:32:30.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:32:30.873 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:32:30.874 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:32:30.874 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:32:30.874 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:32:30.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:30.879 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:32:31.363 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:32:31.410 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:32:31.412 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:32:31.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:31.414 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:32:31.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:31.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:31.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:31.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:31.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:31.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:31.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:31.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:31.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:31.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:31.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:31.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:31.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:31.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:31.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:31.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:31.840 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:32:31.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:31.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:31.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:31.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:32.318 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:32:32.796 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:32:32.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:32.879 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:32.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:32.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:33.274 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:32:33.752 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:32:33.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:33.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:33.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:33.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:34.230 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:32:34.707 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:32:34.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:34.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:34.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:34.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:35.184 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:32:35.662 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:32:35.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:35.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:35.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:35.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:36.139 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:32:36.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:36.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:36.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:36.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:36.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:36.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:36.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:36.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:36.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:36.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:36.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:36.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:36.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:36.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:36.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:36.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:36.557 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:32:36.557 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:32:36.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:36.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:36.612 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:32:37.082 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:32:37.552 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:32:38.023 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:32:38.493 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:32:38.964 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:32:39.436 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:32:39.906 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:32:40.382 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:32:40.852 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:32:41.321 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:32:41.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:41.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:41.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:41.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:41.568 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:32:41.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:41.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:41.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:41.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:41.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:41.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:41.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:41.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:41.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:41.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:41.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:41.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:41.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:41.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:41.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:41.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:41.791 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:32:42.264 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:32:42.733 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:32:43.203 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:32:43.675 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:32:44.152 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:32:44.630 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:32:45.107 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:32:45.581 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:32:46.058 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:32:46.536 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:32:46.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:46.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:46.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:46.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:46.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:46.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:46.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:46.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:46.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:46.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:46.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:46.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:46.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:46.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:46.633 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:46.633 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:46.674 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:32:46.674 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:32:46.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:46.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:47.010 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:32:47.489 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:32:47.967 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:32:48.445 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:32:48.923 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:32:49.397 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:32:49.875 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:32:50.353 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:32:50.830 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:32:51.307 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:32:51.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:51.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:51.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:51.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:51.684 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:32:51.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:51.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:51.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:51.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:51.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:51.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:51.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:51.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:32:51.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:32:51.701 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:32:51.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:51.702 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:51.702 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:51.702 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:51.702 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:51.702 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:51.702 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:51.703 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:32:56.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:32:56.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:32:56.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:56.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:56.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:56.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:56.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:32:56.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:32:56.711 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:56.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:32:56.712 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:32:56.713 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:32:56.713 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:32:56.713 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:32:56.713 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:56.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:32:56.714 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:32:56.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:32:56.714 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:32:56.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:32:56.715 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:32:56.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:32:56.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:32:56.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:32:56.717 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:32:56.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:56.719 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:32:56.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:32:56.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:32:56.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:32:56.720 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:32:56.720 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:32:56.720 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:32:56.725 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:32:57.202 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:32:57.249 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:32:57.251 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:32:57.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:57.255 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:32:57.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:57.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:57.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:57.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:32:57.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:32:57.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:32:57.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:32:57.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:57.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:57.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:57.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:32:57.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:32:57.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:32:57.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:32:57.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:57.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:32:57.674 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:32:57.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:57.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:57.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:57.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:58.145 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:32:58.619 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:32:58.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:58.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:58.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:58.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:32:59.097 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:32:59.574 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:32:59.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:32:59.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:32:59.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:32:59.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:00.046 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:33:00.518 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:33:00.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:00.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:00.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:00.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:00.988 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:33:01.460 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:33:01.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:01.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:01.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:01.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:01.938 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:33:02.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:02.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:02.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:02.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:02.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:02.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:02.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:02.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:02.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:02.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:02.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:02.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:02.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:02.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:02.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:02.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:02.358 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:33:02.358 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:33:02.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:02.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:02.415 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:33:02.884 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:33:03.354 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:33:03.824 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:33:04.296 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:33:04.766 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:33:05.236 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:33:05.706 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:33:06.177 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:33:06.648 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:33:07.125 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:33:07.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:07.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:07.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:07.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:07.368 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:33:07.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:07.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:07.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:07.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:07.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:07.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:07.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:07.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:07.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:07.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:07.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:07.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:07.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:07.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:07.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:07.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:07.598 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:33:08.072 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:33:08.545 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:33:09.017 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:33:09.490 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:33:09.968 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:33:10.441 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:33:10.916 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:33:11.393 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:33:11.869 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:33:12.346 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:33:12.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:12.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:12.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:12.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:12.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:12.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:12.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:12.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:12.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:12.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:12.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:12.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:12.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:12.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:12.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:12.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:12.484 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:33:12.485 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:33:12.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:12.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:12.822 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:33:13.300 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:33:13.771 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:33:14.248 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:33:14.720 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:33:15.192 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:33:15.661 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:33:16.134 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:33:16.612 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:33:17.090 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:33:17.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:17.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:17.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:17.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:17.494 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:33:17.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:17.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:17.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:17.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:17.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:33:17.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:33:17.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:33:17.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:33:17.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:33:17.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:33:17.510 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:33:17.510 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4478 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:17.510 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4478 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:17.510 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4478 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:17.510 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4478 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:17.510 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4478 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:17.510 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4478 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:22.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:33:22.507 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:33:22.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:33:22.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:33:22.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:33:22.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:33:22.526 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:33:22.527 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:33:22.527 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:22.527 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:33:22.527 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:33:22.529 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:33:22.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:33:22.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:33:22.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:22.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:33:22.530 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:33:22.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:33:22.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:33:22.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:22.532 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:33:22.532 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:33:22.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:33:22.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:22.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:33:22.532 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:33:22.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:33:22.532 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:33:22.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:33:22.534 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:33:22.534 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:33:22.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.537 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:33:22.538 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:33:22.538 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:33:22.538 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:22.542 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:33:23.026 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:33:23.069 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:33:23.071 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:33:23.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:23.073 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:33:23.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:23.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:23.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:23.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:23.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:23.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:23.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:23.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:23.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:23.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:23.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:23.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:23.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:23.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:23.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:23.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:23.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:23.443 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:33:23.443 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:33:23.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.500 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:33:23.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:23.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:23.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:23.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:23.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:23.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.823 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:33:23.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:23.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:23.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:23.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:23.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:23.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:23.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:23.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:23.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:23.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:23.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:23.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:23.968 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:33:24.445 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:33:24.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:24.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:24.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:24.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:24.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:24.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:24.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:24.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:24.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:24.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:24.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:24.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:24.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:24.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:24.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:24.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:24.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:24.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:24.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:24.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:24.681 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:33:24.681 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:33:24.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:24.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:24.921 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:33:25.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:25.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:25.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:25.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:25.238 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:33:25.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:25.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:25.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:25.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:25.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:33:25.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:33:25.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:33:25.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:33:25.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:33:25.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:33:25.255 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:33:25.255 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.255 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:25.256 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=585 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:33:30.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:33:30.254 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:33:30.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:33:30.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:33:30.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:33:30.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:33:30.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:33:30.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:33:30.276 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:30.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:33:30.276 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:33:30.279 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:33:30.279 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:33:30.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:33:30.279 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:30.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:33:30.279 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:33:30.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:33:30.279 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:33:30.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:30.281 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:33:30.281 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:33:30.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:33:30.282 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:30.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:33:30.282 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:33:30.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:33:30.282 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:33:30.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:30.283 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:33:30.283 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:33:30.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:33:30.283 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:33:30.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:33:30.283 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:33:30.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:33:30.283 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:33:30.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:33:30.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:33:30.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:33:30.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:33:30.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:33:30.291 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:33:30.762 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:33:30.816 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:33:30.817 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:33:30.820 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:33:30.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:30.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:30.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:30.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:30.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:30.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:30.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:30.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:30.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:30.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:30.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:30.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:30.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:30.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:30.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:30.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:30.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:31.232 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:33:31.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:31.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:31.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:31.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:31.705 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:33:32.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:33:32.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:32.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:32.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:32.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:32.658 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:33:33.135 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:33:33.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:33.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:33.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:33.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:33.613 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:33:34.091 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:33:34.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:34.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:34.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:34.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:34.563 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:33:35.040 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:33:35.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:33:35.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:33:35.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:33:35.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:33:35.512 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:33:35.990 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:33:36.465 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:33:36.938 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:33:37.416 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:33:37.894 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:33:38.367 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:33:38.837 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:33:39.310 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:33:39.780 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:33:40.250 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:33:40.720 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:33:41.191 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:33:41.665 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:33:42.143 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:33:42.620 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:33:43.098 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:33:43.570 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:33:44.041 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:33:44.512 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:33:44.983 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:33:45.453 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:33:45.924 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:33:46.395 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:33:46.867 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:33:47.337 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:33:47.810 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:33:48.284 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:33:48.761 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:33:49.236 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:33:49.714 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:33:50.189 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:33:50.663 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:33:50.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:50.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:50.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:50.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:50.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:50.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:50.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:50.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:33:50.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:33:50.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:33:50.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:33:50.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:50.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:33:50.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:33:50.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:33:50.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:33:50.941 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:33:50.941 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:33:50.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:50.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:33:51.136 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:33:51.612 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:33:52.084 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:33:52.555 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:33:53.025 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:33:53.496 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:33:53.966 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:33:54.438 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:33:54.908 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:33:55.379 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:33:55.856 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:33:56.333 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:33:56.805 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:33:57.281 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:33:57.750 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:33:58.220 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:33:58.690 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:33:59.161 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:33:59.634 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:34:00.112 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:34:00.584 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:34:01.055 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:34:01.525 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:34:02.001 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:34:02.474 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:34:02.946 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:34:03.415 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:34:03.885 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:34:04.358 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:34:04.828 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:34:05.298 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:34:05.768 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:34:06.239 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:34:06.710 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:34:07.180 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 03:34:07.651 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 03:34:08.123 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 03:34:08.592 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 03:34:09.064 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 03:34:09.534 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 03:34:10.006 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 03:34:10.477 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 03:34:10.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:10.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:34:10.947 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 03:34:10.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:10.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:10.953 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:34:10.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:10.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:10.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:34:10.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:10.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:10.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:34:10.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:34:10.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:10.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:34:10.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:34:10.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:34:10.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:34:10.989 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:34:10.989 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:34:10.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:10.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:11.417 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 03:34:11.894 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 03:34:12.372 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 03:34:12.850 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 03:34:13.327 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 03:34:13.802 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 03:34:14.279 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 03:34:14.756 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 03:34:15.234 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 03:34:15.712 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 03:34:16.190 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 03:34:16.668 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 03:34:17.147 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 03:34:17.624 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 03:34:18.096 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 03:34:18.567 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 03:34:19.037 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 03:34:19.508 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 03:34:19.980 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 03:34:20.451 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 03:34:20.928 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 03:34:21.405 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 03:34:21.882 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 03:34:22.355 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 03:34:22.827 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 03:34:23.305 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 03:34:23.777 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 03:34:24.248 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 03:34:24.718 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 03:34:25.190 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 03:34:25.662 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 03:34:26.140 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 03:34:26.613 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 03:34:27.082 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 03:34:27.558 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 03:34:28.035 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 03:34:28.511 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 03:34:28.989 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 03:34:29.467 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 03:34:29.945 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 03:34:30.423 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 03:34:30.898 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 03:34:30.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:30.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:34:31.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:31.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:31.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:31.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:31.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:34:31.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:31.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:31.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:34:31.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:34:31.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:31.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:34:31.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:34:31.025 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:34:31.025 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:34:31.028 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:34:31.028 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:34:31.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:31.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:31.370 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 03:34:31.841 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 03:34:32.317 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 03:34:32.796 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 03:34:33.273 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 03:34:33.752 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 03:34:34.229 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 03:34:34.707 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 03:34:35.179 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 03:34:35.651 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 03:34:36.127 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 03:34:36.603 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 03:34:37.075 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 03:34:37.551 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 03:34:38.029 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 03:34:38.506 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 03:34:38.983 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 03:34:39.462 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 03:34:39.939 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 03:34:40.410 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 03:34:40.884 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 03:34:41.353 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 03:34:41.823 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 03:34:42.294 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 03:34:42.764 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 03:34:43.239 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 03:34:43.716 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 03:34:44.193 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 03:34:44.672 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 03:34:45.150 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 03:34:45.619 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 03:34:46.088 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 03:34:46.561 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 03:34:47.033 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 03:34:47.511 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 03:34:47.985 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 03:34:48.460 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 03:34:48.938 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 03:34:49.416 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 03:34:49.894 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 03:34:50.372 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 03:34:50.850 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 03:34:51.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:34:51.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:34:51.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:34:51.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:34:51.041 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:34:51.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:34:51.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:34:51.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:34:51.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:34:51.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:34:51.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:34:51.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:34:51.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:34:51.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:34:51.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:34:51.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:34:51.060 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.060 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17386 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.061 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.062 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.062 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:51.062 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=17387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:34:56.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:34:56.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:34:56.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:34:56.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:34:56.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:34:56.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:34:56.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:34:56.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:34:56.061 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:34:56.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:34:56.061 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:34:56.062 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:34:56.062 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:34:56.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:34:56.063 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:34:56.063 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:34:56.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:34:56.064 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:34:56.064 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:34:56.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:34:56.064 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:34:56.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:34:56.065 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:34:56.065 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:34:56.065 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:34:56.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:34:56.067 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:34:56.067 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:34:56.067 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:34:56.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:34:56.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:34:56.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:34:56.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:34:56.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:34:56.068 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:34:56.068 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:34:56.068 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:35:01.071 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:01.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:01.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:01.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:01.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:01.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:01.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:01.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:01.082 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:01.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:01.083 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:35:01.085 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:35:01.086 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:35:01.086 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:01.086 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:01.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:01.087 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:35:01.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:01.087 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:35:01.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:01.088 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:35:01.088 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:35:01.089 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:01.089 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:01.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:01.089 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:35:01.089 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:01.089 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:35:01.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:01.091 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:01.091 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:35:01.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:01.093 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:35:01.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:35:01.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:35:01.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:35:01.093 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:35:01.094 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:35:01.094 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:35:01.094 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:01.099 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:35:01.582 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:35:01.617 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:35:01.618 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:35:01.619 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:35:01.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:01.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:01.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:01.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:01.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:01.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:01.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:01.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:01.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:01.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:01.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:01.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:01.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:01.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:01.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:01.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:01.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:01.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:01.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:01.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:01.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:01.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:01.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:01.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:01.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:01.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:01.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:01.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:01.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:01.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:01.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:01.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:01.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:01.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.055 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:35:02.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:02.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:02.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:02.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:02.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:02.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:02.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:02.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:02.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:02.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:02.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:02.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:02.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:02.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:02.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:02.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:02.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:02.377 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:02.377 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:35:02.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.525 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:35:02.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.660 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:02.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:02.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:02.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:02.681 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:02.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:02.708 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:02.708 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:35:02.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:02.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:02.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:02.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:02.985 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:02.996 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:35:03.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:03.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:03.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:03.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:03.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:03.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:03.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:03.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:03.040 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:03.040 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:35:03.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:03.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:03.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:03.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:03.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:03.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:03.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:03.344 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:03.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:03.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:03.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:03.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:03.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:03.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:03.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:03.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:03.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:03.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:03.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:03.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:03.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:03.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:03.466 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:35:03.938 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:35:04.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:04.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:04.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:04.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:04.416 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:35:04.888 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:35:05.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:05.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:05.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:05.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:05.361 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:35:05.839 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:35:05.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:05.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:06.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:06.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:06.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:06.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:06.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:06.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:06.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:06.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:06.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:06.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:06.017 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:06.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:06.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:06.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:06.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:06.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:06.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:06.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:06.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:06.314 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:35:06.787 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:35:07.259 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:35:07.729 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:35:08.199 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:35:08.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:08.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:08.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:08.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:08.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:08.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:08.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:08.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:08.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:08.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:08.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:08.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:08.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:08.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:08.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:08.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:08.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:08.671 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:35:09.144 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:35:09.618 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:35:10.092 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:35:10.561 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:35:11.037 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:35:11.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:11.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:11.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:11.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:11.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:11.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:11.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:11.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:11.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:11.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:11.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:11.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:11.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:11.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:11.225 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:11.225 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:11.272 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:11.272 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:35:11.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:11.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:11.509 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:35:11.984 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:35:12.462 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:35:12.936 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:35:13.412 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:35:13.888 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:35:13.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:13.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:13.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:13.975 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:13.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:13.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:13.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:13.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:13.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:13.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:13.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:13.998 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:13.998 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:14.026 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:14.026 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:35:14.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:14.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:14.360 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:35:14.834 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:35:15.312 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:35:15.790 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:35:16.266 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:35:16.744 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:35:16.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:16.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:16.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:16.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:16.832 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:16.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:16.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:16.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:16.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:16.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:16.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:16.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:16.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:16.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:16.884 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:16.884 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:35:16.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:16.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:17.219 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:35:17.688 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:35:18.158 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:35:18.628 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:35:19.099 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:35:19.570 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:35:19.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:19.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:19.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:19.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:19.649 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:19.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:19.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:19.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:19.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:19.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:19.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:19.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:19.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:19.653 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:19.653 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:19.654 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:19.654 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3998 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:24.655 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:24.656 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:24.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:24.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:24.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:24.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:24.679 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:24.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:24.680 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:35:24.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:35:24.682 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:35:24.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:24.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:24.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:24.682 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:35:24.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:24.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:35:24.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:24.684 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:24.684 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:35:24.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:24.686 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:24.686 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:35:24.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:35:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:35:24.689 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:35:24.689 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:35:24.689 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:24.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:24.694 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:35:25.170 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:35:25.223 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:35:25.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:25.227 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:35:25.229 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:35:25.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:25.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:25.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:25.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:25.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:25.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:25.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:25.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:25.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:25.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:25.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:25.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:25.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:25.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:25.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:25.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:25.640 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:35:25.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:25.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:25.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:25.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:26.113 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:35:26.588 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:35:26.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:26.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:26.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:27.060 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:35:27.537 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:35:27.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:27.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:27.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:27.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:28.015 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:35:28.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:28.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:28.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:28.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:28.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:28.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:28.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:28.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:28.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:28.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:28.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:28.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:28.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:28.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:28.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:28.486 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:28.486 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:35:28.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:28.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:28.493 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:35:28.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:28.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:28.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:28.962 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:35:29.432 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:35:29.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:29.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:29.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:29.902 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:35:30.372 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:35:30.843 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:35:31.314 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:35:31.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:31.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:31.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:31.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:31.695 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:31.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:31.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:31.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:31.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:31.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:31.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:31.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:31.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:31.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:31.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:31.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:31.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:31.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:31.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:31.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:31.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:31.785 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:35:32.260 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:35:32.732 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:35:33.203 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:35:33.675 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:35:34.144 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:35:34.615 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:35:35.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:35.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:35.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:35.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:35.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:35.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:35.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:35.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:35.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:35.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:35.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:35.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:35.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:35.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:35.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:35.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:35.085 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:35.085 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:35:35.086 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:35:35.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:35.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:35.556 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:35:36.028 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:35:36.502 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:35:36.975 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:35:37.447 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:35:37.916 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:35:38.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:38.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:38.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:38.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:38.241 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:38.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:38.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:38.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:38.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:38.256 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:38.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:38.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:38.256 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:38.256 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:38.256 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:38.256 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:35:43.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:43.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:43.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:43.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:43.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:43.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:43.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:43.272 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:43.272 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:43.272 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:43.272 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:43.274 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:43.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:35:43.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:43.275 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:43.275 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:35:43.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:43.276 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:35:43.276 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:35:43.277 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:43.277 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:43.277 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:35:43.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:43.277 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:43.277 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:35:43.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:35:43.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:35:43.279 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:35:43.279 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:35:43.279 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:43.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:43.283 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:35:43.754 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:35:43.812 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:35:43.814 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:35:43.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:43.816 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:35:43.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:43.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:43.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:43.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:43.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:43.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:43.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:43.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:43.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:43.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:43.842 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:43.842 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:43.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:43.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:43.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:43.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:44.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:44.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:44.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:44.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:44.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:44.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:44.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:44.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:44.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:44.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:44.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:44.200 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:44.200 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:44.224 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:35:44.225 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:44.225 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:35:44.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:44.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:44.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:44.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:44.694 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:35:44.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:44.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:44.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:44.708 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:44.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:44.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:44.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:44.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:44.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:44.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:44.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:44.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:44.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:44.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:44.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:44.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:44.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:44.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:44.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:45.163 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:35:45.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:45.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:45.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:45.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:45.634 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:35:46.107 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:35:46.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:46.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:46.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:46.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:46.583 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:35:47.060 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:35:47.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:47.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:47.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:47.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:47.538 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:35:47.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:47.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:47.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:47.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:47.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:47.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:47.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:47.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:47.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:47.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:47.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:47.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:47.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:47.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:47.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:47.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:47.773 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:47.773 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:35:47.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:47.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:48.010 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:35:48.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:48.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:48.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:48.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:48.480 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:35:48.958 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:35:49.430 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:35:49.900 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:35:50.376 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:35:50.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:50.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:50.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:50.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:50.699 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:50.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:50.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:50.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:50.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:50.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:50.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:50.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:50.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:50.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:50.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:50.713 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.714 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:50.715 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:35:55.714 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:35:55.714 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:35:55.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:55.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:55.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:55.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:55.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:35:55.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:55.729 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:55.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:35:55.729 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:35:55.735 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:35:55.735 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:35:55.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:55.736 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:55.736 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:35:55.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:35:55.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:35:55.736 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:35:55.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:55.740 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:35:55.740 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:35:55.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:55.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:55.741 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:35:55.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:35:55.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:35:55.741 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:35:55.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:55.746 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:35:55.746 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:35:55.746 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:55.746 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:35:55.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:35:55.746 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:35:55.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:35:55.747 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:35:55.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:55.752 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.753 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:35:55.754 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:35:55.754 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:35:55.754 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:35:55.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:35:55.759 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:35:56.231 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:35:56.293 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:35:56.294 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:35:56.296 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:35:56.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:56.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:56.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:56.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:56.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:56.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:56.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:56.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:56.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:56.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:56.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:56.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:56.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:56.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:56.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:56.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:56.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:56.704 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:35:56.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:56.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:56.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:56.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:57.174 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:35:57.650 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:35:57.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:57.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:57.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:57.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:57.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:57.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:57.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:57.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:57.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:57.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:57.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:57.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:57.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:57.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:57.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:57.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:57.744 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:35:57.744 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:35:57.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:57.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:57.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:57.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:57.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:57.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:58.122 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:35:58.593 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:35:58.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:58.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:58.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:58.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:59.069 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:35:59.547 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:35:59.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:35:59.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:35:59.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:35:59.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:35:59.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:59.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:59.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:59.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:59.873 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:35:59.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:59.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:59.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:59.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:35:59.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:35:59.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:35:59.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:35:59.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:59.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:59.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:59.901 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:35:59.901 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:35:59.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:35:59.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:35:59.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:35:59.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:00.019 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:36:00.489 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:36:00.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:00.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:00.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:00.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:00.965 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:36:01.443 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:36:01.920 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:36:02.398 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:36:02.876 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:36:03.354 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:36:03.832 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:36:04.309 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:36:04.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:04.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:04.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:04.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:04.786 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:36:04.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:04.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:04.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:04.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:04.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:04.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:04.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:04.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:04.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:04.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:04.800 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:36:04.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:36:04.832 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:36:04.832 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:36:04.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:04.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:05.255 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:36:05.724 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:36:06.197 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:36:06.669 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:36:07.138 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:36:07.610 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:36:08.082 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:36:08.553 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:36:09.024 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:36:09.495 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:36:09.972 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:36:10.450 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:36:10.929 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:36:11.407 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:36:11.881 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:36:12.350 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:36:12.824 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:36:13.302 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:36:13.780 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:36:14.256 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:36:14.730 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:36:15.206 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:36:15.680 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:36:16.156 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:36:16.634 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:36:17.111 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:36:17.590 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:36:18.067 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:36:18.544 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:36:19.021 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:36:19.492 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:36:19.966 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:36:20.436 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:36:20.905 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:36:21.375 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:36:21.846 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:36:22.319 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:36:22.788 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:36:23.259 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:36:23.729 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:36:24.200 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:36:24.673 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:36:24.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:24.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:24.796 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:36:24.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:24.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:24.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:24.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:24.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:36:24.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:36:24.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:36:24.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:36:24.803 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:36:24.803 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:36:24.803 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:36:29.801 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:36:29.802 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:36:29.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:36:29.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:36:29.806 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:36:29.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:36:29.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:36:29.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:36:29.820 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:29.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:36:29.820 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:36:29.822 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:36:29.822 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:36:29.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:36:29.824 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:36:29.824 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:36:29.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:29.825 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:36:29.825 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:36:29.825 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:36:29.825 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:29.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:36:29.826 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:36:29.826 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:36:29.826 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:36:29.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:36:29.828 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:36:29.828 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:36:29.828 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:29.833 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:36:30.302 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:36:30.359 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:36:30.361 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:36:30.363 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:36:30.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:30.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:30.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:30.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:30.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:30.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:30.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:30.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:30.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:30.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:30.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:30.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:36:30.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:36:30.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:30.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:30.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:30.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:30.775 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:36:30.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:30.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:30.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:30.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:31.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:31.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:31.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:31.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:31.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:31.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:31.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:31.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:31.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:31.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:31.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:31.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:31.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:31.089 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:36:31.089 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:36:31.098 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:36:31.098 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:36:31.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:31.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:31.246 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:36:31.716 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:36:31.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:31.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:31.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:31.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:32.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:32.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:32.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:32.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:32.023 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:36:32.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:32.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:32.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:32.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:32.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:32.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:32.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:32.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:32.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:32.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:36:32.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:36:32.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:32.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:32.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:32.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:32.187 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:36:32.665 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:36:32.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:32.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:32.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:32.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:33.142 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:36:33.619 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:36:33.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:33.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:33.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:33.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:34.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:34.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:34.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:34.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:34.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:34.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:34.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:34.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:34.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:34.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:34.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:34.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:34.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:34.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:34.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:36:34.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:36:34.089 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:36:34.090 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:36:34.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:34.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:34.096 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:36:34.573 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:36:34.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:34.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:34.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:34.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:35.048 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:36:35.519 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:36:35.992 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:36:36.470 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:36:36.943 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:36:37.420 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:36:37.898 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:36:38.377 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:36:38.854 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:36:39.333 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:36:39.811 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:36:40.290 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:36:40.767 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:36:41.246 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:36:41.723 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:36:42.199 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:36:42.668 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:36:43.141 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:36:43.613 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:36:44.090 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:36:44.568 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:36:45.042 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:36:45.511 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:36:45.985 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:36:46.463 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:36:46.932 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:36:47.406 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:36:47.879 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:36:48.349 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:36:48.823 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:36:49.293 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:36:49.764 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:36:50.239 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:36:50.717 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:36:51.189 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:36:51.659 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:36:52.132 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:36:52.601 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:36:53.073 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:36:53.547 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:36:54.018 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:36:54.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:54.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:54.037 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:36:54.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:54.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:54.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:54.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:54.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:36:54.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:36:54.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:36:54.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:36:54.044 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:36:54.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:36:54.044 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:54.045 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=5209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:36:59.042 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:36:59.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:36:59.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:36:59.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:36:59.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:36:59.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:36:59.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:36:59.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:36:59.066 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:59.067 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:36:59.067 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:36:59.070 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:36:59.070 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:36:59.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:36:59.070 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:59.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:36:59.070 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:36:59.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:36:59.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:36:59.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:36:59.074 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:36:59.074 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:36:59.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:36:59.074 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:59.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:36:59.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:36:59.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:36:59.075 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:36:59.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:36:59.078 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:36:59.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:36:59.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:36:59.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:36:59.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:36:59.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:36:59.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:36:59.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:36:59.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:36:59.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:36:59.086 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:36:59.086 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:36:59.086 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:36:59.091 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:36:59.567 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:36:59.625 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:36:59.627 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:36:59.629 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:36:59.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:59.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:59.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:59.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:59.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:36:59.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:36:59.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:36:59.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:36:59.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:59.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:59.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:59.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:36:59.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:36:59.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:36:59.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:36:59.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:36:59.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:00.040 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:37:00.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:00.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:00.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:00.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:00.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:37:00.993 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:37:01.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:01.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:01.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:01.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:01.466 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:37:01.936 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:37:02.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:02.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:02.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:02.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:02.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:02.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:02.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:02.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:02.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:02.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:02.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:02.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:02.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:02.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:02.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:02.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:02.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:02.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:02.183 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:02.183 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:02.215 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:37:02.215 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:37:02.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:02.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:02.406 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:37:02.877 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:37:03.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:03.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:03.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:03.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:03.348 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:37:03.821 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:37:04.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:04.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:04.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:04.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:04.291 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:37:04.760 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:37:04.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:04.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:04.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:04.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:04.901 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:37:04.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:04.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:04.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:04.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:04.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:04.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:04.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:04.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:04.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:04.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:04.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:04.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:04.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:04.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:04.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:04.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:05.231 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:37:05.706 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:37:06.184 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:37:06.659 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:37:07.132 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:37:07.605 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:37:08.075 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:37:08.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:08.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:08.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:08.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:08.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:08.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:08.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:08.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:08.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:08.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:08.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:08.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:08.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:08.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:08.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:08.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:08.308 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:37:08.308 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:37:08.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:08.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:08.546 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:37:09.016 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:37:09.488 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:37:09.958 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:37:10.436 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:37:10.913 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:37:11.384 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:37:11.859 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:37:12.337 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:37:12.815 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:37:13.294 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:37:13.773 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:37:14.247 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:37:14.720 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:37:15.198 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:37:15.676 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:37:16.145 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:37:16.614 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:37:17.086 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:37:17.556 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:37:18.026 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:37:18.497 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:37:18.973 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:37:19.450 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:37:19.927 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:37:20.398 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:37:20.873 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:37:21.351 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:37:21.820 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:37:22.289 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:37:22.759 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:37:23.231 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:37:23.701 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:37:24.174 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:37:24.644 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:37:25.117 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:37:25.595 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:37:26.071 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:37:26.549 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:37:27.027 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:37:27.499 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:37:27.969 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:37:28.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:28.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:28.256 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:37:28.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:28.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:28.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:28.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:28.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:37:28.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:37:28.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:37:28.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:37:28.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:37:28.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:37:28.264 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:37:33.267 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:37:33.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:37:33.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:37:33.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:37:33.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:37:33.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:37:33.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:37:33.270 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:37:33.270 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:33.270 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:37:33.270 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:37:33.272 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:37:33.272 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:37:33.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:33.274 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:37:33.274 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:37:33.274 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:37:33.274 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:33.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:37:33.275 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:37:33.275 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:37:33.275 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:37:33.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:33.276 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:37:33.277 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:37:33.277 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:37:33.277 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:33.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:37:33.277 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:37:33.277 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:37:33.277 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:37:33.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:33.279 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:37:33.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:37:33.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:37:33.280 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:37:33.280 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:37:33.280 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:33.285 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:37:33.755 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:37:33.815 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:37:33.817 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:37:33.819 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:37:33.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:33.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:33.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:33.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:33.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:33.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:33.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:33.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:33.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:33.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:33.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:33.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:33.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:33.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:33.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:33.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:33.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:34.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:34.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:34.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:34.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:34.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:34.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:34.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:34.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:34.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:34.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:34.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:34.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:34.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:34.175 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:37:34.175 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:37:34.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.226 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:37:34.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:34.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:34.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:34.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:34.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:34.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:34.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:34.510 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:37:34.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:34.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:34.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:34.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:34.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:34.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:34.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:34.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:34.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:34.538 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:34.538 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:34.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:34.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:34.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:34.695 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:37:35.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:35.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:35.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:35.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:35.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:35.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:35.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:35.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:35.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:35.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:35.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:35.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:35.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:35.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:35.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:35.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:35.162 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:37:35.162 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:37:35.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:35.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:35.164 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:37:35.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:35.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:35.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:35.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:35.641 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:37:35.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:35.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:35.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:35.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:35.729 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:37:35.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:35.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:35.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:35.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:35.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:37:35.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:37:35.742 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:37:35.742 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:37:35.742 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:37:35.743 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:37:35.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:37:35.743 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.743 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.743 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.743 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=533 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.744 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:35.745 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=534 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:37:40.742 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:37:40.742 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:37:40.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:37:40.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:37:40.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:37:40.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:37:40.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:37:40.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:37:40.760 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:40.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:37:40.760 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:37:40.764 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:37:40.764 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:37:40.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:37:40.764 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:40.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:37:40.764 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:37:40.765 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:37:40.765 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:37:40.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:37:40.767 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:37:40.767 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:37:40.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:40.769 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:37:40.769 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:37:40.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:37:40.769 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:37:40.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:37:40.770 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:37:40.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:37:40.770 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:37:40.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:37:40.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:37:40.773 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:37:40.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:37:40.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:37:40.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:37:40.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:37:40.778 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:37:41.255 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:37:41.305 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:37:41.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:41.308 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:37:41.310 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:37:41.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:41.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:41.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:41.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:37:41.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:37:41.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:37:41.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:37:41.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:41.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:41.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:41.367 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:37:41.367 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:37:41.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:37:41.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:37:41.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:41.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:37:41.728 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:37:41.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:41.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:41.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:41.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:42.206 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:37:42.684 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:37:42.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:42.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:42.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:42.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:43.156 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:37:43.627 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:37:43.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:43.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:43.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:43.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:44.097 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:37:44.568 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:37:44.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:44.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:44.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:44.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:45.039 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:37:45.514 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:37:45.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:37:45.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:37:45.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:37:45.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:37:45.991 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:37:46.469 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:37:46.946 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:37:47.424 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:37:47.901 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:37:48.379 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:37:48.856 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:37:49.329 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:37:49.807 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:37:50.285 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:37:50.760 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:37:51.237 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:37:51.715 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:37:52.189 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:37:52.658 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:37:53.135 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:37:53.608 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:37:54.085 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:37:54.557 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:37:55.035 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:37:55.510 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:37:55.988 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:37:56.465 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:37:56.942 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:37:57.420 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:37:57.898 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:37:58.375 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:37:58.852 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:37:59.324 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:37:59.802 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:38:00.276 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:38:00.746 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:38:01.216 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:38:01.687 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:38:02.162 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:38:02.639 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:38:03.114 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:38:03.587 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:38:04.065 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:38:04.542 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:38:05.012 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:38:05.490 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:38:05.962 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:38:06.439 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:38:06.917 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:38:07.395 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:38:07.870 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:38:08.340 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:38:08.817 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:38:09.289 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:38:09.764 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:38:10.238 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:38:10.707 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:38:11.177 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:38:11.651 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:38:12.124 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:38:12.601 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:38:13.079 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:38:13.551 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:38:14.022 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:38:14.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:14.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:38:14.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:38:14.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:38:14.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:38:14.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:38:14.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:38:14.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:38:14.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:38:14.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:38:14.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:38:14.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:14.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:38:14.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:38:14.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:38:14.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:38:14.440 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:38:14.440 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:38:14.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:14.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:14.492 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:38:14.963 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:38:15.435 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:38:15.906 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:38:16.376 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:38:16.852 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:38:17.331 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:38:17.803 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 03:38:18.281 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 03:38:18.758 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 03:38:19.237 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 03:38:19.711 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 03:38:20.185 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 03:38:20.657 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 03:38:21.131 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 03:38:21.603 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 03:38:22.078 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 03:38:22.547 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 03:38:23.017 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 03:38:23.487 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 03:38:23.958 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 03:38:24.436 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 03:38:24.912 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 03:38:25.390 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 03:38:25.864 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 03:38:26.333 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 03:38:26.803 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 03:38:27.274 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 03:38:27.749 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 03:38:28.226 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 03:38:28.701 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 03:38:29.170 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-02 03:38:29.640 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-02 03:38:30.115 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-02 03:38:30.594 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-02 03:38:31.072 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-02 03:38:31.548 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-02 03:38:32.018 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-02 03:38:32.496 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-02 03:38:32.975 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-02 03:38:33.446 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-02 03:38:33.917 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-02 03:38:34.388 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-02 03:38:34.859 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-02 03:38:35.338 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-02 03:38:35.816 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-02 03:38:36.295 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-02 03:38:36.773 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-02 03:38:37.245 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-02 03:38:37.716 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-02 03:38:38.193 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-02 03:38:38.665 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-02 03:38:39.142 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-02 03:38:39.620 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-02 03:38:40.098 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-02 03:38:40.577 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-02 03:38:41.055 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-02 03:38:41.535 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-02 03:38:42.012 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-02 03:38:42.479 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-02 03:38:42.948 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-02 03:38:43.417 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-02 03:38:43.888 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-02 03:38:44.363 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-02 03:38:44.834 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-02 03:38:45.305 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-02 03:38:45.776 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-02 03:38:46.247 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-02 03:38:46.718 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-02 03:38:47.188 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-02 03:38:47.662 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-02 03:38:48.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:48.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:38:48.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:38:48.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:38:48.025 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:38:48.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:38:48.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:38:48.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:38:48.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:38:48.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:38:48.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:38:48.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:38:48.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:48.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:38:48.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:38:48.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:38:48.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:38:48.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:38:48.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:38:48.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:48.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:38:48.132 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-02 03:38:48.602 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-02 03:38:49.072 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-02 03:38:49.542 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-02 03:38:50.013 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-02 03:38:50.484 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-02 03:38:50.956 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-02 03:38:51.428 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-02 03:38:51.906 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-02 03:38:52.378 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-02 03:38:52.853 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-02 03:38:53.329 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-02 03:38:53.805 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-02 03:38:54.283 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-02 03:38:54.759 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-02 03:38:55.237 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-02 03:38:55.714 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-02 03:38:56.192 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-02 03:38:56.667 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-02 03:38:57.145 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-02 03:38:57.623 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-02 03:38:58.100 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-02 03:38:58.577 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-02 03:38:59.049 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-02 03:38:59.520 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-02 03:38:59.991 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-02 03:39:00.462 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-02 03:39:00.932 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-02 03:39:01.403 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-02 03:39:01.874 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-02 03:39:02.345 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-02 03:39:02.816 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-02 03:39:03.287 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-02 03:39:03.757 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-02 03:39:04.232 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-02 03:39:04.703 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-02 03:39:05.174 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-02 03:39:05.647 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-02 03:39:06.116 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-02 03:39:06.587 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-02 03:39:07.058 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-02 03:39:07.528 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-02 03:39:08.005 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-02 03:39:08.482 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-02 03:39:08.960 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-02 03:39:09.437 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-02 03:39:09.915 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-02 03:39:10.393 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-02 03:39:10.869 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-02 03:39:11.341 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-02 03:39:11.815 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-02 03:39:12.292 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-02 03:39:12.768 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-02 03:39:13.245 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-02 03:39:13.723 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-02 03:39:14.198 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-02 03:39:14.667 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-02 03:39:15.137 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-02 03:39:15.608 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-02 03:39:16.086 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-02 03:39:16.561 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-02 03:39:17.034 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-02 03:39:17.512 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-02 03:39:17.984 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-02 03:39:18.455 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-02 03:39:18.926 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-02 03:39:19.396 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-02 03:39:19.867 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-02 03:39:20.338 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-02 03:39:20.810 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-02 03:39:21.280 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-02 03:39:21.750 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-02 03:39:22.221 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-02 03:39:22.692 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-02 03:39:23.167 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-02 03:39:23.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:23.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:23.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:23.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:23.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:23.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:23.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:23.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:23.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:23.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:23.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:23.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:23.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:23.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:23.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:39:23.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:39:23.255 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:39:23.255 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:39:23.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:23.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:23.640 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-02 03:39:24.118 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-02 03:39:24.596 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-02 03:39:25.074 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-02 03:39:25.552 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-02 03:39:26.029 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-02 03:39:26.507 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-02 03:39:26.986 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-02 03:39:27.464 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-02 03:39:27.941 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-02 03:39:28.419 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-02 03:39:28.893 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-02 03:39:29.360 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-02 03:39:29.827 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-02 03:39:30.295 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-02 03:39:30.762 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-02 03:39:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-02 03:39:31.697 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-02 03:39:32.164 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-02 03:39:32.631 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-02 03:39:33.099 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-02 03:39:33.566 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-02 03:39:34.034 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-02 03:39:34.502 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-02 03:39:34.973 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-02 03:39:35.445 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-02 03:39:35.922 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-02 03:39:36.400 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-02 03:39:36.877 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-02 03:39:37.355 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-02 03:39:37.832 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-02 03:39:38.307 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-02 03:39:38.780 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-02 03:39:39.254 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-02 03:39:39.733 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-02 03:39:40.210 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-03-02 03:39:40.688 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-03-02 03:39:40.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:40.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:40.962 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:39:40.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:40.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:39:40.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:39:40.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:39:40.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:39:40.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:39:40.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:39:40.967 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (TRX1@172.18.40.20:5700/1) RX TRXD message (ver=1 fn=25868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:40.967 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=25868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:39:45.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:39:45.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:39:45.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:39:45.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:39:45.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:39:45.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:39:45.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:39:45.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:39:45.986 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:45.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:39:45.987 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:39:45.988 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:39:45.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:39:45.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:39:45.989 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:45.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:39:45.989 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:39:45.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:39:45.989 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:39:45.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:39:45.991 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:39:45.991 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:39:45.991 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:45.992 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:39:45.992 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:39:45.992 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:39:45.992 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:45.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:39:45.993 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:39:45.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:39:45.993 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:39:45.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:39:45.995 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:39:45.995 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:39:45.995 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:45.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:45.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:39:45.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:39:45.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:39:45.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:39:45.996 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:39:45.996 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:39:45.996 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:39:50.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:39:50.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:39:51.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:39:51.002 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:39:51.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:39:51.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:39:51.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:39:51.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:39:51.009 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:51.009 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:39:51.010 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:39:51.013 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:39:51.013 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:39:51.013 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:39:51.014 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:51.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:39:51.014 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:39:51.014 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:39:51.015 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:39:51.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:39:51.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:39:51.016 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:39:51.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:51.018 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:39:51.018 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:39:51.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:39:51.018 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:39:51.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:39:51.018 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:39:51.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:39:51.018 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:39:51.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:39:51.022 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:39:51.022 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:39:51.022 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:39:51.027 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:39:51.510 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:39:51.548 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:39:51.550 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:39:51.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:51.551 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:39:51.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:51.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:51.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:51.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:51.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:51.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:51.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:51.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:51.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:51.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:51.596 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:39:51.596 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:39:51.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:51.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:51.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:51.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:51.987 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:39:52.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:52.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:52.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:52.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:52.466 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:39:52.943 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:39:53.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:53.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:53.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:53.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:53.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:53.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:53.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:53.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:53.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:53.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:53.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:53.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:53.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:53.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:53.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:53.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:53.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:53.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:39:53.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:39:53.078 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:39:53.079 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:39:53.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:53.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:53.412 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:39:53.881 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:39:54.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:54.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:54.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:54.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:54.352 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:39:54.828 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:39:55.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:55.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:55.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:55.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:55.305 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:39:55.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:55.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:55.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:55.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:55.342 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:39:55.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:55.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:55.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:55.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:55.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:55.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:55.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:55.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:55.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:55.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:55.367 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:39:55.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:39:55.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:55.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:55.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:55.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:55.777 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:39:56.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:39:56.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:39:56.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:39:56.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:39:56.248 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:39:56.719 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:39:57.196 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:39:57.672 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:39:58.150 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:39:58.627 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:39:58.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:58.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:58.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:58.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:58.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:58.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:58.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:58.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:39:58.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:39:58.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:39:58.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:39:58.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:58.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:39:58.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:39:58.818 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:39:58.818 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:39:58.862 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:39:58.862 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:39:58.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:58.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:39:59.099 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:39:59.577 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:40:00.056 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:40:00.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:00.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:00.139 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:40:00.143 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:40:00.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:40:00.144 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1958 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1958 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1958 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1958 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:00.144 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:05.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:40:05.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:40:05.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:40:05.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:40:05.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:40:05.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:40:05.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:40:05.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:40:05.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:05.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:40:05.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:40:05.167 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:40:05.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:40:05.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:40:05.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:05.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:40:05.168 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:40:05.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:40:05.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:40:05.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:05.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:40:05.171 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:40:05.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:40:05.171 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:05.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:40:05.171 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:40:05.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:40:05.171 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:40:05.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:05.173 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:40:05.173 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:40:05.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:40:05.174 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:05.174 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:40:05.174 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:40:05.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:40:05.174 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:40:05.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:40:05.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:40:05.178 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:40:05.178 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:40:05.178 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:05.183 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:40:05.666 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:40:05.708 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:40:05.711 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:40:05.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:05.713 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:40:05.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:05.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:05.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:05.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:05.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:05.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:05.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:05.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:05.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:05.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:05.769 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:40:05.769 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:40:05.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:05.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:05.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:05.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:06.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:40:06.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:06.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:06.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:06.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:06.621 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:40:07.100 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:40:07.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:07.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:07.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:07.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:07.574 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:40:08.050 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:40:08.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:08.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:08.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:08.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:08.527 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:40:09.002 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:40:09.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:09.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:09.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:09.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:09.480 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:40:09.958 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:40:10.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:10.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:10.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:10.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:10.436 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:40:10.910 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:40:11.388 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:40:11.865 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:40:12.343 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:40:12.821 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:40:13.299 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:40:13.776 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:40:14.254 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:40:14.732 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:40:15.209 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:40:15.687 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:40:16.165 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:40:16.642 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:40:17.119 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:40:17.597 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:40:18.075 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:40:18.552 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:40:19.029 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:40:19.507 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:40:19.985 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:40:20.462 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:40:20.940 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:40:21.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:21.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:21.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:21.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:21.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:21.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:21.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:21.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:21.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:21.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:21.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:21.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:21.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:21.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:21.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:40:21.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:40:21.313 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:40:21.314 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:40:21.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:21.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:21.415 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:40:21.894 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:40:22.372 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:40:22.850 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:40:23.328 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:40:23.800 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:40:24.277 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:40:24.755 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:40:25.234 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:40:25.713 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:40:26.193 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:40:26.672 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:40:27.150 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:40:27.627 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:40:28.105 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:40:28.583 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:40:29.061 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:40:29.539 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:40:30.017 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:40:30.496 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:40:30.974 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:40:31.452 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:40:31.931 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:40:32.410 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:40:32.888 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:40:33.366 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:40:33.845 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:40:34.320 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:40:34.789 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:40:35.265 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:40:35.744 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:40:36.216 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:40:36.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:36.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:36.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:36.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:36.569 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:40:36.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:36.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:36.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:36.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:36.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:36.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:36.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:36.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:36.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:36.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:36.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:40:36.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:40:36.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:36.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:36.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:36.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:36.686 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:40:37.157 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:40:37.628 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:40:38.099 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:40:38.570 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:40:39.040 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:40:39.512 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:40:39.982 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:40:40.453 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:40:40.923 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:40:41.396 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:40:41.874 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:40:42.350 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 03:40:42.823 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 03:40:43.293 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 03:40:43.763 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 03:40:44.235 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 03:40:44.706 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 03:40:45.177 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 03:40:45.656 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-02 03:40:46.134 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-02 03:40:46.611 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-02 03:40:47.083 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-02 03:40:47.553 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-02 03:40:48.024 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-02 03:40:48.500 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-02 03:40:48.972 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-02 03:40:49.447 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-02 03:40:49.923 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-02 03:40:50.401 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-02 03:40:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:50.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:50.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:50.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:50.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:50.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:50.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:50.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:50.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:50.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:50.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:50.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:50.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:50.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:50.874 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:40:50.874 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:40:50.878 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-02 03:40:50.925 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:40:50.925 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:40:50.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:50.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:51.350 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-02 03:40:51.828 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-02 03:40:52.307 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-02 03:40:52.785 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-02 03:40:53.259 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-02 03:40:53.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:53.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:53.648 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:40:53.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:53.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:53.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:53.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:53.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:40:53.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:40:53.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:40:53.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:40:53.653 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:40:53.653 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:40:53.653 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:53.653 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=10390 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:40:58.655 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:40:58.655 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:40:58.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:40:58.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:40:58.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:40:58.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:40:58.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:40:58.667 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:40:58.667 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:58.668 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:40:58.668 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:40:58.673 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:40:58.673 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:40:58.674 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:40:58.674 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:58.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:40:58.674 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:40:58.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:40:58.675 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:40:58.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:58.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:40:58.680 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:40:58.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:40:58.680 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:58.680 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:40:58.680 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:40:58.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:40:58.681 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:40:58.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:58.685 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:40:58.685 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:40:58.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:40:58.685 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:40:58.685 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:40:58.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:40:58.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:40:58.685 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:40:58.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:40:58.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:40:58.691 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:40:58.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:40:58.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:40:58.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:40:58.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:40:59.172 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:40:59.223 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:40:59.226 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:40:59.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:59.228 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:40:59.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:59.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:59.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:59.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:40:59.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:40:59.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:40:59.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:40:59.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:59.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:59.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:59.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:40:59.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:40:59.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:40:59.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:40:59.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:59.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:40:59.645 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:40:59.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:40:59.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:40:59.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:40:59.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:00.121 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:41:00.595 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:41:00.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:00.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:00.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:00.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:01.069 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:41:01.541 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:41:01.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:01.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:01.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:01.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:02.011 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:41:02.482 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:41:02.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:02.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:02.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:02.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:02.953 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:41:03.428 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:41:03.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:03.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:03.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:03.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:03.906 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:41:04.384 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:41:04.861 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:41:05.339 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:41:05.817 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:41:06.295 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:41:06.767 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:41:07.245 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:41:07.723 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:41:08.200 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:41:08.677 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:41:09.150 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:41:09.627 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:41:09.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:09.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:09.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:09.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:09.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:09.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:09.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:09.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:09.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:09.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:09.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:09.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:09.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:09.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:09.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:09.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:09.910 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:41:09.910 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:41:09.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:09.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:10.100 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:41:10.570 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:41:11.041 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:41:11.513 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:41:11.987 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:41:12.465 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:41:12.937 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:41:13.408 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:41:13.878 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:41:14.351 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:41:14.827 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:41:15.299 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:41:15.770 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:41:16.240 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:41:16.711 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:41:17.187 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:41:17.666 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:41:18.145 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:41:18.624 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:41:19.103 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:41:19.582 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:41:20.061 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:41:20.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:20.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:20.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:20.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:20.225 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:41:20.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:20.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:20.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:20.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:20.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:20.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:20.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:20.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:20.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:20.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:20.240 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:20.240 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:20.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:20.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:20.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:20.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:20.536 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:41:21.013 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:41:21.491 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:41:21.968 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-02 03:41:22.444 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-02 03:41:22.916 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-02 03:41:23.387 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-02 03:41:23.858 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-02 03:41:24.328 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-02 03:41:24.799 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-02 03:41:25.270 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-02 03:41:25.741 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-02 03:41:26.212 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-02 03:41:26.682 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-02 03:41:27.153 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-02 03:41:27.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:27.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:27.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:27.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:27.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:27.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:27.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:27.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:27.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:27.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:27.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:27.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:27.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:27.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:27.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:27.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:27.242 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:41:27.242 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:41:27.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:27.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:27.623 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-02 03:41:28.094 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-02 03:41:28.565 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-02 03:41:29.036 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-02 03:41:29.507 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-02 03:41:29.978 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-02 03:41:30.448 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-02 03:41:30.919 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-02 03:41:31.390 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-02 03:41:31.861 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-02 03:41:32.331 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-02 03:41:32.802 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-02 03:41:33.273 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-02 03:41:33.746 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-02 03:41:34.220 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-02 03:41:34.692 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-02 03:41:35.170 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-02 03:41:35.643 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-02 03:41:36.115 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-02 03:41:36.594 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-02 03:41:37.072 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-02 03:41:37.550 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-02 03:41:38.027 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-02 03:41:38.503 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-02 03:41:38.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:38.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:38.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:38.562 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:41:38.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:38.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:38.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:38.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:38.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:41:38.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:41:38.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:41:38.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:41:38.569 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:41:38.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:41:38.569 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:38.569 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=8584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:43.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:41:43.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:41:43.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:41:43.573 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:41:43.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:41:43.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:41:43.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:41:43.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:41:43.576 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:43.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:41:43.576 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:41:43.577 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:41:43.577 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:41:43.577 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:41:43.578 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:41:43.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:41:43.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:41:43.579 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:41:43.579 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:41:43.579 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.580 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:41:43.581 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:41:43.581 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:43.585 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:41:44.066 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:41:44.095 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:41:44.096 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:41:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:44.097 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:41:44.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:44.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:44.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:44.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:44.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:44.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:44.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:44.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:44.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:44.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:44.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:44.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:44.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:44.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:44.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:44.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:44.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:44.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:44.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:44.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:44.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:44.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:44.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:44.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:44.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:44.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:44.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:44.534 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:41:44.534 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:41:44.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:44.538 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:41:44.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:44.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:44.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:44.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:45.014 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:41:45.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:45.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:45.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:45.032 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:41:45.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:45.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:45.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:45.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:45.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:45.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:45.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:45.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:45.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:45.057 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:45.057 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:45.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:45.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:45.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.491 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:41:45.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:45.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:45.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:45.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:45.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:45.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:45.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:45.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:45.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:45.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:45.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:45.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:45.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:45.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:45.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:45.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:45.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:45.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:45.962 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:41:45.962 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:41:45.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:45.965 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:41:46.435 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:41:46.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:46.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:46.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:46.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:46.907 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:41:47.376 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:41:47.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:47.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:47.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:47.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:47.846 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:41:48.317 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:41:48.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:48.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:48.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:48.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:48.788 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:41:49.258 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:41:49.734 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:41:49.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:49.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:49.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:49.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:49.991 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:41:50.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:50.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:50.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:50.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:50.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:41:50.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:41:50.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:41:50.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:41:50.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:41:50.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:41:50.006 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:41:50.006 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1386 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:50.007 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1386 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:50.007 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1386 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:50.007 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1386 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:50.007 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1386 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:50.007 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=1386 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:41:55.005 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:41:55.005 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:41:55.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:41:55.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:41:55.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:41:55.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:41:55.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:41:55.022 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:41:55.022 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:55.022 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:41:55.023 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:41:55.025 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:41:55.025 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:41:55.025 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:41:55.025 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:55.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:41:55.026 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:41:55.026 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:41:55.026 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:41:55.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:55.028 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:41:55.028 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:41:55.028 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:41:55.028 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:55.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:41:55.028 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:41:55.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:41:55.029 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:41:55.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:55.031 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:41:55.031 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:41:55.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:41:55.031 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:41:55.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:41:55.031 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:41:55.032 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:41:55.032 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:41:55.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:41:55.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:41:55.035 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:41:55.035 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:41:55.035 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:41:55.040 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:41:55.514 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:41:55.558 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:41:55.559 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:41:55.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:55.559 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:41:55.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:55.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:55.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:55.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:55.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:55.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:55.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:55.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:55.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:55.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:55.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:55.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:55.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:55.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:55.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:55.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:55.984 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:41:56.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:56.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:56.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:56.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:56.453 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:41:56.923 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:41:57.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:57.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:57.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:57.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:57.394 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:41:57.866 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:41:58.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:58.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:58.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:58.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:58.336 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:41:58.811 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:41:58.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:58.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:58.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:58.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:58.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:58.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:58.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:58.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:41:58.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:41:58.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:41:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:41:58.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:58.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:41:58.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:41:58.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:41:58.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:41:58.903 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:41:58.903 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:41:58.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:58.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:41:59.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:41:59.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:41:59.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:41:59.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:41:59.288 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:41:59.760 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:42:00.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:00.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:00.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:00.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:00.230 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:42:00.701 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:42:01.172 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:42:01.643 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:42:02.114 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:42:02.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:02.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:02.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:02.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:02.242 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:42:02.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:02.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:02.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:02.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:02.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:02.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:02.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:02.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:02.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:02.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:02.266 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:02.266 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:02.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:02.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:02.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:02.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:02.592 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:42:03.069 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:42:03.547 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:42:04.020 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:42:04.498 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:42:04.976 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:42:05.453 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:42:05.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:05.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:05.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:05.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:05.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:05.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:05.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:05.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:05.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:05.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:05.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:05.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:05.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:05.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:05.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:05.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:05.923 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:42:05.924 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:42:05.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:05.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:05.926 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:42:06.395 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:42:06.865 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:42:07.334 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:42:07.803 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:42:08.276 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:42:08.749 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:42:09.227 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:42:09.701 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:42:10.174 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:42:10.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:10.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:10.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:10.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:10.257 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:42:10.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:10.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:10.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:10.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:10.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:10.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:42:10.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:42:10.270 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:10.270 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3286 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:15.269 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:42:15.269 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:42:15.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:15.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:15.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:15.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:15.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:15.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:42:15.290 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:15.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:42:15.290 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:42:15.293 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:42:15.293 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:42:15.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:42:15.293 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:15.294 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:42:15.294 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:15.294 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:42:15.294 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:42:15.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:42:15.297 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:42:15.297 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:42:15.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:42:15.299 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:42:15.299 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:42:15.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:15.301 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:42:15.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:42:15.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:42:15.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:42:15.301 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:42:15.302 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:42:15.302 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:42:15.302 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:15.307 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:42:15.784 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:42:15.835 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:42:15.836 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:42:15.838 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:42:15.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:15.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:15.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:15.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:15.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:15.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:15.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:15.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:15.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:15.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:15.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:15.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:15.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:15.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:15.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:15.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:15.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.261 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:42:16.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:16.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:16.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:16.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:16.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:16.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:16.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:16.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:16.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:16.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:16.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:16.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:16.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:16.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:16.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:16.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:16.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:16.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:16.350 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:42:16.350 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:42:16.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.734 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:42:16.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:16.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:16.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:16.911 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:42:16.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:16.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:16.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:16.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:16.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:16.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:16.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:16.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:16.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:16.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:16.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:16.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:16.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:16.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:16.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:17.208 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:42:17.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:17.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:17.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:17.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:17.685 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:42:18.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:18.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:18.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:18.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:18.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:18.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:18.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:18.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:18.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:18.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:18.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:18.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:18.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:18.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:18.107 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:18.107 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:18.155 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:42:18.155 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:42:18.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:18.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:18.158 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:42:18.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:18.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:18.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:18.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:18.632 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:42:19.105 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:42:19.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:19.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:19.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:19.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:19.577 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:42:20.050 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:42:20.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:20.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:20.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:20.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:20.528 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:42:21.006 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:42:21.478 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:42:21.949 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:42:22.428 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:42:22.906 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:42:23.384 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:42:23.861 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:42:24.339 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:42:24.817 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:42:25.292 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:42:25.762 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:42:26.241 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:42:26.720 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:42:27.196 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:42:27.670 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:42:28.139 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:42:28.609 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:42:29.080 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:42:29.550 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:42:30.025 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:42:30.504 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:42:30.979 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:42:31.448 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-02 03:42:31.922 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-02 03:42:32.391 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-02 03:42:32.863 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-02 03:42:33.336 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-02 03:42:33.807 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-02 03:42:34.278 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-02 03:42:34.749 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-02 03:42:35.220 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-02 03:42:35.690 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-02 03:42:36.168 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-02 03:42:36.647 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-02 03:42:37.119 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-02 03:42:37.589 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-02 03:42:38.060 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-02 03:42:38.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:38.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:38.104 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:42:38.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:38.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:38.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:38.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:38.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:38.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:42:38.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:42:38.110 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4908 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4908 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4908 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4908 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4908 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4908 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.111 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:38.112 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=4909 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:43.108 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:42:43.109 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:42:43.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:43.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:43.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:43.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:43.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:43.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:42:43.123 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:43.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:42:43.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:42:43.126 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:42:43.126 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:42:43.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:42:43.126 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:43.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:43.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:42:43.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:42:43.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:42:43.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:43.129 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:42:43.129 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:42:43.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:42:43.129 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:43.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:43.130 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:42:43.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:42:43.130 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:42:43.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:43.132 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:42:43.132 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:42:43.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:42:43.132 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:42:43.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:43.133 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:42:43.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:42:43.133 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:42:43.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:42:43.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:42:43.137 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:42:43.137 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:42:43.137 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:42:43.142 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:42:43.612 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:42:43.678 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:42:43.680 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:42:43.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:43.681 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:42:43.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:43.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:43.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:43.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:43.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:43.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:43.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:43.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:43.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:43.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:43.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:43.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:43.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:43.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:43.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:43.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:44.085 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:42:44.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:44.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:44.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:44.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:44.561 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:42:45.039 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:42:45.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:45.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:45.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:45.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:45.511 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:42:45.982 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:42:46.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:46.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:46.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:46.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:46.452 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:42:46.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:46.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:46.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:46.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:46.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:46.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:46.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:46.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:46.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:46.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:46.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:46.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:46.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:46.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:46.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:46.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:46.686 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:42:46.686 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:42:46.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:46.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:46.926 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:42:47.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:47.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:47.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:47.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:47.400 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:42:47.870 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:42:48.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:48.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:48.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:48.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:48.339 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:42:48.809 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:42:49.280 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:42:49.752 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:42:50.222 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:42:50.692 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:42:51.163 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:42:51.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:51.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:51.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:51.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:51.189 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:42:51.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:51.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:51.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:51.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:51.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:51.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:51.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:51.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:51.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:51.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:51.217 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:51.217 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:51.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:51.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:51.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:51.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:51.637 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:42:52.110 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:42:52.582 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:42:53.060 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:42:53.532 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:42:54.003 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:42:54.474 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:42:54.949 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:42:55.418 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:42:55.888 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:42:56.365 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:42:56.837 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:42:57.307 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:42:57.778 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:42:57.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:57.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:57.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:57.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:57.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:57.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:57.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:57.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:57.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:57.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:42:57.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:42:57.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:57.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:42:57.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:42:57.968 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:42:57.968 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:42:58.013 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:42:58.013 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:42:58.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:58.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:42:58.249 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:42:58.722 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:42:58.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:42:58.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:42:58.803 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:42:58.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:42:58.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:42:58.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:42:58.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:42:58.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:42:58.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:42:58.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:42:58.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:42:58.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:42:58.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:42:58.811 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:42:58.811 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.811 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.811 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.811 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.812 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.812 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.812 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:42:58.812 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3388 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:03.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:03.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:03.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:03.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:03.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:03.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:03.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:03.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:03.820 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:03.821 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:03.821 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:03.823 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:03.823 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:03.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:03.824 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:03.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:03.825 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:03.825 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:03.825 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:03.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:03.826 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:03.826 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:03.826 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:03.826 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:03.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:03.826 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:03.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:03.827 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:03.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:03.828 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:03.829 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:03.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:03.829 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:03.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:03.829 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:03.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:03.829 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:03.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.832 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:03.832 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:03.833 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:03.833 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:03.838 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:04.322 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:04.365 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:04.367 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:04.370 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:04.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:04.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:04.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:04.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:04.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:04.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:04.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:04.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:04.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:43:04.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:43:04.428 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:43:04.428 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:43:04.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:43:04.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:43:04.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:04.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:04.797 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:04.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:04.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:04.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:04.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:05.274 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:05.749 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:43:05.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:05.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:05.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:05.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:06.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:06.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:06.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:06.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:06.223 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:43:06.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:06.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:06.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:06.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:06.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:06.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:06.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:06.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:06.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:43:06.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:43:06.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:43:06.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:43:06.267 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:43:06.268 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-02 03:43:06.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:06.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:06.692 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:43:06.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:06.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:06.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:06.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:07.162 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:43:07.632 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:43:07.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:07.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:07.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:07.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:08.102 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:43:08.573 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:43:08.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:08.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:08.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:08.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:08.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:08.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:08.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:08.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:08.978 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:43:08.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:08.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:08.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:09.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:09.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:09.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:09.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:09.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:09.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:43:09.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:43:09.007 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:43:09.007 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:43:09.044 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:43:09.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:43:09.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:43:09.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:09.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:09.520 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:43:09.993 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:43:10.465 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:43:10.943 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:43:11.417 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:43:11.895 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:43:12.366 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:43:12.837 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:43:13.308 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:43:13.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:13.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:13.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:13.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:13.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:13.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:13.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:13.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:13.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:13.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:43:13.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:13.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:13.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:43:13.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:43:13.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:43:13.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:43:13.542 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.40.22:6700) Recv SETFH cmd
2026-03-02 03:43:13.543 [INFO] transceiver.py:201 (MS@172.18.40.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-02 03:43:13.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:13.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:43:13.779 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:43:14.254 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:43:14.725 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:43:15.196 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:43:15.667 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:43:15.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:43:15.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:43:15.750 [INFO] transceiver.py:205 (MS@172.18.40.22:6700) Frequency hopping disabled
2026-03-02 03:43:15.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:15.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:15.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:15.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:15.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:15.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:15.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:15.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:15.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:15.757 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:15.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:15.758 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.758 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.758 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.758 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.758 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:15.759 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=2571 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:20.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:20.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:20.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:20.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:20.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:20.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:20.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:20.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:20.780 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:20.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:20.780 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:20.784 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:20.784 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:20.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:20.784 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:20.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:20.784 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:20.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:20.785 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:20.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:20.787 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:20.787 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:20.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:20.791 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:20.791 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:20.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:20.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:20.796 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:20.796 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:20.796 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:20.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:20.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:20.801 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:21.276 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:21.330 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:21.332 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:21.333 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:21.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.750 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:21.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:21.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:21.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:21.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:21.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:21.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.223 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:22.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:22.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:22.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:22.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:22.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:22.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:22.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:22.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:22.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:22.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:22.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:22.640 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:22.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:22.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:22.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:22.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:22.640 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:27.642 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:27.642 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:27.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:27.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:27.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:27.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:27.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:27.668 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:27.669 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:27.669 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:27.669 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:27.675 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:27.675 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:27.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:27.676 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:27.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:27.677 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:27.677 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:27.677 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:27.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:27.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:27.681 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:27.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:27.681 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:27.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:27.681 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:27.682 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:27.682 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:27.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:27.684 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:27.684 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:27.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:27.685 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:27.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:27.685 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:27.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:27.685 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:27.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:27.690 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:27.690 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:27.690 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:27.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:28.171 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:28.224 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:28.227 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:28.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.229 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:28.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.641 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:28.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:28.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:28.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:28.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:28.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:28.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.114 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:29.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:29.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:29.585 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:43:29.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:29.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:29.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:29.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:29.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:29.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:29.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:29.590 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:29.590 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:29.590 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.591 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=411 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:29.592 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:34.588 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:34.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:34.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:34.592 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:34.592 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:34.592 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:34.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:34.598 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:34.598 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:34.598 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:34.598 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:34.599 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:34.599 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:34.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:34.600 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:34.600 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:34.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:34.601 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:34.601 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:34.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:34.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:34.602 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:34.603 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:34.607 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:35.080 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:35.133 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:35.134 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:35.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.136 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:35.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.548 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:35.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:35.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:35.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:35.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:35.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:35.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.021 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:36.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:36.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:36.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:36.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:36.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:36.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:36.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:36.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:36.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:36.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:36.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:36.463 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:36.463 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:41.464 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:41.464 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:41.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:41.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:41.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:41.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:41.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:41.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:41.479 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:41.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:41.480 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:41.482 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:41.482 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:41.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:41.483 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:41.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:41.483 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:41.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:41.483 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:41.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:41.485 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:41.485 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:41.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:41.487 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:41.487 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:41.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:41.489 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:41.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:41.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:41.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:41.489 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:41.490 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:41.490 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:41.490 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:41.495 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:41.972 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:42.006 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:42.007 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:42.007 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:42.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.443 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:42.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:42.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:42.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:42.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.914 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:42.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:42.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:43.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:43.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:43.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:43.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:43.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:43.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:43.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:43.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:43.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:43.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:43.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:43.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:43.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:43.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:43.328 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:48.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:48.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:48.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:48.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:48.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:48.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:48.340 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:48.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:48.341 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:48.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:48.341 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:48.343 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:48.343 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:48.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:48.344 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:48.344 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:48.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:48.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:48.344 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:48.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:48.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:48.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:48.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:48.349 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:48.349 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:48.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:48.352 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:48.352 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:48.352 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:48.357 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:48.830 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:48.876 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:48.876 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:48.877 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:48.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:48.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:48.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:48.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.304 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:49.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:49.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:49.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:49.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:49.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.777 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:49.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:49.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:50.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:50.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:50.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:50.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:50.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:50.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:50.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:50.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:50.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:50.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:50.204 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:50.204 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:50.204 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:50.205 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:43:55.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:55.202 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:55.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:55.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:55.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:55.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:55.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:55.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:55.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:55.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:43:55.224 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:43:55.226 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:43:55.226 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:43:55.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:55.226 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:55.226 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:43:55.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:55.227 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:43:55.227 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:43:55.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:55.228 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:43:55.228 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:43:55.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:55.228 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:55.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:43:55.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:55.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:43:55.229 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:43:55.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:55.230 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:43:55.230 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:43:55.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:43:55.232 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:43:55.232 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:43:55.232 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:43:55.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:43:55.237 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:43:55.705 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:43:55.766 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:43:55.768 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:43:55.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:55.769 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:43:55.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:43:55.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:55.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:55.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:55.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.174 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:43:56.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:56.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:56.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:56.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:56.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.646 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:43:56.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:56.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:57.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:57.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:57.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:57.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:43:57.118 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:43:57.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:43:57.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:43:57.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:43:57.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:43:57.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:43:57.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:43:57.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:43:57.127 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:43:57.127 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:43:57.127 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:43:57.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:02.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:02.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:02.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:02.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:02.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:02.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:02.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:02.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:02.138 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:02.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:02.138 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:02.140 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:02.141 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:02.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:02.141 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:02.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:02.142 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:02.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:02.142 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:02.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:02.143 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:02.143 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:02.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:02.145 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:02.145 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:02.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:02.148 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:02.148 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:02.148 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.153 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:02.635 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:02.661 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:02.662 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:02.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.662 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:02.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:02.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:02.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.103 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:44:03.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:03.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:03.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:03.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:03.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.576 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:44:03.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:03.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:03.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:03.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:03.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:03.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:03.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:03.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:03.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:03.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:03.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:03.975 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:03.975 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:03.975 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:03.975 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:03.975 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:03.975 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:03.975 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:08.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:08.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:08.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:08.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:08.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:08.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:08.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:08.997 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:08.998 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:08.998 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:08.998 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:09.001 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:09.001 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:09.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:09.001 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:09.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:09.001 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:09.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:09.001 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:09.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:09.004 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:09.004 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:09.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:09.006 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:09.006 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:09.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.008 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:09.008 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:09.008 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:09.008 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:09.013 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:09.488 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:09.534 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:09.536 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:09.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.539 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:09.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:09.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:09.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:09.611 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:14.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:14.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:14.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:14.616 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:14.616 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:14.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:14.621 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:14.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:14.621 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:14.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:14.622 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:14.625 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:14.625 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:14.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:14.627 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:14.628 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:14.628 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:14.628 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:14.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:14.628 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:14.628 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:14.628 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:14.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:14.630 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:14.630 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:14.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:14.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:14.634 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:14.634 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:14.634 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:14.639 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:15.114 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:15.167 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:15.167 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:15.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.170 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:15.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:15.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:15.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:15.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:15.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:15.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:15.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:15.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:15.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:15.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:15.271 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:15.271 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:15.271 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=138 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:20.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:20.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:20.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:20.279 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:20.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:20.280 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:20.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:20.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:20.286 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:20.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:20.286 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:20.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:20.289 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:20.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:20.289 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:20.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:20.289 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:20.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:20.290 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:20.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:20.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:20.294 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:20.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:20.297 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:20.297 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:20.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:20.298 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:20.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:20.298 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:20.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:20.298 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:20.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.301 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:20.301 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:20.301 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:20.302 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:20.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:20.306 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:20.783 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:20.816 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:20.816 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:20.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.817 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:20.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:20.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:20.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:20.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:20.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:20.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:20.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:20.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:20.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:20.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:20.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:20.891 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:25.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:25.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:25.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:25.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:25.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:25.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:25.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:25.903 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:25.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:25.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:25.906 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:25.906 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:25.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:25.906 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:25.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:25.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:25.907 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:25.907 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:25.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:25.909 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:25.909 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:25.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:25.909 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:25.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:25.909 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:25.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:25.910 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:25.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:25.912 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:25.912 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:25.912 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:25.912 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:25.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:25.913 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:25.913 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:25.913 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:25.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:25.916 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:25.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:25.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:25.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:25.916 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:25.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:25.917 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:25.917 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:25.917 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:25.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:25.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:25.922 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:26.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:26.453 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:26.455 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:26.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.457 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:26.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:26.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:26.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:26.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:26.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:26.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:26.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:26.531 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:26.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:26.531 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:26.531 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:26.531 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:31.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:31.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:31.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:31.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:31.537 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:31.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:31.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:31.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:31.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:31.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:31.541 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:31.546 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:31.546 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:31.547 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:31.547 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:31.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:31.547 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:31.547 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:31.547 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:31.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:31.550 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:31.550 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:31.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:31.551 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:31.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:31.551 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:31.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:31.551 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:31.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:31.554 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:31.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:31.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:31.559 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:31.559 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:31.559 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:31.564 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:32.038 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:32.089 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:32.090 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:32.091 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:32.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:32.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:32.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:32.158 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:32.158 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:32.158 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:37.160 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:37.160 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:37.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:37.160 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:37.160 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:37.160 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:37.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:37.166 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:37.167 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:37.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:37.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:37.168 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:37.169 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:37.169 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:37.169 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:37.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:37.170 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:37.170 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:37.170 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:37.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:37.172 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:37.172 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:37.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:37.172 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:37.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:37.172 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:37.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:37.172 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:37.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:37.175 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:37.175 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:37.175 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:37.175 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:37.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:37.175 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:37.175 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:37.175 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:37.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:37.180 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:37.180 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:37.180 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.185 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:37.662 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:37.704 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:37.705 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:37.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.706 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:37.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:37.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:37.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:37.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:37.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:37.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:37.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:37.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:37.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:37.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:37.807 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:37.807 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:37.807 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:37.807 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:37.807 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:37.807 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:42.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:42.809 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:42.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:42.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:42.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:42.813 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:42.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:42.815 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:42.815 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:42.815 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:42.815 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:42.816 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:42.816 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:42.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:42.818 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:42.818 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:42.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:42.819 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:42.820 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:42.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:42.820 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:42.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:42.820 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:42.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:42.820 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:42.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:42.822 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:42.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:42.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:42.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:42.822 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:42.823 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:42.823 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:42.823 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:42.828 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:43.305 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:43.353 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:43.355 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:43.355 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:43.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:43.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:43.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:43.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:43.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:43.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:43.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:43.439 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:43.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:43.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:43.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:43.439 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:43.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:48.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:48.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:48.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:48.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:48.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:48.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:48.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:48.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:48.453 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:48.454 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:48.454 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:48.458 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:48.458 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:48.458 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:48.458 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:48.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:48.459 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:48.459 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:48.459 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:48.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:48.462 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:48.462 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:48.463 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:48.463 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:48.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:48.463 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:48.463 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:48.463 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:48.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:48.466 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:48.466 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:48.466 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:48.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:48.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:48.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:48.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:48.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:48.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:48.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:48.471 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:48.471 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:48.471 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:48.476 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:48.945 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:49.005 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:49.007 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:49.008 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:49.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:49.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:44:49.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:44:49.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:44:49.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:44:49.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:44:49.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:44:49.013 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:44:49.013 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:44:49.418 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:44:49.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:49.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:49.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:49.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:49.891 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:44:50.369 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:44:50.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:50.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:50.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:50.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:50.846 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:44:51.320 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:44:51.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:51.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:51.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:51.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:51.798 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:44:52.275 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:44:52.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:44:52.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:44:52.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:52.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:52.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:52.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:52.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:52.460 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:52.460 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:52.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:52.460 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:52.460 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:52.460 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:52.460 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:52.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:52.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:52.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:52.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:52.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:52.461 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:57.462 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:57.462 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:57.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:57.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:57.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:57.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:57.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:57.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:57.478 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:57.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:44:57.478 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:44:57.482 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:44:57.482 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:44:57.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:57.482 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:57.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:57.482 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:44:57.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:44:57.482 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:44:57.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:57.485 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:44:57.485 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:44:57.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:57.485 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:57.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:57.485 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:44:57.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:44:57.485 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:44:57.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:57.487 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:44:57.487 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:44:57.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:57.489 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:44:57.490 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:44:57.490 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:44:57.490 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:44:57.495 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:44:57.967 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:44:58.019 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:44:58.021 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:44:58.022 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:44:58.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:58.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:44:58.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:44:58.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:44:58.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:44:58.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:44:58.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:44:58.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:44:58.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:44:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 03:44:58.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:44:58.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:44:58.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:44:58.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:44:58.444 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:44:58.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:58.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:58.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:58.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:58.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:44:58.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:44:58.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:44:58.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:44:58.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:44:58.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:44:58.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:44:58.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:44:58.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:44:58.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:44:58.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:44:58.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:44:58.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:44:58.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:44:58.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:44:58.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:44:58.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:44:58.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:44:58.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:44:58.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:44:58.596 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:44:58.596 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:44:58.597 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:44:58.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:58.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:58.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:58.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=239 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:44:58.597 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=239 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:03.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:03.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:03.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:03.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:03.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:03.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:03.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:03.610 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:03.610 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:03.610 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:03.610 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:03.613 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:03.613 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:45:03.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:03.615 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:45:03.615 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:45:03.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:03.615 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:03.615 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:03.615 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:45:03.616 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:03.616 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:45:03.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:03.617 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:03.617 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:45:03.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:45:03.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:45:03.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:45:03.620 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:45:03.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:03.625 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:45:04.102 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:45:04.141 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:45:04.142 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:45:04.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:04.143 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:45:04.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:04.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:04.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:04.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:04.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:04.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:04.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:04.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:04.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 03:45:04.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:04.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:04.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:04.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:04.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:04.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:04.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:04.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:04.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:04.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:04.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:04.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:04.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:04.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:04.572 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:45:04.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:04.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:04.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:04.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:05.048 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:45:05.517 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:45:05.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:05.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:05.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:05.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:05.986 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:45:06.457 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-02 03:45:06.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:06.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:06.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:06.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:06.927 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-02 03:45:07.398 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-02 03:45:07.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:07.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:07.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:07.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:07.869 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-02 03:45:08.340 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-02 03:45:08.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:08.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:08.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:08.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:08.810 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-02 03:45:09.281 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-02 03:45:09.757 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-02 03:45:10.235 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-02 03:45:10.712 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-02 03:45:11.190 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-02 03:45:11.668 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-02 03:45:12.146 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-02 03:45:12.624 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-02 03:45:13.097 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-02 03:45:13.567 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-02 03:45:14.042 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-02 03:45:14.519 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-02 03:45:14.997 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-02 03:45:15.475 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-02 03:45:15.953 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-02 03:45:16.431 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-02 03:45:16.908 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-02 03:45:17.386 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-02 03:45:17.864 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-02 03:45:18.342 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-02 03:45:18.819 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-02 03:45:19.297 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-02 03:45:19.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:19.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:19.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:19.594 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=3432 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.594 [WARNING] transceiver.py:257 (MS@172.18.40.22:6700) RX TRXD message (fn=3432 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:19.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:19.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:19.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:19.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:19.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:19.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:19.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:19.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:19.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:19.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:19.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:19.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:19.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:19.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:19.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:19.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:19.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:19.633 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:45:19.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:19.634 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:24.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:24.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:24.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:24.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:24.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:24.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:24.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:24.651 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:24.651 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:24.651 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:24.651 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:45:24.653 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:45:24.653 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:45:24.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:24.653 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:24.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:24.654 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:45:24.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:24.654 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:45:24.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:24.656 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:45:24.657 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:45:24.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:24.657 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:24.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:24.657 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:45:24.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:24.657 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:45:24.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:24.659 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:45:24.659 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:45:24.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:24.660 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:24.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:24.660 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:45:24.660 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:24.660 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:45:24.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:24.663 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:45:24.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:45:24.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:45:24.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:45:24.663 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:45:24.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:45:24.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:45:24.664 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:45:24.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:45:24.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:24.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:24.669 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:45:25.145 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:45:25.211 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:45:25.213 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:45:25.215 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:45:25.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:25.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:25.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:25.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:25.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:25.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:25.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:25.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:25.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:25.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 03:45:25.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:25.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:25.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:25.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:25.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:25.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 03:45:25.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:25.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:25.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:25.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:25.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:25.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:25.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:25.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:25.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:25.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:25.615 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:45:25.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:25.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:25.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:25.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:25.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:25.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:25.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:25.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:25.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:25.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:25.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:25.629 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:45:25.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:25.629 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:30.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:30.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:30.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:30.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:30.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:30.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:30.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:30.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:30.650 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:30.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:30.650 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:45:30.652 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:45:30.652 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:45:30.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:30.652 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:30.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:30.652 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:45:30.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:30.653 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:45:30.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:30.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:45:30.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:45:30.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:30.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:30.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:30.654 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:45:30.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:30.655 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:45:30.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:30.656 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:30.656 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:45:30.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.658 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:45:30.658 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:45:30.658 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:45:30.659 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:30.663 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-02 03:45:31.132 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-02 03:45:31.178 [DEBUG] fake_trx.py:278 (BTS@172.18.40.20:5700) Recv FAKE_TOA cmd
2026-03-02 03:45:31.179 [DEBUG] fake_trx.py:297 (BTS@172.18.40.20:5700) Recv FAKE_RSSI cmd
2026-03-02 03:45:31.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:31.179 [DEBUG] fake_trx.py:322 (BTS@172.18.40.20:5700) Recv FAKE_CI cmd
2026-03-02 03:45:31.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:31.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:31.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:31.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:31.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:31.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:31.198 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:31.198 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:31.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD HANDOVER
2026-03-02 03:45:31.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:31.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:31.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:31.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:31.601 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-02 03:45:31.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:31.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:31.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:31.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:32.071 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-02 03:45:32.544 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-02 03:45:32.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:32.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:32.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:32.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:33.018 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-02 03:45:33.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:33.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:33.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:33.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD ECHO
2026-03-02 03:45:33.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.40.22:6700) Ignore CMD SETSLOT
2026-03-02 03:45:33.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.40.22:6700) Recv RXTUNE cmd
2026-03-02 03:45:33.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.40.22:6700) Recv TXTUNE cmd
2026-03-02 03:45:33.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.40.22:6700) Recv POWERON CMD
2026-03-02 03:45:33.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.40.22:6700) Starting transceiver...
2026-03-02 03:45:33.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD NOHANDOVER
2026-03-02 03:45:33.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.40.22:6700) Recv POWEROFF cmd
2026-03-02 03:45:33.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.40.22:6700) Stopping transceiver...
2026-03-02 03:45:33.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:33.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:33.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:33.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:33.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:33.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:33.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:33.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:33.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:33.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:33.313 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:33.314 [WARNING] transceiver.py:257 (BTS@172.18.40.20:5700) RX TRXD message (ver=1 fn=575 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-02 03:45:38.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:38.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:38.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:38.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:38.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:38.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:38.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:38.318 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:38.318 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:38.318 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:38.318 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:38.319 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:38.319 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:45:38.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:38.319 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:38.320 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:38.320 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:38.320 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:45:38.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:45:38.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:45:38.322 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:45:38.322 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:45:38.322 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:38.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:38.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:38.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:38.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:38.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:38.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:38.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:38.323 [INFO] transceiver.py:246 Stopping clock generator
2026-03-02 03:45:43.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:43.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:43.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:43.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:43.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:43.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:43.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:43.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:43.330 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.40.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:43.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.40.20:5700) Recv SETFORMAT cmd
2026-03-02 03:45:43.330 [INFO] ctrl_if_trx.py:201 (BTS@172.18.40.20:5700) TRXD header version 1 -> 1
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.40.20:5700/1) Recv RXTUNE cmd
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.40.20:5700/1) Recv TXTUNE cmd
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:43.331 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.40.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.40.20:5700/1) Recv NOMTXPOWER cmd
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.40.20:5700/1) Recv SETFORMAT cmd
2026-03-02 03:45:43.331 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.40.20:5700/1) TRXD header version 1 -> 1
2026-03-02 03:45:43.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.40.20:5700/1) Recv SETPOWER cmd
2026-03-02 03:45:43.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.40.20:5700/2) Recv RXTUNE cmd
2026-03-02 03:45:43.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.40.20:5700/2) Recv TXTUNE cmd
2026-03-02 03:45:43.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:43.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.40.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:43.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:43.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.40.20:5700/2) Recv NOMTXPOWER cmd
2026-03-02 03:45:43.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.40.20:5700/2) Recv SETFORMAT cmd
2026-03-02 03:45:43.332 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.40.20:5700/2) TRXD header version 1 -> 1
2026-03-02 03:45:43.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.40.20:5700/2) Recv SETPOWER cmd
2026-03-02 03:45:43.333 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.40.20:5700/3) Recv RXTUNE cmd
2026-03-02 03:45:43.333 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.40.20:5700/3) Recv TXTUNE cmd
2026-03-02 03:45:43.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:43.334 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.40.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-02 03:45:43.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:43.334 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.40.20:5700/3) Recv NOMTXPOWER cmd
2026-03-02 03:45:43.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.40.20:5700/3) Recv SETFORMAT cmd
2026-03-02 03:45:43.334 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.40.20:5700/3) TRXD header version 1 -> 1
2026-03-02 03:45:43.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.40.20:5700/3) Recv SETPOWER cmd
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.40.20:5700) Recv RXTUNE cmd
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETTSC
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETTSC
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETTSC
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.40.20:5700) Recv TXTUNE cmd
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETRXGAIN
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETRXGAIN
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETRXGAIN
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETTSC
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.40.20:5700) Recv NOMTXPOWER cmd
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.40.20:5700) Recv SETPOWER cmd
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.336 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.40.20:5700) Recv POWERON CMD
2026-03-02 03:45:43.336 [INFO] ctrl_if_trx.py:109 (BTS@172.18.40.20:5700) Starting transceiver...
2026-03-02 03:45:43.336 [INFO] transceiver.py:243 Starting clock generator
2026-03-02 03:45:43.337 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-02 03:45:43.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETRXGAIN
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.40.20:5700/1) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.40.20:5700/1) Recv RFMUTE cmd
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.40.20:5700/2) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.40.20:5700/3) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.40.20:5700/2) Recv RFMUTE cmd
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.40.20:5700) Ignore CMD SETSLOT
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.40.20:5700/3) Recv RFMUTE cmd
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.40.20:5700) Recv RFMUTE cmd
2026-03-02 03:45:43.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.40.20:5700) Recv POWEROFF cmd
2026-03-02 03:45:43.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.40.20:5700) Stopping transceiver...
2026-03-02 03:45:43.338 [INFO] transceiver.py:246 Stopping clock generator